Lines Matching +full:gcc +full:- +full:sm8150
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sm8150.h>
19 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
30 xo_board: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <38400000>;
34 clock-output-names = "xo_board";
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <32764>;
41 clock-output-names = "sleep_clk";
46 #address-cells = <2>;
47 #size-cells = <0>;
54 enable-method = "psci";
55 capacity-dmips-mhz = <488>;
56 dynamic-power-coefficient = <232>;
57 next-level-cache = <&L2_0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
62 power-domains = <&CPU_PD0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
83 enable-method = "psci";
84 capacity-dmips-mhz = <488>;
85 dynamic-power-coefficient = <232>;
86 next-level-cache = <&L2_100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 operating-points-v2 = <&cpu0_opp_table>;
91 power-domains = <&CPU_PD1>;
92 power-domain-names = "psci";
93 #cooling-cells = <2>;
94 L2_100: l2-cache {
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&L3_0>;
107 enable-method = "psci";
108 capacity-dmips-mhz = <488>;
109 dynamic-power-coefficient = <232>;
110 next-level-cache = <&L2_200>;
111 qcom,freq-domain = <&cpufreq_hw 0>;
112 operating-points-v2 = <&cpu0_opp_table>;
115 power-domains = <&CPU_PD2>;
116 power-domain-names = "psci";
117 #cooling-cells = <2>;
118 L2_200: l2-cache {
120 cache-level = <2>;
121 cache-unified;
122 next-level-cache = <&L3_0>;
131 enable-method = "psci";
132 capacity-dmips-mhz = <488>;
133 dynamic-power-coefficient = <232>;
134 next-level-cache = <&L2_300>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
136 operating-points-v2 = <&cpu0_opp_table>;
139 power-domains = <&CPU_PD3>;
140 power-domain-names = "psci";
141 #cooling-cells = <2>;
142 L2_300: l2-cache {
144 cache-level = <2>;
145 cache-unified;
146 next-level-cache = <&L3_0>;
155 enable-method = "psci";
156 capacity-dmips-mhz = <1024>;
157 dynamic-power-coefficient = <369>;
158 next-level-cache = <&L2_400>;
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 operating-points-v2 = <&cpu4_opp_table>;
163 power-domains = <&CPU_PD4>;
164 power-domain-names = "psci";
165 #cooling-cells = <2>;
166 L2_400: l2-cache {
168 cache-level = <2>;
169 cache-unified;
170 next-level-cache = <&L3_0>;
179 enable-method = "psci";
180 capacity-dmips-mhz = <1024>;
181 dynamic-power-coefficient = <369>;
182 next-level-cache = <&L2_500>;
183 qcom,freq-domain = <&cpufreq_hw 1>;
184 operating-points-v2 = <&cpu4_opp_table>;
187 power-domains = <&CPU_PD5>;
188 power-domain-names = "psci";
189 #cooling-cells = <2>;
190 L2_500: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&L3_0>;
203 enable-method = "psci";
204 capacity-dmips-mhz = <1024>;
205 dynamic-power-coefficient = <369>;
206 next-level-cache = <&L2_600>;
207 qcom,freq-domain = <&cpufreq_hw 1>;
208 operating-points-v2 = <&cpu4_opp_table>;
211 power-domains = <&CPU_PD6>;
212 power-domain-names = "psci";
213 #cooling-cells = <2>;
214 L2_600: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&L3_0>;
227 enable-method = "psci";
228 capacity-dmips-mhz = <1024>;
229 dynamic-power-coefficient = <421>;
230 next-level-cache = <&L2_700>;
231 qcom,freq-domain = <&cpufreq_hw 2>;
232 operating-points-v2 = <&cpu7_opp_table>;
235 power-domains = <&CPU_PD7>;
236 power-domain-names = "psci";
237 #cooling-cells = <2>;
238 L2_700: l2-cache {
240 cache-level = <2>;
241 cache-unified;
242 next-level-cache = <&L3_0>;
246 cpu-map {
282 idle-states {
283 entry-method = "psci";
285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
286 compatible = "arm,idle-state";
287 idle-state-name = "little-rail-power-collapse";
288 arm,psci-suspend-param = <0x40000004>;
289 entry-latency-us = <355>;
290 exit-latency-us = <909>;
291 min-residency-us = <3934>;
292 local-timer-stop;
295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
296 compatible = "arm,idle-state";
297 idle-state-name = "big-rail-power-collapse";
298 arm,psci-suspend-param = <0x40000004>;
299 entry-latency-us = <241>;
300 exit-latency-us = <1461>;
301 min-residency-us = <4488>;
302 local-timer-stop;
306 domain-idle-states {
307 CLUSTER_SLEEP_0: cluster-sleep-0 {
308 compatible = "domain-idle-state";
309 arm,psci-suspend-param = <0x4100c244>;
310 entry-latency-us = <3263>;
311 exit-latency-us = <6562>;
312 min-residency-us = <9987>;
317 cpu0_opp_table: opp-table-cpu0 {
318 compatible = "operating-points-v2";
319 opp-shared;
321 cpu0_opp1: opp-300000000 {
322 opp-hz = /bits/ 64 <300000000>;
323 opp-peak-kBps = <800000 9600000>;
326 cpu0_opp2: opp-403200000 {
327 opp-hz = /bits/ 64 <403200000>;
328 opp-peak-kBps = <800000 9600000>;
331 cpu0_opp3: opp-499200000 {
332 opp-hz = /bits/ 64 <499200000>;
333 opp-peak-kBps = <800000 12902400>;
336 cpu0_opp4: opp-576000000 {
337 opp-hz = /bits/ 64 <576000000>;
338 opp-peak-kBps = <800000 12902400>;
341 cpu0_opp5: opp-672000000 {
342 opp-hz = /bits/ 64 <672000000>;
343 opp-peak-kBps = <800000 15974400>;
346 cpu0_opp6: opp-768000000 {
347 opp-hz = /bits/ 64 <768000000>;
348 opp-peak-kBps = <1804000 19660800>;
351 cpu0_opp7: opp-844800000 {
352 opp-hz = /bits/ 64 <844800000>;
353 opp-peak-kBps = <1804000 19660800>;
356 cpu0_opp8: opp-940800000 {
357 opp-hz = /bits/ 64 <940800000>;
358 opp-peak-kBps = <1804000 22732800>;
361 cpu0_opp9: opp-1036800000 {
362 opp-hz = /bits/ 64 <1036800000>;
363 opp-peak-kBps = <1804000 22732800>;
366 cpu0_opp10: opp-1113600000 {
367 opp-hz = /bits/ 64 <1113600000>;
368 opp-peak-kBps = <2188000 25804800>;
371 cpu0_opp11: opp-1209600000 {
372 opp-hz = /bits/ 64 <1209600000>;
373 opp-peak-kBps = <2188000 31948800>;
376 cpu0_opp12: opp-1305600000 {
377 opp-hz = /bits/ 64 <1305600000>;
378 opp-peak-kBps = <3072000 31948800>;
381 cpu0_opp13: opp-1382400000 {
382 opp-hz = /bits/ 64 <1382400000>;
383 opp-peak-kBps = <3072000 31948800>;
386 cpu0_opp14: opp-1478400000 {
387 opp-hz = /bits/ 64 <1478400000>;
388 opp-peak-kBps = <3072000 31948800>;
391 cpu0_opp15: opp-1555200000 {
392 opp-hz = /bits/ 64 <1555200000>;
393 opp-peak-kBps = <3072000 40550400>;
396 cpu0_opp16: opp-1632000000 {
397 opp-hz = /bits/ 64 <1632000000>;
398 opp-peak-kBps = <3072000 40550400>;
401 cpu0_opp17: opp-1708800000 {
402 opp-hz = /bits/ 64 <1708800000>;
403 opp-peak-kBps = <3072000 43008000>;
406 cpu0_opp18: opp-1785600000 {
407 opp-hz = /bits/ 64 <1785600000>;
408 opp-peak-kBps = <3072000 43008000>;
412 cpu4_opp_table: opp-table-cpu4 {
413 compatible = "operating-points-v2";
414 opp-shared;
416 cpu4_opp1: opp-710400000 {
417 opp-hz = /bits/ 64 <710400000>;
418 opp-peak-kBps = <1804000 15974400>;
421 cpu4_opp2: opp-825600000 {
422 opp-hz = /bits/ 64 <825600000>;
423 opp-peak-kBps = <2188000 19660800>;
426 cpu4_opp3: opp-940800000 {
427 opp-hz = /bits/ 64 <940800000>;
428 opp-peak-kBps = <2188000 22732800>;
431 cpu4_opp4: opp-1056000000 {
432 opp-hz = /bits/ 64 <1056000000>;
433 opp-peak-kBps = <3072000 25804800>;
436 cpu4_opp5: opp-1171200000 {
437 opp-hz = /bits/ 64 <1171200000>;
438 opp-peak-kBps = <3072000 31948800>;
441 cpu4_opp6: opp-1286400000 {
442 opp-hz = /bits/ 64 <1286400000>;
443 opp-peak-kBps = <4068000 31948800>;
446 cpu4_opp7: opp-1401600000 {
447 opp-hz = /bits/ 64 <1401600000>;
448 opp-peak-kBps = <4068000 31948800>;
451 cpu4_opp8: opp-1497600000 {
452 opp-hz = /bits/ 64 <1497600000>;
453 opp-peak-kBps = <4068000 40550400>;
456 cpu4_opp9: opp-1612800000 {
457 opp-hz = /bits/ 64 <1612800000>;
458 opp-peak-kBps = <4068000 40550400>;
461 cpu4_opp10: opp-1708800000 {
462 opp-hz = /bits/ 64 <1708800000>;
463 opp-peak-kBps = <4068000 43008000>;
466 cpu4_opp11: opp-1804800000 {
467 opp-hz = /bits/ 64 <1804800000>;
468 opp-peak-kBps = <6220000 43008000>;
471 cpu4_opp12: opp-1920000000 {
472 opp-hz = /bits/ 64 <1920000000>;
473 opp-peak-kBps = <6220000 49152000>;
476 cpu4_opp13: opp-2016000000 {
477 opp-hz = /bits/ 64 <2016000000>;
478 opp-peak-kBps = <7216000 49152000>;
481 cpu4_opp14: opp-2131200000 {
482 opp-hz = /bits/ 64 <2131200000>;
483 opp-peak-kBps = <8368000 49152000>;
486 cpu4_opp15: opp-2227200000 {
487 opp-hz = /bits/ 64 <2227200000>;
488 opp-peak-kBps = <8368000 51609600>;
491 cpu4_opp16: opp-2323200000 {
492 opp-hz = /bits/ 64 <2323200000>;
493 opp-peak-kBps = <8368000 51609600>;
496 cpu4_opp17: opp-2419200000 {
497 opp-hz = /bits/ 64 <2419200000>;
498 opp-peak-kBps = <8368000 51609600>;
502 cpu7_opp_table: opp-table-cpu7 {
503 compatible = "operating-points-v2";
504 opp-shared;
506 cpu7_opp1: opp-825600000 {
507 opp-hz = /bits/ 64 <825600000>;
508 opp-peak-kBps = <2188000 19660800>;
511 cpu7_opp2: opp-940800000 {
512 opp-hz = /bits/ 64 <940800000>;
513 opp-peak-kBps = <2188000 22732800>;
516 cpu7_opp3: opp-1056000000 {
517 opp-hz = /bits/ 64 <1056000000>;
518 opp-peak-kBps = <3072000 25804800>;
521 cpu7_opp4: opp-1171200000 {
522 opp-hz = /bits/ 64 <1171200000>;
523 opp-peak-kBps = <3072000 31948800>;
526 cpu7_opp5: opp-1286400000 {
527 opp-hz = /bits/ 64 <1286400000>;
528 opp-peak-kBps = <4068000 31948800>;
531 cpu7_opp6: opp-1401600000 {
532 opp-hz = /bits/ 64 <1401600000>;
533 opp-peak-kBps = <4068000 31948800>;
536 cpu7_opp7: opp-1497600000 {
537 opp-hz = /bits/ 64 <1497600000>;
538 opp-peak-kBps = <4068000 40550400>;
541 cpu7_opp8: opp-1612800000 {
542 opp-hz = /bits/ 64 <1612800000>;
543 opp-peak-kBps = <4068000 40550400>;
546 cpu7_opp9: opp-1708800000 {
547 opp-hz = /bits/ 64 <1708800000>;
548 opp-peak-kBps = <4068000 43008000>;
551 cpu7_opp10: opp-1804800000 {
552 opp-hz = /bits/ 64 <1804800000>;
553 opp-peak-kBps = <6220000 43008000>;
556 cpu7_opp11: opp-1920000000 {
557 opp-hz = /bits/ 64 <1920000000>;
558 opp-peak-kBps = <6220000 49152000>;
561 cpu7_opp12: opp-2016000000 {
562 opp-hz = /bits/ 64 <2016000000>;
563 opp-peak-kBps = <7216000 49152000>;
566 cpu7_opp13: opp-2131200000 {
567 opp-hz = /bits/ 64 <2131200000>;
568 opp-peak-kBps = <8368000 49152000>;
571 cpu7_opp14: opp-2227200000 {
572 opp-hz = /bits/ 64 <2227200000>;
573 opp-peak-kBps = <8368000 51609600>;
576 cpu7_opp15: opp-2323200000 {
577 opp-hz = /bits/ 64 <2323200000>;
578 opp-peak-kBps = <8368000 51609600>;
581 cpu7_opp16: opp-2419200000 {
582 opp-hz = /bits/ 64 <2419200000>;
583 opp-peak-kBps = <8368000 51609600>;
586 cpu7_opp17: opp-2534400000 {
587 opp-hz = /bits/ 64 <2534400000>;
588 opp-peak-kBps = <8368000 51609600>;
591 cpu7_opp18: opp-2649600000 {
592 opp-hz = /bits/ 64 <2649600000>;
593 opp-peak-kBps = <8368000 51609600>;
596 cpu7_opp19: opp-2745600000 {
597 opp-hz = /bits/ 64 <2745600000>;
598 opp-peak-kBps = <8368000 51609600>;
601 cpu7_opp20: opp-2841600000 {
602 opp-hz = /bits/ 64 <2841600000>;
603 opp-peak-kBps = <8368000 51609600>;
609 compatible = "qcom,scm-sm8150", "qcom,scm";
610 #reset-cells = <1>;
621 compatible = "arm,armv8-pmuv3";
626 compatible = "arm,psci-1.0";
629 CPU_PD0: power-domain-cpu0 {
630 #power-domain-cells = <0>;
631 power-domains = <&CLUSTER_PD>;
632 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 CPU_PD1: power-domain-cpu1 {
636 #power-domain-cells = <0>;
637 power-domains = <&CLUSTER_PD>;
638 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 CPU_PD2: power-domain-cpu2 {
642 #power-domain-cells = <0>;
643 power-domains = <&CLUSTER_PD>;
644 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 CPU_PD3: power-domain-cpu3 {
648 #power-domain-cells = <0>;
649 power-domains = <&CLUSTER_PD>;
650 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 CPU_PD4: power-domain-cpu4 {
654 #power-domain-cells = <0>;
655 power-domains = <&CLUSTER_PD>;
656 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 CPU_PD5: power-domain-cpu5 {
660 #power-domain-cells = <0>;
661 power-domains = <&CLUSTER_PD>;
662 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 CPU_PD6: power-domain-cpu6 {
666 #power-domain-cells = <0>;
667 power-domains = <&CLUSTER_PD>;
668 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 CPU_PD7: power-domain-cpu7 {
672 #power-domain-cells = <0>;
673 power-domains = <&CLUSTER_PD>;
674 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 CLUSTER_PD: power-domain-cpu-cluster0 {
678 #power-domain-cells = <0>;
679 domain-idle-states = <&CLUSTER_SLEEP_0>;
683 reserved-memory {
684 #address-cells = <2>;
685 #size-cells = <2>;
690 no-map;
695 no-map;
700 no-map;
704 compatible = "qcom,cmd-db";
706 no-map;
711 no-map;
716 no-map;
720 compatible = "qcom,rmtfs-mem";
722 no-map;
724 qcom,client-id = <1>;
730 no-map;
735 no-map;
740 no-map;
745 no-map;
750 no-map;
755 no-map;
760 no-map;
765 no-map;
770 no-map;
775 no-map;
780 no-map;
785 no-map;
790 no-map;
796 memory-region = <&smem_mem>;
800 smp2p-cdsp {
808 qcom,local-pid = <0>;
809 qcom,remote-pid = <5>;
811 cdsp_smp2p_out: master-kernel {
812 qcom,entry-name = "master-kernel";
813 #qcom,smem-state-cells = <1>;
816 cdsp_smp2p_in: slave-kernel {
817 qcom,entry-name = "slave-kernel";
819 interrupt-controller;
820 #interrupt-cells = <2>;
824 smp2p-lpass {
832 qcom,local-pid = <0>;
833 qcom,remote-pid = <2>;
835 adsp_smp2p_out: master-kernel {
836 qcom,entry-name = "master-kernel";
837 #qcom,smem-state-cells = <1>;
840 adsp_smp2p_in: slave-kernel {
841 qcom,entry-name = "slave-kernel";
843 interrupt-controller;
844 #interrupt-cells = <2>;
848 smp2p-mpss {
856 qcom,local-pid = <0>;
857 qcom,remote-pid = <1>;
859 modem_smp2p_out: master-kernel {
860 qcom,entry-name = "master-kernel";
861 #qcom,smem-state-cells = <1>;
864 modem_smp2p_in: slave-kernel {
865 qcom,entry-name = "slave-kernel";
867 interrupt-controller;
868 #interrupt-cells = <2>;
872 smp2p-slpi {
880 qcom,local-pid = <0>;
881 qcom,remote-pid = <3>;
883 slpi_smp2p_out: master-kernel {
884 qcom,entry-name = "master-kernel";
885 #qcom,smem-state-cells = <1>;
888 slpi_smp2p_in: slave-kernel {
889 qcom,entry-name = "slave-kernel";
891 interrupt-controller;
892 #interrupt-cells = <2>;
897 #address-cells = <2>;
898 #size-cells = <2>;
900 dma-ranges = <0 0 0 0 0x10 0>;
901 compatible = "simple-bus";
903 gcc: clock-controller@100000 {
904 compatible = "qcom,gcc-sm8150";
906 #clock-cells = <1>;
907 #reset-cells = <1>;
908 #power-domain-cells = <1>;
909 clock-names = "bi_tcxo",
915 gpi_dma0: dma-controller@800000 {
916 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
931 dma-channels = <13>;
932 dma-channel-mask = <0xfa>;
934 #dma-cells = <3>;
939 compatible = "qcom,sm8150-ethqos";
942 reg-names = "stmmaceth", "rgmii";
943 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
944 clocks = <&gcc GCC_EMAC_AXI_CLK>,
945 <&gcc GCC_EMAC_SLV_AHB_CLK>,
946 <&gcc GCC_EMAC_PTP_CLK>,
947 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupt-names = "macirq", "eth_lpi";
952 power-domains = <&gcc EMAC_GDSC>;
953 resets = <&gcc GCC_EMAC_BCR>;
958 rx-fifo-depth = <4096>;
959 tx-fifo-depth = <4096>;
965 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
967 #address-cells = <1>;
968 #size-cells = <1>;
977 compatible = "qcom,geni-se-qup";
979 clock-names = "m-ahb", "s-ahb";
980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
983 #address-cells = <2>;
984 #size-cells = <2>;
989 compatible = "qcom,geni-i2c";
991 clock-names = "se";
992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dma-names = "tx", "rx";
996 pinctrl-names = "default";
997 pinctrl-0 = <&qup_i2c0_default>;
999 #address-cells = <1>;
1000 #size-cells = <0>;
1005 compatible = "qcom,geni-spi";
1007 reg-names = "se";
1008 clock-names = "se";
1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dma-names = "tx", "rx";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&qup_spi0_default>;
1016 spi-max-frequency = <50000000>;
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1023 compatible = "qcom,geni-i2c";
1025 clock-names = "se";
1026 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dma-names = "tx", "rx";
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&qup_i2c1_default>;
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1039 compatible = "qcom,geni-spi";
1041 reg-names = "se";
1042 clock-names = "se";
1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dma-names = "tx", "rx";
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&qup_spi1_default>;
1050 spi-max-frequency = <50000000>;
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1057 compatible = "qcom,geni-i2c";
1059 clock-names = "se";
1060 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dma-names = "tx", "rx";
1064 pinctrl-names = "default";
1065 pinctrl-0 = <&qup_i2c2_default>;
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1073 compatible = "qcom,geni-spi";
1075 reg-names = "se";
1076 clock-names = "se";
1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dma-names = "tx", "rx";
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&qup_spi2_default>;
1084 spi-max-frequency = <50000000>;
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1091 compatible = "qcom,geni-i2c";
1093 clock-names = "se";
1094 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dma-names = "tx", "rx";
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_i2c3_default>;
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1107 compatible = "qcom,geni-spi";
1109 reg-names = "se";
1110 clock-names = "se";
1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dma-names = "tx", "rx";
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&qup_spi3_default>;
1118 spi-max-frequency = <50000000>;
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1125 compatible = "qcom,geni-i2c";
1127 clock-names = "se";
1128 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dma-names = "tx", "rx";
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c4_default>;
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1141 compatible = "qcom,geni-spi";
1143 reg-names = "se";
1144 clock-names = "se";
1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dma-names = "tx", "rx";
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&qup_spi4_default>;
1152 spi-max-frequency = <50000000>;
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1159 compatible = "qcom,geni-i2c";
1161 clock-names = "se";
1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dma-names = "tx", "rx";
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_i2c5_default>;
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1175 compatible = "qcom,geni-spi";
1177 reg-names = "se";
1178 clock-names = "se";
1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dma-names = "tx", "rx";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&qup_spi5_default>;
1186 spi-max-frequency = <50000000>;
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1193 compatible = "qcom,geni-i2c";
1195 clock-names = "se";
1196 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dma-names = "tx", "rx";
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&qup_i2c6_default>;
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1209 compatible = "qcom,geni-spi";
1211 reg-names = "se";
1212 clock-names = "se";
1213 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dma-names = "tx", "rx";
1217 pinctrl-names = "default";
1218 pinctrl-0 = <&qup_spi6_default>;
1220 spi-max-frequency = <50000000>;
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1227 compatible = "qcom,geni-i2c";
1229 clock-names = "se";
1230 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dma-names = "tx", "rx";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&qup_i2c7_default>;
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1243 compatible = "qcom,geni-spi";
1245 reg-names = "se";
1246 clock-names = "se";
1247 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dma-names = "tx", "rx";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&qup_spi7_default>;
1254 spi-max-frequency = <50000000>;
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1261 gpi_dma1: dma-controller@a00000 {
1262 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1277 dma-channels = <13>;
1278 dma-channel-mask = <0xfa>;
1280 #dma-cells = <3>;
1285 compatible = "qcom,geni-se-qup";
1287 clock-names = "m-ahb", "s-ahb";
1288 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1289 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1291 #address-cells = <2>;
1292 #size-cells = <2>;
1297 compatible = "qcom,geni-i2c";
1299 clock-names = "se";
1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dma-names = "tx", "rx";
1304 pinctrl-names = "default";
1305 pinctrl-0 = <&qup_i2c8_default>;
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1313 compatible = "qcom,geni-spi";
1315 reg-names = "se";
1316 clock-names = "se";
1317 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dma-names = "tx", "rx";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_spi8_default>;
1324 spi-max-frequency = <50000000>;
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1331 compatible = "qcom,geni-i2c";
1333 clock-names = "se";
1334 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dma-names = "tx", "rx";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&qup_i2c9_default>;
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1347 compatible = "qcom,geni-spi";
1349 reg-names = "se";
1350 clock-names = "se";
1351 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dma-names = "tx", "rx";
1355 pinctrl-names = "default";
1356 pinctrl-0 = <&qup_spi9_default>;
1358 spi-max-frequency = <50000000>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 compatible = "qcom,geni-uart";
1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1368 clock-names = "se";
1369 pinctrl-0 = <&qup_uart9_default>;
1370 pinctrl-names = "default";
1376 compatible = "qcom,geni-i2c";
1378 clock-names = "se";
1379 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dma-names = "tx", "rx";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_i2c10_default>;
1386 #address-cells = <1>;
1387 #size-cells = <0>;
1392 compatible = "qcom,geni-spi";
1394 reg-names = "se";
1395 clock-names = "se";
1396 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dma-names = "tx", "rx";
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&qup_spi10_default>;
1403 spi-max-frequency = <50000000>;
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1410 compatible = "qcom,geni-i2c";
1412 clock-names = "se";
1413 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dma-names = "tx", "rx";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&qup_i2c11_default>;
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1426 compatible = "qcom,geni-spi";
1428 reg-names = "se";
1429 clock-names = "se";
1430 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dma-names = "tx", "rx";
1434 pinctrl-names = "default";
1435 pinctrl-0 = <&qup_spi11_default>;
1437 spi-max-frequency = <50000000>;
1438 #address-cells = <1>;
1439 #size-cells = <0>;
1444 compatible = "qcom,geni-debug-uart";
1446 clock-names = "se";
1447 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1453 compatible = "qcom,geni-i2c";
1455 clock-names = "se";
1456 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dma-names = "tx", "rx";
1460 pinctrl-names = "default";
1461 pinctrl-0 = <&qup_i2c12_default>;
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1469 compatible = "qcom,geni-spi";
1471 reg-names = "se";
1472 clock-names = "se";
1473 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dma-names = "tx", "rx";
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&qup_spi12_default>;
1480 spi-max-frequency = <50000000>;
1481 #address-cells = <1>;
1482 #size-cells = <0>;
1487 compatible = "qcom,geni-i2c";
1489 clock-names = "se";
1490 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dma-names = "tx", "rx";
1494 pinctrl-names = "default";
1495 pinctrl-0 = <&qup_i2c16_default>;
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1503 compatible = "qcom,geni-spi";
1505 reg-names = "se";
1506 clock-names = "se";
1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dma-names = "tx", "rx";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_spi16_default>;
1514 spi-max-frequency = <50000000>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1521 gpi_dma2: dma-controller@c00000 {
1522 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1537 dma-channels = <13>;
1538 dma-channel-mask = <0xfa>;
1540 #dma-cells = <3>;
1545 compatible = "qcom,geni-se-qup";
1548 clock-names = "m-ahb", "s-ahb";
1549 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1550 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1552 #address-cells = <2>;
1553 #size-cells = <2>;
1558 compatible = "qcom,geni-i2c";
1560 clock-names = "se";
1561 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dma-names = "tx", "rx";
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c17_default>;
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1574 compatible = "qcom,geni-spi";
1576 reg-names = "se";
1577 clock-names = "se";
1578 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dma-names = "tx", "rx";
1582 pinctrl-names = "default";
1583 pinctrl-0 = <&qup_spi17_default>;
1585 spi-max-frequency = <50000000>;
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1592 compatible = "qcom,geni-i2c";
1594 clock-names = "se";
1595 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dma-names = "tx", "rx";
1599 pinctrl-names = "default";
1600 pinctrl-0 = <&qup_i2c18_default>;
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1608 compatible = "qcom,geni-spi";
1610 reg-names = "se";
1611 clock-names = "se";
1612 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dma-names = "tx", "rx";
1616 pinctrl-names = "default";
1617 pinctrl-0 = <&qup_spi18_default>;
1619 spi-max-frequency = <50000000>;
1620 #address-cells = <1>;
1621 #size-cells = <0>;
1626 compatible = "qcom,geni-i2c";
1628 clock-names = "se";
1629 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dma-names = "tx", "rx";
1633 pinctrl-names = "default";
1634 pinctrl-0 = <&qup_i2c19_default>;
1636 #address-cells = <1>;
1637 #size-cells = <0>;
1642 compatible = "qcom,geni-spi";
1644 reg-names = "se";
1645 clock-names = "se";
1646 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dma-names = "tx", "rx";
1650 pinctrl-names = "default";
1651 pinctrl-0 = <&qup_spi19_default>;
1653 spi-max-frequency = <50000000>;
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1660 compatible = "qcom,geni-i2c";
1662 clock-names = "se";
1663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dma-names = "tx", "rx";
1667 pinctrl-names = "default";
1668 pinctrl-0 = <&qup_i2c13_default>;
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1676 compatible = "qcom,geni-spi";
1678 reg-names = "se";
1679 clock-names = "se";
1680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dma-names = "tx", "rx";
1684 pinctrl-names = "default";
1685 pinctrl-0 = <&qup_spi13_default>;
1687 spi-max-frequency = <50000000>;
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1694 compatible = "qcom,geni-i2c";
1696 clock-names = "se";
1697 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dma-names = "tx", "rx";
1701 pinctrl-names = "default";
1702 pinctrl-0 = <&qup_i2c14_default>;
1704 #address-cells = <1>;
1705 #size-cells = <0>;
1710 compatible = "qcom,geni-spi";
1712 reg-names = "se";
1713 clock-names = "se";
1714 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dma-names = "tx", "rx";
1718 pinctrl-names = "default";
1719 pinctrl-0 = <&qup_spi14_default>;
1721 spi-max-frequency = <50000000>;
1722 #address-cells = <1>;
1723 #size-cells = <0>;
1728 compatible = "qcom,geni-i2c";
1730 clock-names = "se";
1731 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dma-names = "tx", "rx";
1735 pinctrl-names = "default";
1736 pinctrl-0 = <&qup_i2c15_default>;
1738 #address-cells = <1>;
1739 #size-cells = <0>;
1744 compatible = "qcom,geni-spi";
1746 reg-names = "se";
1747 clock-names = "se";
1748 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dma-names = "tx", "rx";
1752 pinctrl-names = "default";
1753 pinctrl-0 = <&qup_spi15_default>;
1755 spi-max-frequency = <50000000>;
1756 #address-cells = <1>;
1757 #size-cells = <0>;
1763 compatible = "qcom,sm8150-config-noc";
1765 #interconnect-cells = <2>;
1766 qcom,bcm-voters = <&apps_bcm_voter>;
1770 compatible = "qcom,sm8150-system-noc";
1772 #interconnect-cells = <2>;
1773 qcom,bcm-voters = <&apps_bcm_voter>;
1777 compatible = "qcom,sm8150-mc-virt";
1779 #interconnect-cells = <2>;
1780 qcom,bcm-voters = <&apps_bcm_voter>;
1784 compatible = "qcom,sm8150-aggre1-noc";
1786 #interconnect-cells = <2>;
1787 qcom,bcm-voters = <&apps_bcm_voter>;
1791 compatible = "qcom,sm8150-aggre2-noc";
1793 #interconnect-cells = <2>;
1794 qcom,bcm-voters = <&apps_bcm_voter>;
1798 compatible = "qcom,sm8150-compute-noc";
1800 #interconnect-cells = <2>;
1801 qcom,bcm-voters = <&apps_bcm_voter>;
1805 compatible = "qcom,sm8150-mmss-noc";
1807 #interconnect-cells = <2>;
1808 qcom,bcm-voters = <&apps_bcm_voter>;
1811 system-cache-controller@9200000 {
1812 compatible = "qcom,sm8150-llcc";
1816 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1822 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1828 compatible = "qcom,pcie-sm8150";
1834 reg-names = "parf", "dbi", "elbi", "atu", "config";
1836 linux,pci-domain = <0>;
1837 bus-range = <0x00 0xff>;
1838 num-lanes = <1>;
1840 #address-cells = <3>;
1841 #size-cells = <2>;
1847 interrupt-names = "msi";
1848 #interrupt-cells = <1>;
1849 interrupt-map-mask = <0 0 0 0x7>;
1850 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1855 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1856 <&gcc GCC_PCIE_0_AUX_CLK>,
1857 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1858 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1859 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1860 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1861 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1862 clock-names = "pipe",
1870 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1873 resets = <&gcc GCC_PCIE_0_BCR>;
1874 reset-names = "pci";
1876 power-domains = <&gcc PCIE_0_GDSC>;
1879 phy-names = "pciephy";
1881 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1882 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&pcie0_default_state>;
1891 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1893 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1894 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1895 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1896 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1897 <&gcc GCC_PCIE_0_PIPE_CLK>;
1898 clock-names = "aux",
1904 clock-output-names = "pcie_0_pipe_clk";
1905 #clock-cells = <0>;
1907 #phy-cells = <0>;
1909 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1910 reset-names = "phy";
1912 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1913 assigned-clock-rates = <100000000>;
1919 compatible = "qcom,pcie-sm8150";
1925 reg-names = "parf", "dbi", "elbi", "atu", "config";
1927 linux,pci-domain = <1>;
1928 bus-range = <0x00 0xff>;
1929 num-lanes = <2>;
1931 #address-cells = <3>;
1932 #size-cells = <2>;
1938 interrupt-names = "msi";
1939 #interrupt-cells = <1>;
1940 interrupt-map-mask = <0 0 0 0x7>;
1941 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1946 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1947 <&gcc GCC_PCIE_1_AUX_CLK>,
1948 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1949 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1950 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1951 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1952 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1953 clock-names = "pipe",
1961 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1962 assigned-clock-rates = <19200000>;
1964 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1967 resets = <&gcc GCC_PCIE_1_BCR>;
1968 reset-names = "pci";
1970 power-domains = <&gcc PCIE_1_GDSC>;
1973 phy-names = "pciephy";
1975 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1976 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1978 pinctrl-names = "default";
1979 pinctrl-0 = <&pcie1_default_state>;
1985 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1987 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1990 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
1991 <&gcc GCC_PCIE_1_PIPE_CLK>;
1992 clock-names = "aux",
1998 clock-output-names = "pcie_1_pipe_clk";
1999 #clock-cells = <0>;
2001 #phy-cells = <0>;
2003 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2004 reset-names = "phy";
2006 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2007 assigned-clock-rates = <100000000>;
2013 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2014 "jedec,ufs-2.0";
2017 reg-names = "std", "ice";
2020 phy-names = "ufsphy";
2021 lanes-per-direction = <2>;
2022 #reset-cells = <1>;
2023 resets = <&gcc GCC_UFS_PHY_BCR>;
2024 reset-names = "rst";
2028 clock-names =
2039 <&gcc GCC_UFS_PHY_AXI_CLK>,
2040 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2041 <&gcc GCC_UFS_PHY_AHB_CLK>,
2042 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2044 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2045 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2046 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2047 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2048 freq-table-hz =
2063 compatible = "qcom,sm8150-qmp-ufs-phy";
2066 clock-names = "ref",
2068 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2069 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2071 power-domains = <&gcc UFS_PHY_GDSC>;
2074 reset-names = "ufsphy";
2076 #phy-cells = <0>;
2081 cryptobam: dma-controller@1dc4000 {
2082 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2085 #dma-cells = <1>;
2087 qcom,controlled-remotely;
2088 num-channels = <8>;
2089 qcom,num-ees = <2>;
2098 compatible = "qcom,sm8150-qce", "qcom,qce";
2101 dma-names = "rx", "tx";
2108 interconnect-names = "memory";
2112 compatible = "qcom,tcsr-mutex";
2114 #hwlock-cells = <1>;
2118 compatible = "qcom,sm8150-tcsr", "syscon";
2123 compatible = "qcom,sm8150-slpi-pas";
2126 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2131 interrupt-names = "wdog", "fatal", "ready",
2132 "handover", "stop-ack";
2135 clock-names = "xo";
2137 power-domains = <&rpmhpd SM8150_LCX>,
2139 power-domain-names = "lcx", "lmx";
2141 memory-region = <&slpi_mem>;
2145 qcom,smem-states = <&slpi_smp2p_out 0>;
2146 qcom,smem-state-names = "stop";
2150 glink-edge {
2153 qcom,remote-pid = <3>;
2158 qcom,glink-channels = "fastrpcglink-apps-dsp";
2160 qcom,non-secure-domain;
2161 #address-cells = <1>;
2162 #size-cells = <0>;
2164 compute-cb@1 {
2165 compatible = "qcom,fastrpc-compute-cb";
2170 compute-cb@2 {
2171 compatible = "qcom,fastrpc-compute-cb";
2176 compute-cb@3 {
2177 compatible = "qcom,fastrpc-compute-cb";
2180 /* note: shared-cb = <4> in downstream */
2187 compatible = "qcom,adreno-640.1", "qcom,adreno";
2189 reg-names = "kgsl_3d0_reg_memory";
2195 operating-points-v2 = <&gpu_opp_table>;
2199 nvmem-cells = <&gpu_speed_bin>;
2200 nvmem-cell-names = "speed_bin";
2204 zap-shader {
2205 memory-region = <&gpu_mem>;
2208 gpu_opp_table: opp-table {
2209 compatible = "operating-points-v2";
2211 opp-675000000 {
2212 opp-hz = /bits/ 64 <675000000>;
2213 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2214 opp-supported-hw = <0x2>;
2217 opp-585000000 {
2218 opp-hz = /bits/ 64 <585000000>;
2219 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2220 opp-supported-hw = <0x3>;
2223 opp-499200000 {
2224 opp-hz = /bits/ 64 <499200000>;
2225 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2226 opp-supported-hw = <0x3>;
2229 opp-427000000 {
2230 opp-hz = /bits/ 64 <427000000>;
2231 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2232 opp-supported-hw = <0x3>;
2235 opp-345000000 {
2236 opp-hz = /bits/ 64 <345000000>;
2237 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2238 opp-supported-hw = <0x3>;
2241 opp-257000000 {
2242 opp-hz = /bits/ 64 <257000000>;
2243 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2244 opp-supported-hw = <0x3>;
2250 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2255 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2259 interrupt-names = "hfi", "gmu";
2264 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2265 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2266 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2268 power-domains = <&gpucc GPU_CX_GDSC>,
2270 power-domain-names = "cx", "gx";
2274 operating-points-v2 = <&gmu_opp_table>;
2278 gmu_opp_table: opp-table {
2279 compatible = "operating-points-v2";
2281 opp-200000000 {
2282 opp-hz = /bits/ 64 <200000000>;
2283 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2288 gpucc: clock-controller@2c90000 {
2289 compatible = "qcom,sm8150-gpucc";
2292 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2293 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2294 clock-names = "bi_tcxo",
2297 #clock-cells = <1>;
2298 #reset-cells = <1>;
2299 #power-domain-cells = <1>;
2303 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2304 "qcom,smmu-500", "arm,mmu-500";
2306 #iommu-cells = <2>;
2307 #global-interrupts = <1>;
2318 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2319 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2320 clock-names = "ahb", "bus", "iface";
2322 power-domains = <&gpucc GPU_CX_GDSC>;
2326 compatible = "qcom,sm8150-pinctrl";
2331 reg-names = "west", "east", "north", "south";
2333 gpio-ranges = <&tlmm 0 0 176>;
2334 gpio-controller;
2335 #gpio-cells = <2>;
2336 interrupt-controller;
2337 #interrupt-cells = <2>;
2338 wakeup-parent = <&pdc>;
2340 qup_i2c0_default: qup-i2c0-default-state {
2343 drive-strength = <0x02>;
2344 bias-disable;
2347 qup_spi0_default: qup-spi0-default-state {
2350 drive-strength = <6>;
2351 bias-disable;
2354 qup_i2c1_default: qup-i2c1-default-state {
2357 drive-strength = <2>;
2358 bias-disable;
2361 qup_spi1_default: qup-spi1-default-state {
2364 drive-strength = <6>;
2365 bias-disable;
2368 qup_i2c2_default: qup-i2c2-default-state {
2371 drive-strength = <2>;
2372 bias-disable;
2375 qup_spi2_default: qup-spi2-default-state {
2378 drive-strength = <6>;
2379 bias-disable;
2382 qup_i2c3_default: qup-i2c3-default-state {
2385 drive-strength = <2>;
2386 bias-disable;
2389 qup_spi3_default: qup-spi3-default-state {
2392 drive-strength = <6>;
2393 bias-disable;
2396 qup_i2c4_default: qup-i2c4-default-state {
2399 drive-strength = <2>;
2400 bias-disable;
2403 qup_spi4_default: qup-spi4-default-state {
2406 drive-strength = <6>;
2407 bias-disable;
2410 qup_i2c5_default: qup-i2c5-default-state {
2413 drive-strength = <2>;
2414 bias-disable;
2417 qup_spi5_default: qup-spi5-default-state {
2420 drive-strength = <6>;
2421 bias-disable;
2424 qup_i2c6_default: qup-i2c6-default-state {
2427 drive-strength = <2>;
2428 bias-disable;
2431 qup_spi6_default: qup-spi6_default-state {
2434 drive-strength = <6>;
2435 bias-disable;
2438 qup_i2c7_default: qup-i2c7-default-state {
2441 drive-strength = <2>;
2442 bias-disable;
2445 qup_spi7_default: qup-spi7_default-state {
2448 drive-strength = <6>;
2449 bias-disable;
2452 qup_i2c8_default: qup-i2c8-default-state {
2455 drive-strength = <2>;
2456 bias-disable;
2459 qup_spi8_default: qup-spi8-default-state {
2462 drive-strength = <6>;
2463 bias-disable;
2466 qup_i2c9_default: qup-i2c9-default-state {
2469 drive-strength = <2>;
2470 bias-disable;
2473 qup_spi9_default: qup-spi9-default-state {
2476 drive-strength = <6>;
2477 bias-disable;
2480 qup_uart9_default: qup-uart9-default-state {
2483 drive-strength = <2>;
2484 bias-disable;
2487 qup_i2c10_default: qup-i2c10-default-state {
2490 drive-strength = <2>;
2491 bias-disable;
2494 qup_spi10_default: qup-spi10-default-state {
2497 drive-strength = <6>;
2498 bias-disable;
2501 qup_i2c11_default: qup-i2c11-default-state {
2504 drive-strength = <2>;
2505 bias-disable;
2508 qup_spi11_default: qup-spi11-default-state {
2511 drive-strength = <6>;
2512 bias-disable;
2515 qup_i2c12_default: qup-i2c12-default-state {
2518 drive-strength = <2>;
2519 bias-disable;
2522 qup_spi12_default: qup-spi12-default-state {
2525 drive-strength = <6>;
2526 bias-disable;
2529 qup_i2c13_default: qup-i2c13-default-state {
2532 drive-strength = <2>;
2533 bias-disable;
2536 qup_spi13_default: qup-spi13-default-state {
2539 drive-strength = <6>;
2540 bias-disable;
2543 qup_i2c14_default: qup-i2c14-default-state {
2546 drive-strength = <2>;
2547 bias-disable;
2550 qup_spi14_default: qup-spi14-default-state {
2553 drive-strength = <6>;
2554 bias-disable;
2557 qup_i2c15_default: qup-i2c15-default-state {
2560 drive-strength = <2>;
2561 bias-disable;
2564 qup_spi15_default: qup-spi15-default-state {
2567 drive-strength = <6>;
2568 bias-disable;
2571 qup_i2c16_default: qup-i2c16-default-state {
2574 drive-strength = <2>;
2575 bias-disable;
2578 qup_spi16_default: qup-spi16-default-state {
2581 drive-strength = <6>;
2582 bias-disable;
2585 qup_i2c17_default: qup-i2c17-default-state {
2588 drive-strength = <2>;
2589 bias-disable;
2592 qup_spi17_default: qup-spi17-default-state {
2595 drive-strength = <6>;
2596 bias-disable;
2599 qup_i2c18_default: qup-i2c18-default-state {
2602 drive-strength = <2>;
2603 bias-disable;
2606 qup_spi18_default: qup-spi18-default-state {
2609 drive-strength = <6>;
2610 bias-disable;
2613 qup_i2c19_default: qup-i2c19-default-state {
2616 drive-strength = <2>;
2617 bias-disable;
2620 qup_spi19_default: qup-spi19-default-state {
2623 drive-strength = <6>;
2624 bias-disable;
2627 pcie0_default_state: pcie0-default-state {
2628 perst-pins {
2631 drive-strength = <2>;
2632 bias-pull-down;
2635 clkreq-pins {
2638 drive-strength = <2>;
2639 bias-pull-up;
2642 wake-pins {
2645 drive-strength = <2>;
2646 bias-pull-up;
2650 pcie1_default_state: pcie1-default-state {
2651 perst-pins {
2654 drive-strength = <2>;
2655 bias-pull-down;
2658 clkreq-pins {
2661 drive-strength = <2>;
2662 bias-pull-up;
2665 wake-pins {
2668 drive-strength = <2>;
2669 bias-pull-up;
2675 compatible = "qcom,sm8150-mpss-pas";
2678 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2684 interrupt-names = "wdog", "fatal", "ready", "handover",
2685 "stop-ack", "shutdown-ack";
2688 clock-names = "xo";
2690 power-domains = <&rpmhpd SM8150_CX>,
2692 power-domain-names = "cx", "mss";
2694 memory-region = <&mpss_mem>;
2698 qcom,smem-states = <&modem_smp2p_out 0>;
2699 qcom,smem-state-names = "stop";
2703 glink-edge {
2706 qcom,remote-pid = <1>;
2712 compatible = "arm,coresight-stm", "arm,primecell";
2715 reg-names = "stm-base", "stm-stimulus-base";
2718 clock-names = "apb_pclk";
2720 out-ports {
2723 remote-endpoint = <&funnel0_in7>;
2730 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2734 clock-names = "apb_pclk";
2736 out-ports {
2739 remote-endpoint = <&merge_funnel_in0>;
2744 in-ports {
2745 #address-cells = <1>;
2746 #size-cells = <0>;
2751 remote-endpoint = <&stm_out>;
2758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2762 clock-names = "apb_pclk";
2764 out-ports {
2767 remote-endpoint = <&merge_funnel_in1>;
2772 in-ports {
2773 #address-cells = <1>;
2774 #size-cells = <0>;
2779 remote-endpoint = <&swao_replicator_out>;
2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2790 clock-names = "apb_pclk";
2792 out-ports {
2795 remote-endpoint = <&merge_funnel_in2>;
2800 in-ports {
2801 #address-cells = <1>;
2802 #size-cells = <0>;
2807 remote-endpoint = <&apss_merge_funnel_out>;
2814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2818 clock-names = "apb_pclk";
2820 out-ports {
2823 remote-endpoint = <&etf_in>;
2828 in-ports {
2829 #address-cells = <1>;
2830 #size-cells = <0>;
2835 remote-endpoint = <&funnel0_out>;
2842 remote-endpoint = <&funnel1_out>;
2849 remote-endpoint = <&funnel2_out>;
2856 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2860 clock-names = "apb_pclk";
2862 out-ports {
2863 #address-cells = <1>;
2864 #size-cells = <0>;
2869 remote-endpoint = <&etr_in>;
2876 remote-endpoint = <&replicator1_in>;
2881 in-ports {
2884 remote-endpoint = <&etf_out>;
2891 compatible = "arm,coresight-tmc", "arm,primecell";
2895 clock-names = "apb_pclk";
2897 out-ports {
2900 remote-endpoint = <&replicator_in0>;
2905 in-ports {
2908 remote-endpoint = <&merge_funnel_out>;
2915 compatible = "arm,coresight-tmc", "arm,primecell";
2920 clock-names = "apb_pclk";
2921 arm,scatter-gather;
2923 in-ports {
2926 remote-endpoint = <&replicator_out0>;
2933 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2937 clock-names = "apb_pclk";
2939 out-ports {
2940 #address-cells = <1>;
2941 #size-cells = <0>;
2946 remote-endpoint = <&swao_funnel_in>;
2951 in-ports {
2955 remote-endpoint = <&replicator_out1>;
2962 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2966 clock-names = "apb_pclk";
2968 out-ports {
2971 remote-endpoint = <&swao_etf_in>;
2976 in-ports {
2977 #address-cells = <1>;
2978 #size-cells = <0>;
2983 remote-endpoint = <&replicator1_out>;
2990 compatible = "arm,coresight-tmc", "arm,primecell";
2994 clock-names = "apb_pclk";
2996 out-ports {
2999 remote-endpoint = <&swao_replicator_in>;
3004 in-ports {
3007 remote-endpoint = <&swao_funnel_out>;
3014 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3018 clock-names = "apb_pclk";
3019 qcom,replicator-loses-context;
3021 out-ports {
3024 remote-endpoint = <&funnel1_in4>;
3029 in-ports {
3032 remote-endpoint = <&swao_etf_out>;
3039 compatible = "arm,coresight-etm4x", "arm,primecell";
3045 clock-names = "apb_pclk";
3046 arm,coresight-loses-context-with-cpu;
3047 qcom,skip-power-up;
3049 out-ports {
3052 remote-endpoint = <&apss_funnel_in0>;
3059 compatible = "arm,coresight-etm4x", "arm,primecell";
3065 clock-names = "apb_pclk";
3066 arm,coresight-loses-context-with-cpu;
3067 qcom,skip-power-up;
3069 out-ports {
3072 remote-endpoint = <&apss_funnel_in1>;
3079 compatible = "arm,coresight-etm4x", "arm,primecell";
3085 clock-names = "apb_pclk";
3086 arm,coresight-loses-context-with-cpu;
3087 qcom,skip-power-up;
3089 out-ports {
3092 remote-endpoint = <&apss_funnel_in2>;
3099 compatible = "arm,coresight-etm4x", "arm,primecell";
3105 clock-names = "apb_pclk";
3106 arm,coresight-loses-context-with-cpu;
3107 qcom,skip-power-up;
3109 out-ports {
3112 remote-endpoint = <&apss_funnel_in3>;
3119 compatible = "arm,coresight-etm4x", "arm,primecell";
3125 clock-names = "apb_pclk";
3126 arm,coresight-loses-context-with-cpu;
3127 qcom,skip-power-up;
3129 out-ports {
3132 remote-endpoint = <&apss_funnel_in4>;
3139 compatible = "arm,coresight-etm4x", "arm,primecell";
3145 clock-names = "apb_pclk";
3146 arm,coresight-loses-context-with-cpu;
3147 qcom,skip-power-up;
3149 out-ports {
3152 remote-endpoint = <&apss_funnel_in5>;
3159 compatible = "arm,coresight-etm4x", "arm,primecell";
3165 clock-names = "apb_pclk";
3166 arm,coresight-loses-context-with-cpu;
3167 qcom,skip-power-up;
3169 out-ports {
3172 remote-endpoint = <&apss_funnel_in6>;
3179 compatible = "arm,coresight-etm4x", "arm,primecell";
3185 clock-names = "apb_pclk";
3186 arm,coresight-loses-context-with-cpu;
3187 qcom,skip-power-up;
3189 out-ports {
3192 remote-endpoint = <&apss_funnel_in7>;
3199 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3203 clock-names = "apb_pclk";
3205 out-ports {
3208 remote-endpoint = <&apss_merge_funnel_in>;
3213 in-ports {
3214 #address-cells = <1>;
3215 #size-cells = <0>;
3220 remote-endpoint = <&etm0_out>;
3227 remote-endpoint = <&etm1_out>;
3234 remote-endpoint = <&etm2_out>;
3241 remote-endpoint = <&etm3_out>;
3248 remote-endpoint = <&etm4_out>;
3255 remote-endpoint = <&etm5_out>;
3262 remote-endpoint = <&etm6_out>;
3269 remote-endpoint = <&etm7_out>;
3276 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 clock-names = "apb_pclk";
3282 out-ports {
3285 remote-endpoint = <&funnel2_in2>;
3290 in-ports {
3293 remote-endpoint = <&apss_funnel_out>;
3300 compatible = "qcom,sm8150-cdsp-pas";
3303 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3308 interrupt-names = "wdog", "fatal", "ready",
3309 "handover", "stop-ack";
3312 clock-names = "xo";
3314 power-domains = <&rpmhpd SM8150_CX>;
3316 memory-region = <&cdsp_mem>;
3320 qcom,smem-states = <&cdsp_smp2p_out 0>;
3321 qcom,smem-state-names = "stop";
3325 glink-edge {
3328 qcom,remote-pid = <5>;
3333 qcom,glink-channels = "fastrpcglink-apps-dsp";
3335 qcom,non-secure-domain;
3336 #address-cells = <1>;
3337 #size-cells = <0>;
3339 compute-cb@1 {
3340 compatible = "qcom,fastrpc-compute-cb";
3345 compute-cb@2 {
3346 compatible = "qcom,fastrpc-compute-cb";
3351 compute-cb@3 {
3352 compatible = "qcom,fastrpc-compute-cb";
3357 compute-cb@4 {
3358 compatible = "qcom,fastrpc-compute-cb";
3363 compute-cb@5 {
3364 compatible = "qcom,fastrpc-compute-cb";
3369 compute-cb@6 {
3370 compatible = "qcom,fastrpc-compute-cb";
3375 compute-cb@7 {
3376 compatible = "qcom,fastrpc-compute-cb";
3381 compute-cb@8 {
3382 compatible = "qcom,fastrpc-compute-cb";
3393 compatible = "qcom,sm8150-usb-hs-phy",
3394 "qcom,usb-snps-hs-7nm-phy";
3397 #phy-cells = <0>;
3400 clock-names = "ref";
3402 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3406 compatible = "qcom,sm8150-usb-hs-phy",
3407 "qcom,usb-snps-hs-7nm-phy";
3410 #phy-cells = <0>;
3413 clock-names = "ref";
3415 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3419 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3422 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3423 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3424 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3425 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3426 clock-names = "aux",
3431 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3432 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3433 reset-names = "phy", "common";
3435 #clock-cells = <1>;
3436 #phy-cells = <1>;
3441 #address-cells = <1>;
3442 #size-cells = <0>;
3468 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3471 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3472 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3473 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3474 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3475 clock-names = "aux",
3479 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3480 #clock-cells = <0>;
3481 #phy-cells = <0>;
3483 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3484 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3485 reset-names = "phy",
3492 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3497 interrupt-names = "hc_irq", "pwr_irq";
3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3500 <&gcc GCC_SDCC2_APPS_CLK>,
3502 clock-names = "iface", "core", "xo";
3504 qcom,dll-config = <0x0007642c>;
3505 qcom,ddr-config = <0x80040868>;
3506 power-domains = <&rpmhpd 0>;
3507 operating-points-v2 = <&sdhc2_opp_table>;
3511 sdhc2_opp_table: opp-table {
3512 compatible = "operating-points-v2";
3514 opp-19200000 {
3515 opp-hz = /bits/ 64 <19200000>;
3516 required-opps = <&rpmhpd_opp_min_svs>;
3519 opp-50000000 {
3520 opp-hz = /bits/ 64 <50000000>;
3521 required-opps = <&rpmhpd_opp_low_svs>;
3524 opp-100000000 {
3525 opp-hz = /bits/ 64 <100000000>;
3526 required-opps = <&rpmhpd_opp_svs>;
3529 opp-202000000 {
3530 opp-hz = /bits/ 64 <202000000>;
3531 required-opps = <&rpmhpd_opp_svs_l1>;
3537 compatible = "qcom,sm8150-dc-noc";
3539 #interconnect-cells = <2>;
3540 qcom,bcm-voters = <&apps_bcm_voter>;
3544 compatible = "qcom,sm8150-gem-noc";
3546 #interconnect-cells = <2>;
3547 qcom,bcm-voters = <&apps_bcm_voter>;
3551 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3554 #address-cells = <2>;
3555 #size-cells = <2>;
3557 dma-ranges;
3559 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3560 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3561 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3562 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3563 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3564 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3565 clock-names = "cfg_noc",
3572 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3573 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3574 assigned-clock-rates = <19200000>, <200000000>;
3576 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3580 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3583 power-domains = <&gcc USB30_PRIM_GDSC>;
3585 resets = <&gcc GCC_USB30_PRIM_BCR>;
3589 interconnect-names = "usb-ddr", "apps-usb";
3599 phy-names = "usb2-phy", "usb3-phy";
3602 #address-cells = <1>;
3603 #size-cells = <0>;
3623 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3626 #address-cells = <2>;
3627 #size-cells = <2>;
3629 dma-ranges;
3631 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3632 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3633 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3634 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3635 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3636 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3637 clock-names = "cfg_noc",
3644 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3645 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3646 assigned-clock-rates = <19200000>, <200000000>;
3648 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3652 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3655 power-domains = <&gcc USB30_SEC_GDSC>;
3657 resets = <&gcc GCC_USB30_SEC_BCR>;
3661 interconnect-names = "usb-ddr", "apps-usb";
3671 phy-names = "usb2-phy", "usb3-phy";
3676 compatible = "qcom,sm8150-camnoc-virt";
3678 #interconnect-cells = <2>;
3679 qcom,bcm-voters = <&apps_bcm_voter>;
3682 mdss: display-subsystem@ae00000 {
3683 compatible = "qcom,sm8150-mdss";
3685 reg-names = "mdss";
3689 interconnect-names = "mdp0-mem", "mdp1-mem";
3691 power-domains = <&dispcc MDSS_GDSC>;
3694 <&gcc GCC_DISP_HF_AXI_CLK>,
3695 <&gcc GCC_DISP_SF_AXI_CLK>,
3697 clock-names = "iface", "bus", "nrt_bus", "core";
3700 interrupt-controller;
3701 #interrupt-cells = <1>;
3707 #address-cells = <2>;
3708 #size-cells = <2>;
3711 mdss_mdp: display-controller@ae01000 {
3712 compatible = "qcom,sm8150-dpu";
3715 reg-names = "mdp", "vbif";
3718 <&gcc GCC_DISP_HF_AXI_CLK>,
3721 clock-names = "iface", "bus", "core", "vsync";
3723 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3724 assigned-clock-rates = <19200000>;
3726 operating-points-v2 = <&mdp_opp_table>;
3727 power-domains = <&rpmhpd SM8150_MMCX>;
3729 interrupt-parent = <&mdss>;
3733 #address-cells = <1>;
3734 #size-cells = <0>;
3739 remote-endpoint = <&mdss_dsi0_in>;
3746 remote-endpoint = <&mdss_dsi1_in>;
3753 remote-endpoint = <&mdss_dp_in>;
3758 mdp_opp_table: opp-table {
3759 compatible = "operating-points-v2";
3761 opp-171428571 {
3762 opp-hz = /bits/ 64 <171428571>;
3763 required-opps = <&rpmhpd_opp_low_svs>;
3766 opp-300000000 {
3767 opp-hz = /bits/ 64 <300000000>;
3768 required-opps = <&rpmhpd_opp_svs>;
3771 opp-345000000 {
3772 opp-hz = /bits/ 64 <345000000>;
3773 required-opps = <&rpmhpd_opp_svs_l1>;
3776 opp-460000000 {
3777 opp-hz = /bits/ 64 <460000000>;
3778 required-opps = <&rpmhpd_opp_nom>;
3783 mdss_dp: displayport-controller@ae90000 {
3784 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3791 interrupt-parent = <&mdss>;
3798 clock-names = "core_iface",
3804 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3806 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3810 phy-names = "dp";
3812 #sound-dai-cells = <0>;
3814 operating-points-v2 = <&dp_opp_table>;
3815 power-domains = <&rpmhpd SM8250_MMCX>;
3820 #address-cells = <1>;
3821 #size-cells = <0>;
3826 remote-endpoint = <&dpu_intf0_out>;
3838 dp_opp_table: opp-table {
3839 compatible = "operating-points-v2";
3841 opp-160000000 {
3842 opp-hz = /bits/ 64 <160000000>;
3843 required-opps = <&rpmhpd_opp_low_svs>;
3846 opp-270000000 {
3847 opp-hz = /bits/ 64 <270000000>;
3848 required-opps = <&rpmhpd_opp_svs>;
3851 opp-540000000 {
3852 opp-hz = /bits/ 64 <540000000>;
3853 required-opps = <&rpmhpd_opp_svs_l1>;
3856 opp-810000000 {
3857 opp-hz = /bits/ 64 <810000000>;
3858 required-opps = <&rpmhpd_opp_nom>;
3864 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3866 reg-names = "dsi_ctrl";
3868 interrupt-parent = <&mdss>;
3876 <&gcc GCC_DISP_HF_AXI_CLK>;
3877 clock-names = "byte",
3884 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3886 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3889 operating-points-v2 = <&dsi_opp_table>;
3890 power-domains = <&rpmhpd SM8150_MMCX>;
3896 #address-cells = <1>;
3897 #size-cells = <0>;
3900 #address-cells = <1>;
3901 #size-cells = <0>;
3906 remote-endpoint = <&dpu_intf1_out>;
3917 dsi_opp_table: opp-table {
3918 compatible = "operating-points-v2";
3920 opp-187500000 {
3921 opp-hz = /bits/ 64 <187500000>;
3922 required-opps = <&rpmhpd_opp_low_svs>;
3925 opp-300000000 {
3926 opp-hz = /bits/ 64 <300000000>;
3927 required-opps = <&rpmhpd_opp_svs>;
3930 opp-358000000 {
3931 opp-hz = /bits/ 64 <358000000>;
3932 required-opps = <&rpmhpd_opp_svs_l1>;
3938 compatible = "qcom,dsi-phy-7nm-8150";
3942 reg-names = "dsi_phy",
3946 #clock-cells = <1>;
3947 #phy-cells = <0>;
3951 clock-names = "iface", "ref";
3957 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg-names = "dsi_ctrl";
3961 interrupt-parent = <&mdss>;
3969 <&gcc GCC_DISP_HF_AXI_CLK>;
3970 clock-names = "byte",
3977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3979 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3982 operating-points-v2 = <&dsi_opp_table>;
3983 power-domains = <&rpmhpd SM8150_MMCX>;
3989 #address-cells = <1>;
3990 #size-cells = <0>;
3993 #address-cells = <1>;
3994 #size-cells = <0>;
3999 remote-endpoint = <&dpu_intf2_out>;
4012 compatible = "qcom,dsi-phy-7nm-8150";
4016 reg-names = "dsi_phy",
4020 #clock-cells = <1>;
4021 #phy-cells = <0>;
4025 clock-names = "iface", "ref";
4031 dispcc: clock-controller@af00000 {
4032 compatible = "qcom,sm8150-dispcc";
4041 clock-names = "bi_tcxo",
4048 power-domains = <&rpmhpd SM8150_MMCX>;
4049 required-opps = <&rpmhpd_opp_low_svs>;
4050 #clock-cells = <1>;
4051 #reset-cells = <1>;
4052 #power-domain-cells = <1>;
4055 pdc: interrupt-controller@b220000 {
4056 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4058 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4060 #interrupt-cells = <2>;
4061 interrupt-parent = <&intc>;
4062 interrupt-controller;
4065 aoss_qmp: power-management@c300000 {
4066 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4071 #clock-cells = <0>;
4075 compatible = "qcom,rpmh-stats";
4079 tsens0: thermal-sensor@c263000 {
4080 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4086 interrupt-names = "uplow", "critical";
4087 #thermal-sensor-cells = <1>;
4090 tsens1: thermal-sensor@c265000 {
4091 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4097 interrupt-names = "uplow", "critical";
4098 #thermal-sensor-cells = <1>;
4102 compatible = "qcom,spmi-pmic-arb";
4108 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4109 interrupt-names = "periph_irq";
4113 #address-cells = <2>;
4114 #size-cells = <0>;
4115 interrupt-controller;
4116 #interrupt-cells = <4>;
4120 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4122 #iommu-cells = <2>;
4123 #global-interrupts = <1>;
4208 compatible = "qcom,sm8150-adsp-pas";
4211 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4216 interrupt-names = "wdog", "fatal", "ready",
4217 "handover", "stop-ack";
4220 clock-names = "xo";
4222 power-domains = <&rpmhpd SM8150_CX>;
4224 memory-region = <&adsp_mem>;
4228 qcom,smem-states = <&adsp_smp2p_out 0>;
4229 qcom,smem-state-names = "stop";
4233 glink-edge {
4236 qcom,remote-pid = <2>;
4241 qcom,glink-channels = "fastrpcglink-apps-dsp";
4243 qcom,non-secure-domain;
4244 #address-cells = <1>;
4245 #size-cells = <0>;
4247 compute-cb@3 {
4248 compatible = "qcom,fastrpc-compute-cb";
4253 compute-cb@4 {
4254 compatible = "qcom,fastrpc-compute-cb";
4259 compute-cb@5 {
4260 compatible = "qcom,fastrpc-compute-cb";
4268 intc: interrupt-controller@17a00000 {
4269 compatible = "arm,gic-v3";
4270 interrupt-controller;
4271 #interrupt-cells = <3>;
4278 compatible = "qcom,sm8150-apss-shared",
4279 "qcom,sdm845-apss-shared";
4281 #mbox-cells = <1>;
4285 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4292 #address-cells = <1>;
4293 #size-cells = <1>;
4295 compatible = "arm,armv7-timer-mem";
4297 clock-frequency = <19200000>;
4300 frame-number = <0>;
4308 frame-number = <1>;
4315 frame-number = <2>;
4322 frame-number = <3>;
4329 frame-number = <4>;
4336 frame-number = <5>;
4343 frame-number = <6>;
4352 compatible = "qcom,rpmh-rsc";
4356 reg-names = "drv-0", "drv-1", "drv-2";
4360 qcom,tcs-offset = <0xd00>;
4361 qcom,drv-id = <2>;
4362 qcom,tcs-config = <ACTIVE_TCS 2>,
4366 power-domains = <&CLUSTER_PD>;
4368 rpmhcc: clock-controller {
4369 compatible = "qcom,sm8150-rpmh-clk";
4370 #clock-cells = <1>;
4371 clock-names = "xo";
4375 rpmhpd: power-controller {
4376 compatible = "qcom,sm8150-rpmhpd";
4377 #power-domain-cells = <1>;
4378 operating-points-v2 = <&rpmhpd_opp_table>;
4380 rpmhpd_opp_table: opp-table {
4381 compatible = "operating-points-v2";
4384 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4388 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4392 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4396 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4404 opp-level = <224>;
4408 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4412 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4416 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4420 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4424 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4429 apps_bcm_voter: bcm-voter {
4430 compatible = "qcom,bcm-voter";
4435 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4438 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4439 clock-names = "xo", "alternate";
4441 #interconnect-cells = <1>;
4445 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4448 reg-names = "freq-domain0", "freq-domain1",
4449 "freq-domain2";
4451 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4452 clock-names = "xo", "alternate";
4454 #freq-domain-cells = <1>;
4455 #clock-cells = <1>;
4459 compatible = "qcom,sm8150-lmh";
4463 qcom,lmh-temp-arm-millicelsius = <60000>;
4464 qcom,lmh-temp-low-millicelsius = <84500>;
4465 qcom,lmh-temp-high-millicelsius = <85000>;
4466 interrupt-controller;
4467 #interrupt-cells = <1>;
4471 compatible = "qcom,sm8150-lmh";
4475 qcom,lmh-temp-arm-millicelsius = <60000>;
4476 qcom,lmh-temp-low-millicelsius = <84500>;
4477 qcom,lmh-temp-high-millicelsius = <85000>;
4478 interrupt-controller;
4479 #interrupt-cells = <1>;
4483 compatible = "qcom,wcn3990-wifi";
4485 reg-names = "membase";
4486 memory-region = <&wlan_mem>;
4487 clock-names = "cxo_ref_clk_pin", "qdss";
4507 compatible = "arm,armv8-timer";
4514 thermal-zones {
4515 cpu0-thermal {
4516 polling-delay-passive = <250>;
4517 polling-delay = <1000>;
4519 thermal-sensors = <&tsens0 1>;
4522 cpu0_alert0: trip-point0 {
4528 cpu0_alert1: trip-point1 {
4534 cpu0_crit: cpu-crit {
4541 cooling-maps {
4544 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4551 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4559 cpu1-thermal {
4560 polling-delay-passive = <250>;
4561 polling-delay = <1000>;
4563 thermal-sensors = <&tsens0 2>;
4566 cpu1_alert0: trip-point0 {
4572 cpu1_alert1: trip-point1 {
4578 cpu1_crit: cpu-crit {
4585 cooling-maps {
4588 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4595 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4603 cpu2-thermal {
4604 polling-delay-passive = <250>;
4605 polling-delay = <1000>;
4607 thermal-sensors = <&tsens0 3>;
4610 cpu2_alert0: trip-point0 {
4616 cpu2_alert1: trip-point1 {
4622 cpu2_crit: cpu-crit {
4629 cooling-maps {
4632 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 cpu3-thermal {
4648 polling-delay-passive = <250>;
4649 polling-delay = <1000>;
4651 thermal-sensors = <&tsens0 4>;
4654 cpu3_alert0: trip-point0 {
4660 cpu3_alert1: trip-point1 {
4666 cpu3_crit: cpu-crit {
4673 cooling-maps {
4676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4691 cpu4-top-thermal {
4692 polling-delay-passive = <250>;
4693 polling-delay = <1000>;
4695 thermal-sensors = <&tsens0 7>;
4698 cpu4_top_alert0: trip-point0 {
4704 cpu4_top_alert1: trip-point1 {
4710 cpu4_top_crit: cpu-crit {
4717 cooling-maps {
4720 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4727 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4735 cpu5-top-thermal {
4736 polling-delay-passive = <250>;
4737 polling-delay = <1000>;
4739 thermal-sensors = <&tsens0 8>;
4742 cpu5_top_alert0: trip-point0 {
4748 cpu5_top_alert1: trip-point1 {
4754 cpu5_top_crit: cpu-crit {
4761 cooling-maps {
4764 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4771 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4779 cpu6-top-thermal {
4780 polling-delay-passive = <250>;
4781 polling-delay = <1000>;
4783 thermal-sensors = <&tsens0 9>;
4786 cpu6_top_alert0: trip-point0 {
4792 cpu6_top_alert1: trip-point1 {
4798 cpu6_top_crit: cpu-crit {
4805 cooling-maps {
4808 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4815 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4823 cpu7-top-thermal {
4824 polling-delay-passive = <250>;
4825 polling-delay = <1000>;
4827 thermal-sensors = <&tsens0 10>;
4830 cpu7_top_alert0: trip-point0 {
4836 cpu7_top_alert1: trip-point1 {
4842 cpu7_top_crit: cpu-crit {
4849 cooling-maps {
4852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4859 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4867 cpu4-bottom-thermal {
4868 polling-delay-passive = <250>;
4869 polling-delay = <1000>;
4871 thermal-sensors = <&tsens0 11>;
4874 cpu4_bottom_alert0: trip-point0 {
4880 cpu4_bottom_alert1: trip-point1 {
4886 cpu4_bottom_crit: cpu-crit {
4893 cooling-maps {
4896 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4911 cpu5-bottom-thermal {
4912 polling-delay-passive = <250>;
4913 polling-delay = <1000>;
4915 thermal-sensors = <&tsens0 12>;
4918 cpu5_bottom_alert0: trip-point0 {
4924 cpu5_bottom_alert1: trip-point1 {
4930 cpu5_bottom_crit: cpu-crit {
4937 cooling-maps {
4940 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4955 cpu6-bottom-thermal {
4956 polling-delay-passive = <250>;
4957 polling-delay = <1000>;
4959 thermal-sensors = <&tsens0 13>;
4962 cpu6_bottom_alert0: trip-point0 {
4968 cpu6_bottom_alert1: trip-point1 {
4974 cpu6_bottom_crit: cpu-crit {
4981 cooling-maps {
4984 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4999 cpu7-bottom-thermal {
5000 polling-delay-passive = <250>;
5001 polling-delay = <1000>;
5003 thermal-sensors = <&tsens0 14>;
5006 cpu7_bottom_alert0: trip-point0 {
5012 cpu7_bottom_alert1: trip-point1 {
5018 cpu7_bottom_crit: cpu-crit {
5025 cooling-maps {
5028 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5035 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5043 aoss0-thermal {
5044 polling-delay-passive = <250>;
5045 polling-delay = <1000>;
5047 thermal-sensors = <&tsens0 0>;
5050 aoss0_alert0: trip-point0 {
5058 cluster0-thermal {
5059 polling-delay-passive = <250>;
5060 polling-delay = <1000>;
5062 thermal-sensors = <&tsens0 5>;
5065 cluster0_alert0: trip-point0 {
5078 cluster1-thermal {
5079 polling-delay-passive = <250>;
5080 polling-delay = <1000>;
5082 thermal-sensors = <&tsens0 6>;
5085 cluster1_alert0: trip-point0 {
5098 gpu-top-thermal {
5099 polling-delay-passive = <250>;
5100 polling-delay = <1000>;
5102 thermal-sensors = <&tsens0 15>;
5105 gpu1_alert0: trip-point0 {
5113 aoss1-thermal {
5114 polling-delay-passive = <250>;
5115 polling-delay = <1000>;
5117 thermal-sensors = <&tsens1 0>;
5120 aoss1_alert0: trip-point0 {
5128 wlan-thermal {
5129 polling-delay-passive = <250>;
5130 polling-delay = <1000>;
5132 thermal-sensors = <&tsens1 1>;
5135 wlan_alert0: trip-point0 {
5143 video-thermal {
5144 polling-delay-passive = <250>;
5145 polling-delay = <1000>;
5147 thermal-sensors = <&tsens1 2>;
5150 video_alert0: trip-point0 {
5158 mem-thermal {
5159 polling-delay-passive = <250>;
5160 polling-delay = <1000>;
5162 thermal-sensors = <&tsens1 3>;
5165 mem_alert0: trip-point0 {
5173 q6-hvx-thermal {
5174 polling-delay-passive = <250>;
5175 polling-delay = <1000>;
5177 thermal-sensors = <&tsens1 4>;
5180 q6_hvx_alert0: trip-point0 {
5188 camera-thermal {
5189 polling-delay-passive = <250>;
5190 polling-delay = <1000>;
5192 thermal-sensors = <&tsens1 5>;
5195 camera_alert0: trip-point0 {
5203 compute-thermal {
5204 polling-delay-passive = <250>;
5205 polling-delay = <1000>;
5207 thermal-sensors = <&tsens1 6>;
5210 compute_alert0: trip-point0 {
5218 modem-thermal {
5219 polling-delay-passive = <250>;
5220 polling-delay = <1000>;
5222 thermal-sensors = <&tsens1 7>;
5225 modem_alert0: trip-point0 {
5233 npu-thermal {
5234 polling-delay-passive = <250>;
5235 polling-delay = <1000>;
5237 thermal-sensors = <&tsens1 8>;
5240 npu_alert0: trip-point0 {
5248 modem-vec-thermal {
5249 polling-delay-passive = <250>;
5250 polling-delay = <1000>;
5252 thermal-sensors = <&tsens1 9>;
5255 modem_vec_alert0: trip-point0 {
5263 modem-scl-thermal {
5264 polling-delay-passive = <250>;
5265 polling-delay = <1000>;
5267 thermal-sensors = <&tsens1 10>;
5270 modem_scl_alert0: trip-point0 {
5278 gpu-bottom-thermal {
5279 polling-delay-passive = <250>;
5280 polling-delay = <1000>;
5282 thermal-sensors = <&tsens1 11>;
5285 gpu2_alert0: trip-point0 {