Lines Matching +full:1 +full:c25000
154 clocks = <&cpufreq_hw 1>;
159 qcom,freq-domain = <&cpufreq_hw 1>;
178 clocks = <&cpufreq_hw 1>;
183 qcom,freq-domain = <&cpufreq_hw 1>;
202 clocks = <&cpufreq_hw 1>;
207 qcom,freq-domain = <&cpufreq_hw 1>;
295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
610 #reset-cells = <1>;
724 qcom,client-id = <1>;
813 #qcom,smem-state-cells = <1>;
837 #qcom,smem-state-cells = <1>;
857 qcom,remote-pid = <1>;
861 #qcom,smem-state-cells = <1>;
885 #qcom,smem-state-cells = <1>;
906 #clock-cells = <1>;
907 #reset-cells = <1>;
908 #power-domain-cells = <1>;
967 #address-cells = <1>;
968 #size-cells = <1>;
994 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
999 #address-cells = <1>;
1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1017 #address-cells = <1>;
1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1033 #address-cells = <1>;
1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1045 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1051 #address-cells = <1>;
1062 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1067 #address-cells = <1>;
1079 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1085 #address-cells = <1>;
1096 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1101 #address-cells = <1>;
1113 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1119 #address-cells = <1>;
1130 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1135 #address-cells = <1>;
1147 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1153 #address-cells = <1>;
1164 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1169 #address-cells = <1>;
1181 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1187 #address-cells = <1>;
1198 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1203 #address-cells = <1>;
1215 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1221 #address-cells = <1>;
1232 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1237 #address-cells = <1>;
1249 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1255 #address-cells = <1>;
1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1307 #address-cells = <1>;
1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1325 #address-cells = <1>;
1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1336 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1341 #address-cells = <1>;
1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1353 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1359 #address-cells = <1>;
1381 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1386 #address-cells = <1>;
1398 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1404 #address-cells = <1>;
1415 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1420 #address-cells = <1>;
1432 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1438 #address-cells = <1>;
1458 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1463 #address-cells = <1>;
1475 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1481 #address-cells = <1>;
1492 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1497 #address-cells = <1>;
1509 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1515 #address-cells = <1>;
1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1568 #address-cells = <1>;
1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1586 #address-cells = <1>;
1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1597 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1602 #address-cells = <1>;
1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1614 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1620 #address-cells = <1>;
1631 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1636 #address-cells = <1>;
1648 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1654 #address-cells = <1>;
1665 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1670 #address-cells = <1>;
1682 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1688 #address-cells = <1>;
1699 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1704 #address-cells = <1>;
1716 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1722 #address-cells = <1>;
1733 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1738 #address-cells = <1>;
1750 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1756 #address-cells = <1>;
1827 pcie0: pcie@1c00000 {
1838 num-lanes = <1>;
1848 #interrupt-cells = <1>;
1850 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1890 pcie0_phy: phy@1c06000 {
1918 pcie1: pcie@1c08000 {
1927 linux,pci-domain = <1>;
1939 #interrupt-cells = <1>;
1941 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 pcie1_phy: phy@1c0e000 {
2012 ufs_mem_hc: ufshc@1d84000 {
2022 #reset-cells = <1>;
2062 ufs_mem_phy: phy@1d87000 {
2081 cryptobam: dma-controller@1dc4000 {
2085 #dma-cells = <1>;
2097 crypto: crypto@1dfa000 {
2111 tcsr_mutex: hwlock@1f40000 {
2114 #hwlock-cells = <1>;
2117 tcsr_regs_1: syscon@1f60000 {
2128 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2161 #address-cells = <1>;
2164 compute-cb@1 {
2166 reg = <1>;
2297 #clock-cells = <1>;
2298 #reset-cells = <1>;
2299 #power-domain-cells = <1>;
2307 #global-interrupts = <1>;
2680 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2706 qcom,remote-pid = <1>;
2745 #address-cells = <1>;
2773 #address-cells = <1>;
2801 #address-cells = <1>;
2829 #address-cells = <1>;
2839 port@1 {
2840 reg = <1>;
2863 #address-cells = <1>;
2873 port@1 {
2874 reg = <1>;
2940 #address-cells = <1>;
2943 port@1 {
2944 reg = <1>;
2977 #address-cells = <1>;
3214 #address-cells = <1>;
3224 port@1 {
3225 reg = <1>;
3305 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3336 #address-cells = <1>;
3339 compute-cb@1 {
3341 reg = <1>;
3435 #clock-cells = <1>;
3436 #phy-cells = <1>;
3441 #address-cells = <1>;
3451 port@1 {
3452 reg = <1>;
3602 #address-cells = <1>;
3612 port@1 {
3613 reg = <1>;
3701 #interrupt-cells = <1>;
3733 #address-cells = <1>;
3743 port@1 {
3744 reg = <1>;
3820 #address-cells = <1>;
3830 port@1 {
3831 reg = <1>;
3887 <&mdss_dsi0_phy 1>;
3896 #address-cells = <1>;
3900 #address-cells = <1>;
3910 port@1 {
3911 reg = <1>;
3946 #clock-cells = <1>;
3980 <&mdss_dsi1_phy 1>;
3989 #address-cells = <1>;
3993 #address-cells = <1>;
4003 port@1 {
4004 reg = <1>;
4020 #clock-cells = <1>;
4036 <&mdss_dsi0_phy 1>,
4038 <&mdss_dsi1_phy 1>,
4050 #clock-cells = <1>;
4051 #reset-cells = <1>;
4052 #power-domain-cells = <1>;
4059 <125 63 1>;
4087 #thermal-sensor-cells = <1>;
4098 #thermal-sensor-cells = <1>;
4123 #global-interrupts = <1>;
4213 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4244 #address-cells = <1>;
4281 #mbox-cells = <1>;
4292 #address-cells = <1>;
4293 #size-cells = <1>;
4308 frame-number = <1>;
4314 frame@17c25000 {
4356 reg-names = "drv-0", "drv-1", "drv-2";
4365 <CONTROL_TCS 1>;
4370 #clock-cells = <1>;
4377 #power-domain-cells = <1>;
4441 #interconnect-cells = <1>;
4454 #freq-domain-cells = <1>;
4455 #clock-cells = <1>;
4467 #interrupt-cells = <1>;
4479 #interrupt-cells = <1>;
4508 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4519 thermal-sensors = <&tsens0 1>;
5132 thermal-sensors = <&tsens1 1>;