Lines Matching +full:0 +full:x010a2000
32 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
105 reg = <0x0 0x200>;
106 clocks = <&cpufreq_hw 0>;
111 qcom,freq-domain = <&cpufreq_hw 0>;
113 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
129 reg = <0x0 0x300>;
130 clocks = <&cpufreq_hw 0>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
153 reg = <0x0 0x400>;
161 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
177 reg = <0x0 0x500>;
185 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
201 reg = <0x0 0x600>;
209 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
225 reg = <0x0 0x700>;
233 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 arm,psci-suspend-param = <0x40000004>;
295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 arm,psci-suspend-param = <0x40000004>;
307 CLUSTER_SLEEP_0: cluster-sleep-0 {
309 arm,psci-suspend-param = <0x4100c244>;
617 reg = <0x0 0x80000000 0x0 0x0>;
630 #power-domain-cells = <0>;
636 #power-domain-cells = <0>;
642 #power-domain-cells = <0>;
648 #power-domain-cells = <0>;
654 #power-domain-cells = <0>;
660 #power-domain-cells = <0>;
666 #power-domain-cells = <0>;
672 #power-domain-cells = <0>;
678 #power-domain-cells = <0>;
689 reg = <0x0 0x85700000 0x0 0x600000>;
694 reg = <0x0 0x85d00000 0x0 0x140000>;
699 reg = <0x0 0x85f00000 0x0 0x20000>;
705 reg = <0x0 0x85f20000 0x0 0x20000>;
710 reg = <0x0 0x86000000 0x0 0x200000>;
715 reg = <0x0 0x86200000 0x0 0x3900000>;
721 reg = <0x0 0x89b00000 0x0 0x200000>;
729 reg = <0x0 0x8b700000 0x0 0x500000>;
734 reg = <0x0 0x8bc00000 0x0 0x180000>;
739 reg = <0x0 0x8bd80000 0x0 0x80000>;
744 reg = <0x0 0x8be00000 0x0 0x1a00000>;
749 reg = <0x0 0x8d800000 0x0 0x9600000>;
754 reg = <0x0 0x96e00000 0x0 0x500000>;
759 reg = <0x0 0x97300000 0x0 0x1400000>;
764 reg = <0x0 0x98700000 0x0 0x10000>;
769 reg = <0x0 0x98710000 0x0 0x5000>;
774 reg = <0x0 0x98715000 0x0 0x2000>;
779 reg = <0x0 0x98800000 0x0 0x100000>;
784 reg = <0x0 0x98900000 0x0 0x1400000>;
789 reg = <0x0 0x9e400000 0x0 0x1400000>;
808 qcom,local-pid = <0>;
832 qcom,local-pid = <0>;
856 qcom,local-pid = <0>;
880 qcom,local-pid = <0>;
896 soc: soc@0 {
899 ranges = <0 0 0 0 0x10 0>;
900 dma-ranges = <0 0 0 0 0x10 0>;
905 reg = <0x0 0x00100000 0x0 0x1f0000>;
917 reg = <0 0x00800000 0 0x60000>;
932 dma-channel-mask = <0xfa>;
933 iommus = <&apps_smmu 0x00d6 0x0>;
940 reg = <0x0 0x00020000 0x0 0x10000>,
941 <0x0 0x00036000 0x0 0x100>;
955 iommus = <&apps_smmu 0x3c0 0x0>;
966 reg = <0 0x00784000 0 0x8ff>;
971 reg = <0x133 0x1>;
978 reg = <0x0 0x008c0000 0x0 0x6000>;
982 iommus = <&apps_smmu 0xc3 0x0>;
990 reg = <0 0x00880000 0 0x4000>;
993 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
994 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 pinctrl-0 = <&qup_i2c0_default>;
1000 #size-cells = <0>;
1006 reg = <0 0x00880000 0 0x4000>;
1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 pinctrl-0 = <&qup_spi0_default>;
1018 #size-cells = <0>;
1024 reg = <0 0x00884000 0 0x4000>;
1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1031 pinctrl-0 = <&qup_i2c1_default>;
1034 #size-cells = <0>;
1040 reg = <0 0x00884000 0 0x4000>;
1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1048 pinctrl-0 = <&qup_spi1_default>;
1052 #size-cells = <0>;
1058 reg = <0 0x00888000 0 0x4000>;
1061 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1065 pinctrl-0 = <&qup_i2c2_default>;
1068 #size-cells = <0>;
1074 reg = <0 0x00888000 0 0x4000>;
1078 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1082 pinctrl-0 = <&qup_spi2_default>;
1086 #size-cells = <0>;
1092 reg = <0 0x0088c000 0 0x4000>;
1095 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1099 pinctrl-0 = <&qup_i2c3_default>;
1102 #size-cells = <0>;
1108 reg = <0 0x0088c000 0 0x4000>;
1112 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1116 pinctrl-0 = <&qup_spi3_default>;
1120 #size-cells = <0>;
1126 reg = <0 0x00890000 0 0x4000>;
1129 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1133 pinctrl-0 = <&qup_i2c4_default>;
1136 #size-cells = <0>;
1142 reg = <0 0x00890000 0 0x4000>;
1146 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1150 pinctrl-0 = <&qup_spi4_default>;
1154 #size-cells = <0>;
1160 reg = <0 0x00894000 0 0x4000>;
1163 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1167 pinctrl-0 = <&qup_i2c5_default>;
1170 #size-cells = <0>;
1176 reg = <0 0x00894000 0 0x4000>;
1180 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1184 pinctrl-0 = <&qup_spi5_default>;
1188 #size-cells = <0>;
1194 reg = <0 0x00898000 0 0x4000>;
1197 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1201 pinctrl-0 = <&qup_i2c6_default>;
1204 #size-cells = <0>;
1210 reg = <0 0x00898000 0 0x4000>;
1214 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1218 pinctrl-0 = <&qup_spi6_default>;
1222 #size-cells = <0>;
1228 reg = <0 0x0089c000 0 0x4000>;
1231 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1235 pinctrl-0 = <&qup_i2c7_default>;
1238 #size-cells = <0>;
1244 reg = <0 0x0089c000 0 0x4000>;
1248 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1252 pinctrl-0 = <&qup_spi7_default>;
1256 #size-cells = <0>;
1263 reg = <0 0x00a00000 0 0x60000>;
1278 dma-channel-mask = <0xfa>;
1279 iommus = <&apps_smmu 0x0616 0x0>;
1286 reg = <0x0 0x00ac0000 0x0 0x6000>;
1290 iommus = <&apps_smmu 0x603 0x0>;
1298 reg = <0 0x00a80000 0 0x4000>;
1301 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 pinctrl-0 = <&qup_i2c8_default>;
1308 #size-cells = <0>;
1314 reg = <0 0x00a80000 0 0x4000>;
1318 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 pinctrl-0 = <&qup_spi8_default>;
1326 #size-cells = <0>;
1332 reg = <0 0x00a84000 0 0x4000>;
1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1339 pinctrl-0 = <&qup_i2c9_default>;
1342 #size-cells = <0>;
1348 reg = <0 0x00a84000 0 0x4000>;
1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1356 pinctrl-0 = <&qup_spi9_default>;
1360 #size-cells = <0>;
1366 reg = <0x0 0x00a84000 0x0 0x4000>;
1369 pinctrl-0 = <&qup_uart9_default>;
1377 reg = <0 0x00a88000 0 0x4000>;
1380 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1384 pinctrl-0 = <&qup_i2c10_default>;
1387 #size-cells = <0>;
1393 reg = <0 0x00a88000 0 0x4000>;
1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1401 pinctrl-0 = <&qup_spi10_default>;
1405 #size-cells = <0>;
1411 reg = <0 0x00a8c000 0 0x4000>;
1414 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1418 pinctrl-0 = <&qup_i2c11_default>;
1421 #size-cells = <0>;
1427 reg = <0 0x00a8c000 0 0x4000>;
1431 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1435 pinctrl-0 = <&qup_spi11_default>;
1439 #size-cells = <0>;
1445 reg = <0x0 0x00a90000 0x0 0x4000>;
1454 reg = <0 0x00a90000 0 0x4000>;
1457 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1461 pinctrl-0 = <&qup_i2c12_default>;
1464 #size-cells = <0>;
1470 reg = <0 0x00a90000 0 0x4000>;
1474 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1478 pinctrl-0 = <&qup_spi12_default>;
1482 #size-cells = <0>;
1488 reg = <0 0x00094000 0 0x4000>;
1491 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1495 pinctrl-0 = <&qup_i2c16_default>;
1498 #size-cells = <0>;
1504 reg = <0 0x00a94000 0 0x4000>;
1508 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1512 pinctrl-0 = <&qup_spi16_default>;
1516 #size-cells = <0>;
1523 reg = <0 0x00c00000 0 0x60000>;
1538 dma-channel-mask = <0xfa>;
1539 iommus = <&apps_smmu 0x07b6 0x0>;
1546 reg = <0x0 0x00cc0000 0x0 0x6000>;
1551 iommus = <&apps_smmu 0x7a3 0x0>;
1559 reg = <0 0x00c80000 0 0x4000>;
1562 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 pinctrl-0 = <&qup_i2c17_default>;
1569 #size-cells = <0>;
1575 reg = <0 0x00c80000 0 0x4000>;
1579 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 pinctrl-0 = <&qup_spi17_default>;
1587 #size-cells = <0>;
1593 reg = <0 0x00c84000 0 0x4000>;
1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1600 pinctrl-0 = <&qup_i2c18_default>;
1603 #size-cells = <0>;
1609 reg = <0 0x00c84000 0 0x4000>;
1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1617 pinctrl-0 = <&qup_spi18_default>;
1621 #size-cells = <0>;
1627 reg = <0 0x00c88000 0 0x4000>;
1630 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1634 pinctrl-0 = <&qup_i2c19_default>;
1637 #size-cells = <0>;
1643 reg = <0 0x00c88000 0 0x4000>;
1647 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1651 pinctrl-0 = <&qup_spi19_default>;
1655 #size-cells = <0>;
1661 reg = <0 0x00c8c000 0 0x4000>;
1664 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1668 pinctrl-0 = <&qup_i2c13_default>;
1671 #size-cells = <0>;
1677 reg = <0 0x00c8c000 0 0x4000>;
1681 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1685 pinctrl-0 = <&qup_spi13_default>;
1689 #size-cells = <0>;
1695 reg = <0 0x00c90000 0 0x4000>;
1698 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1702 pinctrl-0 = <&qup_i2c14_default>;
1705 #size-cells = <0>;
1711 reg = <0 0x00c90000 0 0x4000>;
1715 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1719 pinctrl-0 = <&qup_spi14_default>;
1723 #size-cells = <0>;
1729 reg = <0 0x00c94000 0 0x4000>;
1732 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1736 pinctrl-0 = <&qup_i2c15_default>;
1739 #size-cells = <0>;
1745 reg = <0 0x00c94000 0 0x4000>;
1749 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1753 pinctrl-0 = <&qup_spi15_default>;
1757 #size-cells = <0>;
1764 reg = <0 0x01500000 0 0x7400>;
1771 reg = <0 0x01620000 0 0x19400>;
1778 reg = <0 0x0163a000 0 0x1000>;
1785 reg = <0 0x016e0000 0 0xd080>;
1792 reg = <0 0x01700000 0 0x20000>;
1799 reg = <0 0x01720000 0 0x7000>;
1806 reg = <0 0x01740000 0 0x1c100>;
1813 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1814 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1815 <0 0x09600000 0 0x50000>;
1823 reg = <0x0 0x010a2000 0x0 0x1000>,
1824 <0x0 0x010ad000 0x0 0x3000>;
1829 reg = <0 0x01c00000 0 0x3000>,
1830 <0 0x60000000 0 0xf1d>,
1831 <0 0x60000f20 0 0xa8>,
1832 <0 0x60001000 0 0x1000>,
1833 <0 0x60100000 0 0x100000>;
1836 linux,pci-domain = <0>;
1837 bus-range = <0x00 0xff>;
1843 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1844 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1849 interrupt-map-mask = <0 0 0 0x7>;
1850 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1851 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1852 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1853 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1871 <0x100 &apps_smmu 0x1d81 0x1>;
1885 pinctrl-0 = <&pcie0_default_state>;
1892 reg = <0 0x01c06000 0 0x1000>;
1905 #clock-cells = <0>;
1907 #phy-cells = <0>;
1920 reg = <0 0x01c08000 0 0x3000>,
1921 <0 0x40000000 0 0xf1d>,
1922 <0 0x40000f20 0 0xa8>,
1923 <0 0x40001000 0 0x1000>,
1924 <0 0x40100000 0 0x100000>;
1928 bus-range = <0x00 0xff>;
1934 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1935 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1940 interrupt-map-mask = <0 0 0 0x7>;
1941 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1942 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1943 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1944 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1964 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1965 <0x100 &apps_smmu 0x1e01 0x1>;
1979 pinctrl-0 = <&pcie1_default_state>;
1986 reg = <0 0x01c0e000 0 0x1000>;
1999 #clock-cells = <0>;
2001 #phy-cells = <0>;
2015 reg = <0 0x01d84000 0 0x2500>,
2016 <0 0x01d90000 0 0x8000>;
2026 iommus = <&apps_smmu 0x300 0>;
2050 <0 0>,
2051 <0 0>,
2053 <0 0>,
2054 <0 0>,
2055 <0 0>,
2056 <0 0>,
2057 <0 300000000>;
2064 reg = <0 0x01d87000 0 0x1000>;
2073 resets = <&ufs_mem_hc 0>;
2076 #phy-cells = <0>;
2083 reg = <0 0x01dc4000 0 0x24000>;
2086 qcom,ee = <0>;
2090 iommus = <&apps_smmu 0x502 0x0641>,
2091 <&apps_smmu 0x504 0x0011>,
2092 <&apps_smmu 0x506 0x0011>,
2093 <&apps_smmu 0x508 0x0011>,
2094 <&apps_smmu 0x512 0x0000>;
2099 reg = <0 0x01dfa000 0 0x6000>;
2102 iommus = <&apps_smmu 0x502 0x0641>,
2103 <&apps_smmu 0x504 0x0011>,
2104 <&apps_smmu 0x506 0x0011>,
2105 <&apps_smmu 0x508 0x0011>,
2106 <&apps_smmu 0x512 0x0000>;
2107 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2113 reg = <0x0 0x01f40000 0x0 0x20000>;
2119 reg = <0x0 0x01f60000 0x0 0x20000>;
2124 reg = <0x0 0x02400000 0x0 0x4040>;
2127 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2145 qcom,smem-states = <&slpi_smp2p_out 0>;
2162 #size-cells = <0>;
2167 iommus = <&apps_smmu 0x05a1 0x0>;
2173 iommus = <&apps_smmu 0x05a2 0x0>;
2179 iommus = <&apps_smmu 0x05a3 0x0>;
2188 reg = <0 0x02c00000 0 0x40000>;
2193 iommus = <&adreno_smmu 0 0x401>;
2214 opp-supported-hw = <0x2>;
2220 opp-supported-hw = <0x3>;
2226 opp-supported-hw = <0x3>;
2232 opp-supported-hw = <0x3>;
2238 opp-supported-hw = <0x3>;
2244 opp-supported-hw = <0x3>;
2252 reg = <0 0x02c6a000 0 0x30000>,
2253 <0 0x0b290000 0 0x10000>,
2254 <0 0x0b490000 0 0x10000>;
2272 iommus = <&adreno_smmu 5 0x400>;
2290 reg = <0 0x02c90000 0 0x9000>;
2305 reg = <0 0x02ca0000 0 0x10000>;
2327 reg = <0x0 0x03100000 0x0 0x300000>,
2328 <0x0 0x03500000 0x0 0x300000>,
2329 <0x0 0x03900000 0x0 0x300000>,
2330 <0x0 0x03D00000 0x0 0x300000>;
2333 gpio-ranges = <&tlmm 0 0 176>;
2343 drive-strength = <0x02>;
2676 reg = <0x0 0x04080000 0x0 0x4040>;
2679 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2698 qcom,smem-states = <&modem_smp2p_out 0>;
2713 reg = <0 0x06002000 0 0x1000>,
2714 <0 0x16280000 0 0x180000>;
2731 reg = <0 0x06041000 0 0x1000>;
2746 #size-cells = <0>;
2759 reg = <0 0x06042000 0 0x1000>;
2774 #size-cells = <0>;
2787 reg = <0 0x06043000 0 0x1000>;
2802 #size-cells = <0>;
2815 reg = <0 0x06045000 0 0x1000>;
2830 #size-cells = <0>;
2832 port@0 {
2833 reg = <0>;
2857 reg = <0 0x06046000 0 0x1000>;
2864 #size-cells = <0>;
2866 port@0 {
2867 reg = <0>;
2892 reg = <0 0x06047000 0 0x1000>;
2916 reg = <0 0x06048000 0 0x1000>;
2917 iommus = <&apps_smmu 0x05e0 0x0>;
2934 reg = <0 0x0604a000 0 0x1000>;
2941 #size-cells = <0>;
2963 reg = <0 0x06b08000 0 0x1000>;
2978 #size-cells = <0>;
2991 reg = <0 0x06b09000 0 0x1000>;
3015 reg = <0 0x06b0a000 0 0x1000>;
3040 reg = <0 0x07040000 0 0x1000>;
3060 reg = <0 0x07140000 0 0x1000>;
3080 reg = <0 0x07240000 0 0x1000>;
3100 reg = <0 0x07340000 0 0x1000>;
3120 reg = <0 0x07440000 0 0x1000>;
3140 reg = <0 0x07540000 0 0x1000>;
3160 reg = <0 0x07640000 0 0x1000>;
3180 reg = <0 0x07740000 0 0x1000>;
3200 reg = <0 0x07800000 0 0x1000>;
3215 #size-cells = <0>;
3217 port@0 {
3218 reg = <0>;
3277 reg = <0 0x07810000 0 0x1000>;
3301 reg = <0x0 0x08300000 0x0 0x4040>;
3304 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3320 qcom,smem-states = <&cdsp_smp2p_out 0>;
3337 #size-cells = <0>;
3342 iommus = <&apps_smmu 0x1001 0x0460>;
3348 iommus = <&apps_smmu 0x1002 0x0460>;
3354 iommus = <&apps_smmu 0x1003 0x0460>;
3360 iommus = <&apps_smmu 0x1004 0x0460>;
3366 iommus = <&apps_smmu 0x1005 0x0460>;
3372 iommus = <&apps_smmu 0x1006 0x0460>;
3378 iommus = <&apps_smmu 0x1007 0x0460>;
3384 iommus = <&apps_smmu 0x1008 0x0460>;
3395 reg = <0 0x088e2000 0 0x400>;
3397 #phy-cells = <0>;
3408 reg = <0 0x088e3000 0 0x400>;
3410 #phy-cells = <0>;
3420 reg = <0 0x088e8000 0 0x3000>;
3442 #size-cells = <0>;
3444 port@0 {
3445 reg = <0>;
3469 reg = <0 0x088eb000 0 0x1000>;
3480 #clock-cells = <0>;
3481 #phy-cells = <0>;
3493 reg = <0 0x08804000 0 0x1000>;
3503 iommus = <&apps_smmu 0x6a0 0x0>;
3504 qcom,dll-config = <0x0007642c>;
3505 qcom,ddr-config = <0x80040868>;
3506 power-domains = <&rpmhpd 0>;
3538 reg = <0 0x09160000 0 0x3200>;
3545 reg = <0 0x09680000 0 0x3e200>;
3552 reg = <0 0x0a6f8800 0 0x400>;
3587 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3588 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3593 reg = <0 0x0a600000 0 0xcd00>;
3595 iommus = <&apps_smmu 0x140 0>;
3603 #size-cells = <0>;
3605 port@0 {
3606 reg = <0>;
3624 reg = <0 0x0a8f8800 0 0x400>;
3659 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3660 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3665 reg = <0 0x0a800000 0 0xcd00>;
3667 iommus = <&apps_smmu 0x160 0>;
3677 reg = <0 0x0ac00000 0 0x1000>;
3684 reg = <0 0x0ae00000 0 0x1000>;
3687 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3688 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3703 iommus = <&apps_smmu 0x800 0x420>;
3713 reg = <0 0x0ae01000 0 0x8f000>,
3714 <0 0x0aeb0000 0 0x2008>;
3730 interrupts = <0>;
3734 #size-cells = <0>;
3736 port@0 {
3737 reg = <0>;
3785 reg = <0 0xae90000 0 0x200>,
3786 <0 0xae90200 0 0x200>,
3787 <0 0xae90400 0 0x600>,
3788 <0 0x0ae90a00 0 0x600>,
3789 <0 0x0ae91000 0 0x600>;
3812 #sound-dai-cells = <0>;
3821 #size-cells = <0>;
3823 port@0 {
3824 reg = <0>;
3865 reg = <0 0x0ae94000 0 0x400>;
3886 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3897 #size-cells = <0>;
3901 #size-cells = <0>;
3903 port@0 {
3904 reg = <0>;
3939 reg = <0 0x0ae94400 0 0x200>,
3940 <0 0x0ae94600 0 0x280>,
3941 <0 0x0ae94900 0 0x260>;
3947 #phy-cells = <0>;
3958 reg = <0 0x0ae96000 0 0x400>;
3979 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3990 #size-cells = <0>;
3994 #size-cells = <0>;
3996 port@0 {
3997 reg = <0>;
4013 reg = <0 0x0ae96400 0 0x200>,
4014 <0 0x0ae96600 0 0x280>,
4015 <0 0x0ae96900 0 0x260>;
4021 #phy-cells = <0>;
4033 reg = <0 0x0af00000 0 0x10000>;
4035 <&mdss_dsi0_phy 0>,
4037 <&mdss_dsi1_phy 0>,
4057 reg = <0 0x0b220000 0 0x30000>;
4058 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4067 reg = <0x0 0x0c300000 0x0 0x400>;
4069 mboxes = <&apss_shared 0>;
4071 #clock-cells = <0>;
4076 reg = <0 0x0c3f0000 0 0x400>;
4081 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4082 <0 0x0c222000 0 0x1ff>; /* SROT */
4092 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4093 <0 0x0c223000 0 0x1ff>; /* SROT */
4103 reg = <0x0 0x0c440000 0x0 0x0001100>,
4104 <0x0 0x0c600000 0x0 0x2000000>,
4105 <0x0 0x0e600000 0x0 0x0100000>,
4106 <0x0 0x0e700000 0x0 0x00a0000>,
4107 <0x0 0x0c40a000 0x0 0x0026000>;
4111 qcom,ee = <0>;
4112 qcom,channel = <0>;
4114 #size-cells = <0>;
4121 reg = <0 0x15000000 0 0x100000>;
4209 reg = <0x0 0x17300000 0x0 0x4040>;
4212 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4228 qcom,smem-states = <&adsp_smp2p_out 0>;
4245 #size-cells = <0>;
4250 iommus = <&apps_smmu 0x1b23 0x0>;
4256 iommus = <&apps_smmu 0x1b24 0x0>;
4262 iommus = <&apps_smmu 0x1b25 0x0>;
4272 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4273 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4280 reg = <0x0 0x17c00000 0x0 0x1000>;
4286 reg = <0 0x17c10000 0 0x1000>;
4288 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4294 ranges = <0 0 0 0x20000000>;
4296 reg = <0x0 0x17c20000 0x0 0x1000>;
4300 frame-number = <0>;
4303 reg = <0x17c21000 0x1000>,
4304 <0x17c22000 0x1000>;
4310 reg = <0x17c23000 0x1000>;
4317 reg = <0x17c25000 0x1000>;
4324 reg = <0x17c26000 0x1000>;
4331 reg = <0x17c29000 0x1000>;
4338 reg = <0x17c2b000 0x1000>;
4345 reg = <0x17c2d000 0x1000>;
4353 reg = <0x0 0x18200000 0x0 0x10000>,
4354 <0x0 0x18210000 0x0 0x10000>,
4355 <0x0 0x18220000 0x0 0x10000>;
4356 reg-names = "drv-0", "drv-1", "drv-2";
4360 qcom,tcs-offset = <0xd00>;
4436 reg = <0 0x18321000 0 0x1400>;
4446 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4447 <0 0x18327800 0 0x1400>;
4460 reg = <0 0x18350800 0 0x400>;
4472 reg = <0 0x18358800 0 0x400>;
4484 reg = <0 0x18800000 0 0x800000>;
4501 iommus = <&apps_smmu 0x0640 0x1>;
4511 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5047 thermal-sensors = <&tsens0 0>;
5117 thermal-sensors = <&tsens1 0>;