Lines Matching +full:0 +full:x0a400000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
91 reg = <0x0 0x200>;
92 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x300>;
113 clocks = <&cpufreq_hw 0>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
133 reg = <0x0 0x400>;
134 clocks = <&cpufreq_hw 0>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
154 reg = <0x0 0x500>;
155 clocks = <&cpufreq_hw 0>;
158 qcom,freq-domain = <&cpufreq_hw 0>;
175 reg = <0x0 0x600>;
196 reg = <0x0 0x700>;
253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
256 arm,psci-suspend-param = <0x40000003>;
263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
266 arm,psci-suspend-param = <0x40000004>;
273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
276 arm,psci-suspend-param = <0x40000003>;
286 arm,psci-suspend-param = <0x40000004>;
295 CLUSTER_SLEEP_0: cluster-sleep-0 {
297 arm,psci-suspend-param = <0x41000044>;
321 #power-domain-cells = <0>;
327 <89 314>, /* TSENS0 0C */
328 <90 315>, /* TSENS1 0C */
336 reg = <0x0 0x80000000 0x0 0x0>;
459 #power-domain-cells = <0>;
465 #power-domain-cells = <0>;
471 #power-domain-cells = <0>;
477 #power-domain-cells = <0>;
483 #power-domain-cells = <0>;
489 #power-domain-cells = <0>;
495 #power-domain-cells = <0>;
501 #power-domain-cells = <0>;
507 #power-domain-cells = <0>;
538 reg = <0 0x80000000 0 0x600000>;
543 reg = <0 0x80700000 0 0x100000>;
548 reg = <0 0x80880000 0 0x14000>;
554 reg = <0 0x80900000 0 0x200000>;
560 reg = <0 0x80b00000 0 0x100000>;
565 reg = <0 0x80c00000 0 0x1e00000>;
570 reg = <0 0x85e00000 0 0x100000>;
575 reg = <0 0x86500000 0 0x200000>;
580 reg = <0 0x86700000 0 0x2000000>;
585 reg = <0 0x88700000 0 0x1e00000>;
590 reg = <0 0x8a500000 0 0x500000>;
595 reg = <0 0x8aa00000 0 0x10000>;
600 reg = <0 0x8aa10000 0 0xa000>;
605 reg = <0 0x8aa1a000 0 0x2000>;
610 reg = <0 0x8b800000 0 0x10000000>;
615 reg = <0 0xc0000000 0 0x5100000>;
621 reg = <0 0xf3900000 0 0x280000>;
629 reg = <0 0xffb00000 0 0xc0000>;
634 reg = <0 0xffbc0000 0 0x80000>;
639 reg = <0 0xffd00000 0 0x1000>;
724 qcom,local-pid = <0>;
748 qcom,local-pid = <0>;
772 qcom,local-pid = <0>;
804 soc: soc@0 {
807 ranges = <0 0 0 0 0x10 0>;
808 dma-ranges = <0 0 0 0 0x10 0>;
813 reg = <0 0x00208000 0 0x1000>;
822 reg = <0x0 0x00340000 0x0 0x40000>;
828 reg = <0 0x00500000 0 0x800000>;
830 gpio-ranges = <&tlmm 0 0 157>;
953 reg = <0 0x01400000 0 0x1f0000>;
964 reg = <0 0x0162b000 0 0x400>;
969 #phy-cells = <0>;
976 reg = <0 0x01c40000 0 0x1100>,
977 <0 0x01e00000 0 0x2000000>,
978 <0 0x03e00000 0 0x100000>,
979 <0 0x03f00000 0 0xa0000>,
980 <0 0x01c0a000 0 0x26000>;
984 qcom,ee = <0>;
985 qcom,channel = <0>;
987 #size-cells = <0>;
994 reg = <0 0x04411000 0 0x140>, /* TM */
995 <0 0x04410000 0 0x20>; /* SROT */
1005 reg = <0 0x04413000 0 0x140>, /* TM */
1006 <0 0x04412000 0 0x20>; /* SROT */
1016 reg = <0 0x045f0000 0 0x7000>;
1019 ranges = <0 0x0 0x045f0000 0x7000>;
1022 reg = <0x1b8 0x48>;
1028 reg = <0 0x04690000 0 0x400>;
1033 reg = <0 0x04784000 0 0x1000>;
1044 iommus = <&apps_smmu 0x40 0x0>;
1046 pinctrl-0 = <&sdc2_on_state>;
1050 qcom,dll-config = <0x0007642c>;
1051 qcom,ddr-config = <0x80040868>;
1075 reg = <0 0x04a00000 0 0x60000>;
1087 dma-channel-mask = <0x1f>;
1088 iommus = <&apps_smmu 0x16 0x0>;
1095 reg = <0x0 0x04ac0000 0x0 0x2000>;
1099 iommus = <&apps_smmu 0x3 0x0>;
1107 reg = <0x0 0x04a80000 0x0 0x4000>;
1112 pinctrl-0 = <&qup_i2c0_default>;
1113 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1114 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1117 #size-cells = <0>;
1123 reg = <0x0 0x04a80000 0x0 0x4000>;
1128 pinctrl-0 = <&qup_spi0_default>;
1131 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1132 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1135 #size-cells = <0>;
1141 reg = <0x0 0x04a84000 0x0 0x4000>;
1146 pinctrl-0 = <&qup_i2c1_default>;
1147 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1151 #size-cells = <0>;
1157 reg = <0x0 0x04a84000 0x0 0x4000>;
1163 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1167 #size-cells = <0>;
1173 reg = <0x0 0x04a84000 0x0 0x4000>;
1179 pinctrl-0 = <&qup_uart1_default>;
1186 reg = <0x0 0x04a88000 0x0 0x4000>;
1191 pinctrl-0 = <&qup_i2c2_default>;
1192 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1196 #size-cells = <0>;
1202 reg = <0x0 0x04a88000 0x0 0x4000>;
1208 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1212 #size-cells = <0>;
1227 reg = <0 0x04c00000 0 0x60000>;
1239 dma-channel-mask = <0x1f>;
1240 iommus = <&apps_smmu 0xd6 0x0>;
1247 reg = <0x0 0x04cc0000 0x0 0x2000>;
1251 iommus = <&apps_smmu 0xc3 0x0>;
1259 reg = <0x0 0x04c80000 0x0 0x4000>;
1263 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1264 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1267 #size-cells = <0>;
1273 reg = <0x0 0x04c80000 0x0 0x4000>;
1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1280 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1283 #size-cells = <0>;
1289 reg = <0x0 0x04c84000 0x0 0x4000>;
1293 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1297 #size-cells = <0>;
1303 reg = <0x0 0x04c84000 0x0 0x4000>;
1309 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1313 #size-cells = <0>;
1319 reg = <0x0 0x04c88000 0x0 0x4000>;
1324 pinctrl-0 = <&qup_i2c8_default>;
1325 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1329 #size-cells = <0>;
1335 reg = <0x0 0x04c88000 0x0 0x4000>;
1341 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1345 #size-cells = <0>;
1351 reg = <0x0 0x04c8c000 0x0 0x4000>;
1355 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1359 #size-cells = <0>;
1365 reg = <0x0 0x04c8c000 0x0 0x4000>;
1371 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1375 #size-cells = <0>;
1381 reg = <0x0 0x04c90000 0x0 0x4000>;
1386 pinctrl-0 = <&qup_i2c10_default>;
1387 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1391 #size-cells = <0>;
1397 reg = <0x0 0x04c90000 0x0 0x4000>;
1403 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1407 #size-cells = <0>;
1414 reg = <0 0x04ef8800 0 0x400>;
1461 reg = <0 0x04e00000 0 0xcd00>;
1466 iommus = <&apps_smmu 0xe0 0x0>;
1469 snps,hird-threshold = /bits/ 8 <0x10>;
1483 reg = <0 0x05940000 0 0x10000>;
1505 reg = <0 0x05990000 0 0x9000>;
1519 reg = <0 0x06000000 0 0x4040>;
1522 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1542 qcom,smem-states = <&smp2p_modem_out 0>;
1560 reg = <0 0x0a400000 0 0x100>;
1563 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1579 qcom,smem-states = <&smp2p_adsp_out 0>;
1598 reg = <0x0 0x0b000000 0x0 0x100000>;
1601 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1616 qcom,smem-states = <&smp2p_cdsp_out 0>;
1634 reg = <0 0x0c125000 0 0x1000>;
1635 ranges = <0 0 0x0c125000 0x1000>;
1642 reg = <0x94c 0xc8>;
1648 reg = <0 0x0c600000 0 0x100000>;
1724 reg = <0 0x0c800000 0 0x800000>;
1739 iommus = <&apps_smmu 0x80 0x1>;
1746 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */
1747 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */
1751 redistributor-stride = <0 0x20000>;
1757 reg = <0 0x0f420000 0 0x1000>;
1758 ranges = <0 0 0 0x20000000>;
1763 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>;
1766 frame-number = <0>;
1770 reg = <0x0f243000 0x1000>;
1777 reg = <0x0f425000 0x1000>;
1784 reg = <0x0f427000 0x1000>;
1791 reg = <0x0f429000 0x1000>;
1798 reg = <0x0f42b000 0x1000>;
1805 reg = <0x0f42d000 0x1000>;
1814 reg = <0 0x0fd90000 0 0x1000>;
1823 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
1830 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
1838 polling-delay-passive = <0>;
1839 polling-delay = <0>;
1841 thermal-sensors = <&tsens0 0>;
1865 polling-delay-passive = <0>;
1866 polling-delay = <0>;
1892 polling-delay-passive = <0>;
1893 polling-delay = <0>;
1919 polling-delay-passive = <0>;
1920 polling-delay = <0>;
1946 polling-delay-passive = <0>;
1947 polling-delay = <0>;
1973 polling-delay-passive = <0>;
1974 polling-delay = <0>;
2000 polling-delay-passive = <0>;
2001 polling-delay = <0>;
2027 polling-delay-passive = <0>;
2028 polling-delay = <0>;
2054 polling-delay-passive = <0>;
2055 polling-delay = <0>;
2081 polling-delay-passive = <0>;
2082 polling-delay = <0>;
2108 polling-delay-passive = <0>;
2109 polling-delay = <0>;
2135 polling-delay-passive = <0>;
2136 polling-delay = <0>;
2162 polling-delay-passive = <0>;
2163 polling-delay = <0>;
2189 polling-delay-passive = <0>;
2190 polling-delay = <0>;
2216 polling-delay-passive = <0>;
2217 polling-delay = <0>;
2243 polling-delay-passive = <0>;
2244 polling-delay = <0>;
2246 thermal-sensors = <&tsens1 0>;
2270 polling-delay-passive = <0>;
2271 polling-delay = <0>;
2297 polling-delay-passive = <0>;
2298 polling-delay = <0>;
2324 polling-delay-passive = <0>;
2325 polling-delay = <0>;
2351 polling-delay-passive = <0>;
2352 polling-delay = <0>;
2378 polling-delay-passive = <0>;
2379 polling-delay = <0>;
2405 polling-delay-passive = <0>;
2406 polling-delay = <0>;
2432 polling-delay-passive = <0>;
2433 polling-delay = <0>;
2459 polling-delay-passive = <0>;
2460 polling-delay = <0>;
2486 polling-delay-passive = <0>;
2487 polling-delay = <0>;
2513 polling-delay-passive = <0>;
2514 polling-delay = <0>;
2545 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;