Lines Matching +full:1 +full:f200000
54 CPU1: cpu@1 {
164 #reset-cells = <1>;
200 #clock-cells = <1>;
207 #power-domain-cells = <1>;
376 #address-cells = <1>;
377 #size-cells = <1>;
384 #hwlock-cells = <1>;
668 #clock-cells = <1>;
669 #reset-cells = <1>;
670 #power-domain-cells = <1>;
688 spmi_bus: spmi@1c40000 {
754 pinctrl-1 = <&sdc2_off_state>;
799 #reset-cells = <1>;
804 lanes-per-direction = <1>;
855 #address-cells = <1>;
856 #size-cells = <1>;
867 pinctrl-1 = <&qup_i2c0_sleep>;
870 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
872 #address-cells = <1>;
884 pinctrl-1 = <&qup_spi0_sleep>;
887 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
889 #address-cells = <1>;
901 pinctrl-1 = <&qup_i2c1_sleep>;
903 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
904 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
906 #address-cells = <1>;
918 pinctrl-1 = <&qup_i2c2_sleep>;
921 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
923 #address-cells = <1>;
935 pinctrl-1 = <&qup_spi2_sleep>;
938 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
940 #address-cells = <1>;
952 pinctrl-1 = <&qup_i2c3_sleep>;
955 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
957 #address-cells = <1>;
969 pinctrl-1 = <&qup_i2c4_sleep>;
972 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
974 #address-cells = <1>;
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1017 pinctrl-1 = <&qup_i2c5_sleep>;
1020 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1022 #address-cells = <1>;
1034 pinctrl-1 = <&qup_spi5_sleep>;
1037 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1039 #address-cells = <1>;
1051 pinctrl-1 = <&qup_i2c6_sleep>;
1053 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1054 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1056 #address-cells = <1>;
1068 pinctrl-1 = <&qup_spi6_sleep>;
1070 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1071 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1073 #address-cells = <1>;
1085 pinctrl-1 = <&qup_i2c7_sleep>;
1088 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1090 #address-cells = <1>;
1102 pinctrl-1 = <&qup_i2c8_sleep>;
1105 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1107 #address-cells = <1>;
1119 pinctrl-1 = <&qup_spi8_sleep>;
1122 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1124 #address-cells = <1>;
1136 pinctrl-1 = <&qup_i2c9_sleep>;
1139 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1141 #address-cells = <1>;
1153 pinctrl-1 = <&qup_spi9_sleep>;
1156 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1158 #address-cells = <1>;
1167 #address-cells = <1>;
1168 #size-cells = <1>;
1222 #interrupt-cells = <1>;
1235 #address-cells = <1>;
1236 #size-cells = <1>;
1271 #address-cells = <1>;
1334 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1342 #address-cells = <1>;
1348 #address-cells = <1>;
1358 port@1 {
1359 reg = <1>;
1389 #clock-cells = <1>;
1410 <&mdss_dsi0_phy 1>,
1428 #clock-cells = <1>;
1429 #power-domain-cells = <1>;
1501 #global-interrupts = <1>;
1510 #mbox-cells = <1>;
1515 #address-cells = <1>;
1516 #size-cells = <1>;
1530 frame-number = <1>;
1572 intc: interrupt-controller@f200000 {
1584 interrupts = <GIC_PPI 1 0xf08