Lines Matching +full:sm6350 +full:- +full:dpu
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
39 #address-cells = <2>;
40 #size-cells = <0>;
47 capacity-dmips-mhz = <1024>;
48 dynamic-power-coefficient = <100>;
49 enable-method = "psci";
50 next-level-cache = <&L2_0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
52 power-domains = <&CPU_PD0>;
53 power-domain-names = "psci";
54 L2_0: l2-cache {
56 cache-level = <2>;
57 cache-unified;
66 capacity-dmips-mhz = <1024>;
67 dynamic-power-coefficient = <100>;
68 enable-method = "psci";
69 next-level-cache = <&L2_0>;
70 qcom,freq-domain = <&cpufreq_hw 0>;
71 power-domains = <&CPU_PD1>;
72 power-domain-names = "psci";
80 capacity-dmips-mhz = <1024>;
81 dynamic-power-coefficient = <100>;
82 enable-method = "psci";
83 next-level-cache = <&L2_0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 power-domains = <&CPU_PD2>;
86 power-domain-names = "psci";
94 capacity-dmips-mhz = <1024>;
95 dynamic-power-coefficient = <100>;
96 enable-method = "psci";
97 next-level-cache = <&L2_0>;
98 qcom,freq-domain = <&cpufreq_hw 0>;
99 power-domains = <&CPU_PD3>;
100 power-domain-names = "psci";
108 enable-method = "psci";
109 capacity-dmips-mhz = <1638>;
110 dynamic-power-coefficient = <282>;
111 next-level-cache = <&L2_1>;
112 qcom,freq-domain = <&cpufreq_hw 1>;
113 power-domains = <&CPU_PD4>;
114 power-domain-names = "psci";
115 L2_1: l2-cache {
117 cache-level = <2>;
118 cache-unified;
127 capacity-dmips-mhz = <1638>;
128 dynamic-power-coefficient = <282>;
129 enable-method = "psci";
130 next-level-cache = <&L2_1>;
131 qcom,freq-domain = <&cpufreq_hw 1>;
132 power-domains = <&CPU_PD5>;
133 power-domain-names = "psci";
141 capacity-dmips-mhz = <1638>;
142 dynamic-power-coefficient = <282>;
143 enable-method = "psci";
144 next-level-cache = <&L2_1>;
145 qcom,freq-domain = <&cpufreq_hw 1>;
146 power-domains = <&CPU_PD6>;
147 power-domain-names = "psci";
155 capacity-dmips-mhz = <1638>;
156 dynamic-power-coefficient = <282>;
157 enable-method = "psci";
158 next-level-cache = <&L2_1>;
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 power-domains = <&CPU_PD7>;
161 power-domain-names = "psci";
164 cpu-map {
202 idle-states {
203 entry-method = "psci";
205 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
206 compatible = "arm,idle-state";
207 idle-state-name = "silver-rail-power-collapse";
208 arm,psci-suspend-param = <0x40000003>;
209 entry-latency-us = <290>;
210 exit-latency-us = <376>;
211 min-residency-us = <1182>;
212 local-timer-stop;
215 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
216 compatible = "arm,idle-state";
217 idle-state-name = "gold-rail-power-collapse";
218 arm,psci-suspend-param = <0x40000003>;
219 entry-latency-us = <297>;
220 exit-latency-us = <324>;
221 min-residency-us = <1110>;
222 local-timer-stop;
226 domain-idle-states {
227 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
229 compatible = "domain-idle-state";
230 arm,psci-suspend-param = <0x40000022>;
231 entry-latency-us = <360>;
232 exit-latency-us = <421>;
233 min-residency-us = <782>;
236 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
238 compatible = "domain-idle-state";
239 arm,psci-suspend-param = <0x41000044>;
240 entry-latency-us = <800>;
241 exit-latency-us = <2118>;
242 min-residency-us = <7376>;
245 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
247 compatible = "domain-idle-state";
248 arm,psci-suspend-param = <0x40000042>;
249 entry-latency-us = <314>;
250 exit-latency-us = <345>;
251 min-residency-us = <660>;
254 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
256 compatible = "domain-idle-state";
257 arm,psci-suspend-param = <0x41000044>;
258 entry-latency-us = <640>;
259 exit-latency-us = <1654>;
260 min-residency-us = <8094>;
267 compatible = "qcom,scm-sm6115", "qcom,scm";
268 #reset-cells = <1>;
280 qup_opp_table: opp-table-qup {
281 compatible = "operating-points-v2";
283 opp-75000000 {
284 opp-hz = /bits/ 64 <75000000>;
285 required-opps = <&rpmpd_opp_low_svs>;
288 opp-100000000 {
289 opp-hz = /bits/ 64 <100000000>;
290 required-opps = <&rpmpd_opp_svs>;
293 opp-128000000 {
294 opp-hz = /bits/ 64 <128000000>;
295 required-opps = <&rpmpd_opp_nom>;
300 compatible = "arm,armv8-pmuv3";
305 compatible = "arm,psci-1.0";
308 CPU_PD0: power-domain-cpu0 {
309 #power-domain-cells = <0>;
310 power-domains = <&CLUSTER_0_PD>;
311 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
314 CPU_PD1: power-domain-cpu1 {
315 #power-domain-cells = <0>;
316 power-domains = <&CLUSTER_0_PD>;
317 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
320 CPU_PD2: power-domain-cpu2 {
321 #power-domain-cells = <0>;
322 power-domains = <&CLUSTER_0_PD>;
323 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
326 CPU_PD3: power-domain-cpu3 {
327 #power-domain-cells = <0>;
328 power-domains = <&CLUSTER_0_PD>;
329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
332 CPU_PD4: power-domain-cpu4 {
333 #power-domain-cells = <0>;
334 power-domains = <&CLUSTER_1_PD>;
335 domain-idle-states = <&BIG_CPU_SLEEP_0>;
338 CPU_PD5: power-domain-cpu5 {
339 #power-domain-cells = <0>;
340 power-domains = <&CLUSTER_1_PD>;
341 domain-idle-states = <&BIG_CPU_SLEEP_0>;
344 CPU_PD6: power-domain-cpu6 {
345 #power-domain-cells = <0>;
346 power-domains = <&CLUSTER_1_PD>;
347 domain-idle-states = <&BIG_CPU_SLEEP_0>;
350 CPU_PD7: power-domain-cpu7 {
351 #power-domain-cells = <0>;
352 power-domains = <&CLUSTER_1_PD>;
353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
356 CLUSTER_0_PD: power-domain-cpu-cluster0 {
357 #power-domain-cells = <0>;
358 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
361 CLUSTER_1_PD: power-domain-cpu-cluster1 {
362 #power-domain-cells = <0>;
363 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
368 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
370 glink-edge {
371 compatible = "qcom,glink-rpm";
374 qcom,rpm-msg-ram = <&rpm_msg_ram>;
377 rpm_requests: rpm-requests {
378 compatible = "qcom,rpm-sm6115";
379 qcom,glink-channels = "rpm_requests";
381 rpmcc: clock-controller {
382 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
384 clock-names = "xo";
385 #clock-cells = <1>;
388 rpmpd: power-controller {
389 compatible = "qcom,sm6115-rpmpd";
390 #power-domain-cells = <1>;
391 operating-points-v2 = <&rpmpd_opp_table>;
393 rpmpd_opp_table: opp-table {
394 compatible = "operating-points-v2";
397 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
401 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
405 opp-level = <RPM_SMD_LEVEL_SVS>;
409 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
413 opp-level = <RPM_SMD_LEVEL_NOM>;
417 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
421 opp-level = <RPM_SMD_LEVEL_TURBO>;
425 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
433 reserved_memory: reserved-memory {
434 #address-cells = <2>;
435 #size-cells = <2>;
440 no-map;
445 no-map;
450 no-map;
456 no-map;
459 qcom,rpm-msg-ram = <&rpm_msg_ram>;
464 no-map;
469 no-map;
474 no-map;
479 no-map;
484 no-map;
489 no-map;
494 no-map;
499 no-map;
504 no-map;
509 no-map;
514 no-map;
519 no-map;
523 compatible = "qcom,rmtfs-mem";
525 no-map;
527 qcom,client-id = <1>;
532 smp2p-adsp {
540 qcom,local-pid = <0>;
541 qcom,remote-pid = <2>;
543 adsp_smp2p_out: master-kernel {
544 qcom,entry-name = "master-kernel";
545 #qcom,smem-state-cells = <1>;
548 adsp_smp2p_in: slave-kernel {
549 qcom,entry-name = "slave-kernel";
551 interrupt-controller;
552 #interrupt-cells = <2>;
556 smp2p-cdsp {
564 qcom,local-pid = <0>;
565 qcom,remote-pid = <5>;
567 cdsp_smp2p_out: master-kernel {
568 qcom,entry-name = "master-kernel";
569 #qcom,smem-state-cells = <1>;
572 cdsp_smp2p_in: slave-kernel {
573 qcom,entry-name = "slave-kernel";
575 interrupt-controller;
576 #interrupt-cells = <2>;
580 smp2p-mpss {
588 qcom,local-pid = <0>;
589 qcom,remote-pid = <1>;
591 modem_smp2p_out: master-kernel {
592 qcom,entry-name = "master-kernel";
593 #qcom,smem-state-cells = <1>;
596 modem_smp2p_in: slave-kernel {
597 qcom,entry-name = "slave-kernel";
599 interrupt-controller;
600 #interrupt-cells = <2>;
605 compatible = "simple-bus";
606 #address-cells = <2>;
607 #size-cells = <2>;
609 dma-ranges = <0 0 0 0 0x10 0>;
612 compatible = "qcom,tcsr-mutex";
614 #hwlock-cells = <1>;
618 compatible = "qcom,sm6115-tlmm";
622 reg-names = "west", "south", "east";
624 gpio-controller;
625 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
626 #gpio-cells = <2>;
627 interrupt-controller;
628 #interrupt-cells = <2>;
630 qup_i2c0_default: qup-i2c0-default-state {
633 drive-strength = <2>;
634 bias-pull-up;
637 qup_i2c1_default: qup-i2c1-default-state {
640 drive-strength = <2>;
641 bias-pull-up;
644 qup_i2c2_default: qup-i2c2-default-state {
647 drive-strength = <2>;
648 bias-pull-up;
651 qup_i2c3_default: qup-i2c3-default-state {
654 drive-strength = <2>;
655 bias-pull-up;
658 qup_i2c4_default: qup-i2c4-default-state {
661 drive-strength = <2>;
662 bias-pull-up;
665 qup_i2c5_default: qup-i2c5-default-state {
668 drive-strength = <2>;
669 bias-pull-up;
672 qup_spi0_default: qup-spi0-default-state {
675 drive-strength = <2>;
676 bias-pull-up;
679 qup_spi1_default: qup-spi1-default-state {
682 drive-strength = <2>;
683 bias-pull-up;
686 qup_spi2_default: qup-spi2-default-state {
689 drive-strength = <2>;
690 bias-pull-up;
693 qup_spi3_default: qup-spi3-default-state {
696 drive-strength = <2>;
697 bias-pull-up;
700 qup_spi4_default: qup-spi4-default-state {
703 drive-strength = <2>;
704 bias-pull-up;
707 qup_spi5_default: qup-spi5-default-state {
710 drive-strength = <2>;
711 bias-pull-up;
714 sdc1_state_on: sdc1-on-state {
715 clk-pins {
717 bias-disable;
718 drive-strength = <16>;
721 cmd-pins {
723 bias-pull-up;
724 drive-strength = <10>;
727 data-pins {
729 bias-pull-up;
730 drive-strength = <10>;
733 rclk-pins {
735 bias-pull-down;
739 sdc1_state_off: sdc1-off-state {
740 clk-pins {
742 bias-disable;
743 drive-strength = <2>;
746 cmd-pins {
748 bias-pull-up;
749 drive-strength = <2>;
752 data-pins {
754 bias-pull-up;
755 drive-strength = <2>;
758 rclk-pins {
760 bias-pull-down;
764 sdc2_state_on: sdc2-on-state {
765 clk-pins {
767 bias-disable;
768 drive-strength = <16>;
771 cmd-pins {
773 bias-pull-up;
774 drive-strength = <10>;
777 data-pins {
779 bias-pull-up;
780 drive-strength = <10>;
784 sdc2_state_off: sdc2-off-state {
785 clk-pins {
787 bias-disable;
788 drive-strength = <2>;
791 cmd-pins {
793 bias-pull-up;
794 drive-strength = <2>;
797 data-pins {
799 bias-pull-up;
800 drive-strength = <2>;
805 gcc: clock-controller@1400000 {
806 compatible = "qcom,gcc-sm6115";
809 clock-names = "bi_tcxo", "sleep_clk";
810 #clock-cells = <1>;
811 #reset-cells = <1>;
812 #power-domain-cells = <1>;
816 compatible = "qcom,sm6115-qusb2-phy";
818 #phy-cells = <0>;
821 clock-names = "cfg_ahb", "ref";
824 nvmem-cells = <&qusb2_hstx_trim>;
829 cryptobam: dma-controller@1b04000 {
830 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
834 clock-names = "bam_clk";
835 #dma-cells = <1>;
837 qcom,controlled-remotely;
846 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
849 clock-names = "core";
852 dma-names = "rx", "tx";
861 compatible = "qcom,sm6115-qmp-usb3-phy";
868 clock-names = "cfg_ahb",
875 reset-names = "phy", "phy_phy";
877 #clock-cells = <0>;
878 clock-output-names = "usb3_phy_pipe_clk_src";
880 #phy-cells = <0>;
886 compatible = "qcom,sm6115-snoc";
892 clock-names = "cpu_axi",
896 #interconnect-cells = <2>;
898 clk_virt: interconnect-clk {
899 compatible = "qcom,sm6115-clk-virt";
900 #interconnect-cells = <2>;
903 mmrt_virt: interconnect-mmrt {
904 compatible = "qcom,sm6115-mmrt-virt";
905 #interconnect-cells = <2>;
908 mmnrt_virt: interconnect-mmnrt {
909 compatible = "qcom,sm6115-mmnrt-virt";
910 #interconnect-cells = <2>;
915 compatible = "qcom,sm6115-cnoc";
918 clock-names = "usb_axi";
919 #interconnect-cells = <2>;
923 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
925 #address-cells = <1>;
926 #size-cells = <1>;
928 qusb2_hstx_trim: hstx-trim@25b {
933 gpu_speed_bin: gpu-speed-bin@6006 {
940 compatible = "qcom,prng-ee";
943 clock-names = "core";
947 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
951 operating-points-v2 = <&cpu_bwmon_opp_table>;
955 cpu_bwmon_opp_table: opp-table {
956 compatible = "operating-points-v2";
958 opp-0 {
959 opp-peak-kBps = <(200 * 4 * 1000)>;
962 opp-1 {
963 opp-peak-kBps = <(300 * 4 * 1000)>;
966 opp-2 {
967 opp-peak-kBps = <(451 * 4 * 1000)>;
970 opp-3 {
971 opp-peak-kBps = <(547 * 4 * 1000)>;
974 opp-4 {
975 opp-peak-kBps = <(681 * 4 * 1000)>;
978 opp-5 {
979 opp-peak-kBps = <(768 * 4 * 1000)>;
982 opp-6 {
983 opp-peak-kBps = <(1017 * 4 * 1000)>;
986 opp-7 {
987 opp-peak-kBps = <(1353 * 4 * 1000)>;
990 opp-8 {
991 opp-peak-kBps = <(1555 * 4 * 1000)>;
994 opp-9 {
995 opp-peak-kBps = <(1804 * 4 * 1000)>;
1001 compatible = "qcom,spmi-pmic-arb";
1007 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1008 interrupt-names = "periph_irq";
1012 #address-cells = <2>;
1013 #size-cells = <0>;
1014 interrupt-controller;
1015 #interrupt-cells = <4>;
1018 tsens0: thermal-sensor@4411000 {
1019 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1025 interrupt-names = "uplow", "critical";
1026 #thermal-sensor-cells = <1>;
1030 compatible = "qcom,sm6115-bimc";
1032 #interconnect-cells = <2>;
1036 compatible = "qcom,rpm-msg-ram";
1041 compatible = "qcom,rpm-stats";
1046 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1050 reg-names = "hc", "cqhci", "ice";
1054 interrupt-names = "hc_irq", "pwr_irq";
1060 clock-names = "iface", "core", "xo", "ice";
1062 power-domains = <&rpmpd SM6115_VDDCX>;
1063 operating-points-v2 = <&sdhc1_opp_table>;
1068 interconnect-names = "sdhc-ddr",
1069 "cpu-sdhc";
1071 bus-width = <8>;
1074 sdhc1_opp_table: opp-table {
1075 compatible = "operating-points-v2";
1077 opp-100000000 {
1078 opp-hz = /bits/ 64 <100000000>;
1079 required-opps = <&rpmpd_opp_low_svs>;
1080 opp-peak-kBps = <250000 133320>;
1081 opp-avg-kBps = <102400 65000>;
1084 opp-192000000 {
1085 opp-hz = /bits/ 64 <192000000>;
1086 required-opps = <&rpmpd_opp_low_svs>;
1087 opp-peak-kBps = <800000 300000>;
1088 opp-avg-kBps = <204800 200000>;
1091 opp-384000000 {
1092 opp-hz = /bits/ 64 <384000000>;
1093 required-opps = <&rpmpd_opp_svs_plus>;
1094 opp-peak-kBps = <800000 300000>;
1095 opp-avg-kBps = <204800 200000>;
1101 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1103 reg-names = "hc";
1107 interrupt-names = "hc_irq", "pwr_irq";
1112 clock-names = "iface", "core", "xo";
1114 power-domains = <&rpmpd SM6115_VDDCX>;
1115 operating-points-v2 = <&sdhc2_opp_table>;
1122 interconnect-names = "sdhc-ddr",
1123 "cpu-sdhc";
1125 bus-width = <4>;
1126 qcom,dll-config = <0x0007642c>;
1127 qcom,ddr-config = <0x80040868>;
1130 sdhc2_opp_table: opp-table {
1131 compatible = "operating-points-v2";
1133 opp-100000000 {
1134 opp-hz = /bits/ 64 <100000000>;
1135 required-opps = <&rpmpd_opp_low_svs>;
1136 opp-peak-kBps = <250000 133320>;
1137 opp-avg-kBps = <261438 150000>;
1140 opp-202000000 {
1141 opp-hz = /bits/ 64 <202000000>;
1142 required-opps = <&rpmpd_opp_nom>;
1143 opp-peak-kBps = <800000 300000>;
1144 opp-avg-kBps = <261438 300000>;
1150 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1152 reg-names = "std", "ice";
1155 phy-names = "ufsphy";
1156 lanes-per-direction = <1>;
1157 #reset-cells = <1>;
1159 reset-names = "rst";
1161 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1172 clock-names = "core_clk",
1181 freq-table-hz = <50000000 200000000>,
1194 compatible = "qcom,sm6115-qmp-ufs-phy";
1198 clock-names = "ref", "ref_aux";
1201 reset-names = "ufsphy";
1203 #phy-cells = <0>;
1208 gpi_dma0: dma-controller@4a00000 {
1209 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1221 dma-channels = <10>;
1222 dma-channel-mask = <0xf>;
1224 #dma-cells = <3>;
1229 compatible = "qcom,geni-se-qup";
1231 clock-names = "m-ahb", "s-ahb";
1234 #address-cells = <2>;
1235 #size-cells = <2>;
1241 compatible = "qcom,geni-i2c";
1243 clock-names = "se";
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&qup_i2c0_default>;
1250 dma-names = "tx", "rx";
1257 interconnect-names = "qup-core",
1258 "qup-config",
1259 "qup-memory";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1266 compatible = "qcom,geni-spi";
1268 clock-names = "se";
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&qup_spi0_default>;
1275 dma-names = "tx", "rx";
1282 interconnect-names = "qup-core",
1283 "qup-config",
1284 "qup-memory";
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 compatible = "qcom,geni-i2c";
1293 clock-names = "se";
1295 pinctrl-names = "default";
1296 pinctrl-0 = <&qup_i2c1_default>;
1300 dma-names = "tx", "rx";
1307 interconnect-names = "qup-core",
1308 "qup-config",
1309 "qup-memory";
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1316 compatible = "qcom,geni-spi";
1318 clock-names = "se";
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&qup_spi1_default>;
1325 dma-names = "tx", "rx";
1332 interconnect-names = "qup-core",
1333 "qup-config",
1334 "qup-memory";
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1341 compatible = "qcom,geni-i2c";
1343 clock-names = "se";
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c2_default>;
1350 dma-names = "tx", "rx";
1357 interconnect-names = "qup-core",
1358 "qup-config",
1359 "qup-memory";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "qcom,geni-spi";
1368 clock-names = "se";
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_spi2_default>;
1375 dma-names = "tx", "rx";
1382 interconnect-names = "qup-core",
1383 "qup-config",
1384 "qup-memory";
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1391 compatible = "qcom,geni-i2c";
1393 clock-names = "se";
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&qup_i2c3_default>;
1400 dma-names = "tx", "rx";
1407 interconnect-names = "qup-core",
1408 "qup-config",
1409 "qup-memory";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1416 compatible = "qcom,geni-spi";
1418 clock-names = "se";
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&qup_spi3_default>;
1425 dma-names = "tx", "rx";
1432 interconnect-names = "qup-core",
1433 "qup-config",
1434 "qup-memory";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1441 compatible = "qcom,geni-uart";
1443 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1445 clock-names = "se";
1446 power-domains = <&rpmpd SM6115_VDDCX>;
1447 operating-points-v2 = <&qup_opp_table>;
1452 interconnect-names = "qup-core",
1453 "qup-config";
1458 compatible = "qcom,geni-i2c";
1460 clock-names = "se";
1462 pinctrl-names = "default";
1463 pinctrl-0 = <&qup_i2c4_default>;
1467 dma-names = "tx", "rx";
1474 interconnect-names = "qup-core",
1475 "qup-config",
1476 "qup-memory";
1477 #address-cells = <1>;
1478 #size-cells = <0>;
1483 compatible = "qcom,geni-spi";
1485 clock-names = "se";
1487 pinctrl-names = "default";
1488 pinctrl-0 = <&qup_spi4_default>;
1492 dma-names = "tx", "rx";
1499 interconnect-names = "qup-core",
1500 "qup-config",
1501 "qup-memory";
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1508 compatible = "qcom,geni-debug-uart";
1510 clock-names = "se";
1517 interconnect-names = "qup-core",
1518 "qup-config";
1523 compatible = "qcom,geni-i2c";
1525 clock-names = "se";
1527 pinctrl-names = "default";
1528 pinctrl-0 = <&qup_i2c5_default>;
1532 dma-names = "tx", "rx";
1539 interconnect-names = "qup-core",
1540 "qup-config",
1541 "qup-memory";
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1548 compatible = "qcom,geni-spi";
1550 clock-names = "se";
1552 pinctrl-names = "default";
1553 pinctrl-0 = <&qup_spi5_default>;
1557 dma-names = "tx", "rx";
1564 interconnect-names = "qup-core",
1565 "qup-config",
1566 "qup-memory";
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1574 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1576 #address-cells = <2>;
1577 #size-cells = <2>;
1586 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1588 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1590 assigned-clock-rates = <19200000>, <66666667>;
1594 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1597 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1598 /* TODO: USB<->IPA path */
1603 interconnect-names = "usb-ddr",
1604 "apps-usb";
1606 qcom,select-utmi-as-pipe-clk;
1614 phy-names = "usb2-phy", "usb3-phy";
1618 snps,has-lpm-erratum;
1619 snps,hird-threshold = /bits/ 8 <0x10>;
1625 compatible = "qcom,adreno-610.0", "qcom,adreno";
1627 reg-names = "kgsl_3d0_reg_memory";
1636 clock-names = "core",
1646 operating-points-v2 = <&gpu_opp_table>;
1647 power-domains = <&rpmpd SM6115_VDDCX>;
1650 nvmem-cells = <&gpu_speed_bin>;
1651 nvmem-cell-names = "speed_bin";
1655 zap-shader {
1656 memory-region = <&pil_gpu_mem>;
1659 gpu_opp_table: opp-table {
1660 compatible = "operating-points-v2";
1662 opp-320000000 {
1663 opp-hz = /bits/ 64 <320000000>;
1664 required-opps = <&rpmpd_opp_low_svs>;
1665 opp-supported-hw = <0x1f>;
1668 opp-465000000 {
1669 opp-hz = /bits/ 64 <465000000>;
1670 required-opps = <&rpmpd_opp_svs>;
1671 opp-supported-hw = <0x1f>;
1674 opp-600000000 {
1675 opp-hz = /bits/ 64 <600000000>;
1676 required-opps = <&rpmpd_opp_svs_plus>;
1677 opp-supported-hw = <0x1f>;
1680 opp-745000000 {
1681 opp-hz = /bits/ 64 <745000000>;
1682 required-opps = <&rpmpd_opp_nom>;
1683 opp-supported-hw = <0xf>;
1686 opp-820000000 {
1687 opp-hz = /bits/ 64 <820000000>;
1688 required-opps = <&rpmpd_opp_nom_plus>;
1689 opp-supported-hw = <0x7>;
1692 opp-900000000 {
1693 opp-hz = /bits/ 64 <900000000>;
1694 required-opps = <&rpmpd_opp_turbo>;
1695 opp-supported-hw = <0x7>;
1699 opp-950000000 {
1700 opp-hz = /bits/ 64 <950000000>;
1701 required-opps = <&rpmpd_opp_turbo_plus>;
1702 opp-supported-hw = <0x4>;
1705 opp-980000000 {
1706 opp-hz = /bits/ 64 <980000000>;
1707 required-opps = <&rpmpd_opp_turbo_plus>;
1708 opp-supported-hw = <0x3>;
1714 compatible = "qcom,adreno-gmu-wrapper";
1716 reg-names = "gmu";
1717 power-domains = <&gpucc GPU_CX_GDSC>,
1719 power-domain-names = "cx", "gx";
1722 gpucc: clock-controller@5990000 {
1723 compatible = "qcom,sm6115-gpucc";
1728 #clock-cells = <1>;
1729 #reset-cells = <1>;
1730 #power-domain-cells = <1>;
1734 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1735 "qcom,smmu-500", "arm,mmu-500";
1750 clock-names = "mem",
1753 power-domains = <&gpucc GPU_CX_GDSC>;
1755 #global-interrupts = <1>;
1756 #iommu-cells = <2>;
1759 mdss: display-subsystem@5e00000 {
1760 compatible = "qcom,sm6115-mdss";
1762 reg-names = "mdss";
1764 power-domains = <&dispcc MDSS_GDSC>;
1771 interrupt-controller;
1772 #interrupt-cells = <1>;
1781 interconnect-names = "mdp0-mem",
1782 "cpu-cfg";
1784 #address-cells = <2>;
1785 #size-cells = <2>;
1790 mdp: display-controller@5e01000 {
1791 compatible = "qcom,sm6115-dpu";
1794 reg-names = "mdp", "vbif";
1802 clock-names = "bus",
1809 operating-points-v2 = <&mdp_opp_table>;
1810 power-domains = <&rpmpd SM6115_VDDCX>;
1812 interrupt-parent = <&mdss>;
1816 #address-cells = <1>;
1817 #size-cells = <0>;
1822 remote-endpoint = <&mdss_dsi0_in>;
1827 mdp_opp_table: opp-table {
1828 compatible = "operating-points-v2";
1830 opp-19200000 {
1831 opp-hz = /bits/ 64 <19200000>;
1832 required-opps = <&rpmpd_opp_min_svs>;
1835 opp-192000000 {
1836 opp-hz = /bits/ 64 <192000000>;
1837 required-opps = <&rpmpd_opp_low_svs>;
1840 opp-256000000 {
1841 opp-hz = /bits/ 64 <256000000>;
1842 required-opps = <&rpmpd_opp_svs>;
1845 opp-307200000 {
1846 opp-hz = /bits/ 64 <307200000>;
1847 required-opps = <&rpmpd_opp_svs_plus>;
1850 opp-384000000 {
1851 opp-hz = /bits/ 64 <384000000>;
1852 required-opps = <&rpmpd_opp_nom>;
1858 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1860 reg-names = "dsi_ctrl";
1862 interrupt-parent = <&mdss>;
1871 clock-names = "byte",
1878 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1880 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1882 operating-points-v2 = <&dsi_opp_table>;
1883 power-domains = <&rpmpd SM6115_VDDCX>;
1886 #address-cells = <1>;
1887 #size-cells = <0>;
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1898 remote-endpoint = <&dpu_intf1_out>;
1909 dsi_opp_table: opp-table {
1910 compatible = "operating-points-v2";
1912 opp-19200000 {
1913 opp-hz = /bits/ 64 <19200000>;
1914 required-opps = <&rpmpd_opp_min_svs>;
1917 opp-164000000 {
1918 opp-hz = /bits/ 64 <164000000>;
1919 required-opps = <&rpmpd_opp_low_svs>;
1922 opp-187500000 {
1923 opp-hz = /bits/ 64 <187500000>;
1924 required-opps = <&rpmpd_opp_svs>;
1930 compatible = "qcom,dsi-phy-14nm-2290";
1934 reg-names = "dsi_phy",
1938 #clock-cells = <1>;
1939 #phy-cells = <0>;
1943 clock-names = "iface", "ref";
1949 dispcc: clock-controller@5f00000 {
1950 compatible = "qcom,sm6115-dispcc";
1957 #clock-cells = <1>;
1958 #reset-cells = <1>;
1959 #power-domain-cells = <1>;
1963 compatible = "qcom,sm6115-mpss-pas";
1966 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1972 interrupt-names = "wdog", "fatal", "ready", "handover",
1973 "stop-ack", "shutdown-ack";
1976 clock-names = "xo";
1978 power-domains = <&rpmpd SM6115_VDDCX>;
1980 memory-region = <&pil_modem_mem>;
1982 qcom,smem-states = <&modem_smp2p_out 0>;
1983 qcom,smem-state-names = "stop";
1987 glink-edge {
1990 qcom,remote-pid = <1>;
1996 compatible = "arm,coresight-stm", "arm,primecell";
1999 reg-names = "stm-base", "stm-stimulus-base";
2002 clock-names = "apb_pclk";
2006 out-ports {
2009 remote-endpoint = <&funnel_in0_in>;
2016 compatible = "arm,coresight-cti", "arm,primecell";
2020 clock-names = "apb_pclk";
2026 compatible = "arm,coresight-cti", "arm,primecell";
2030 clock-names = "apb_pclk";
2036 compatible = "arm,coresight-cti", "arm,primecell";
2040 clock-names = "apb_pclk";
2046 compatible = "arm,coresight-cti", "arm,primecell";
2050 clock-names = "apb_pclk";
2056 compatible = "arm,coresight-cti", "arm,primecell";
2060 clock-names = "apb_pclk";
2066 compatible = "arm,coresight-cti", "arm,primecell";
2070 clock-names = "apb_pclk";
2076 compatible = "arm,coresight-cti", "arm,primecell";
2080 clock-names = "apb_pclk";
2086 compatible = "arm,coresight-cti", "arm,primecell";
2090 clock-names = "apb_pclk";
2096 compatible = "arm,coresight-cti", "arm,primecell";
2100 clock-names = "apb_pclk";
2106 compatible = "arm,coresight-cti", "arm,primecell";
2110 clock-names = "apb_pclk";
2116 compatible = "arm,coresight-cti", "arm,primecell";
2120 clock-names = "apb_pclk";
2126 compatible = "arm,coresight-cti", "arm,primecell";
2130 clock-names = "apb_pclk";
2136 compatible = "arm,coresight-cti", "arm,primecell";
2140 clock-names = "apb_pclk";
2146 compatible = "arm,coresight-cti", "arm,primecell";
2150 clock-names = "apb_pclk";
2156 compatible = "arm,coresight-cti", "arm,primecell";
2160 clock-names = "apb_pclk";
2166 compatible = "arm,coresight-cti", "arm,primecell";
2170 clock-names = "apb_pclk";
2176 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2180 clock-names = "apb_pclk";
2184 out-ports {
2187 remote-endpoint = <&etr_in>;
2192 in-ports {
2195 remote-endpoint = <&etf_out>;
2202 compatible = "arm,coresight-tmc", "arm,primecell";
2206 clock-names = "apb_pclk";
2210 in-ports {
2213 remote-endpoint = <&merge_funnel_out>;
2218 out-ports {
2221 remote-endpoint = <&replicator_in>;
2228 compatible = "arm,coresight-tmc", "arm,primecell";
2232 clock-names = "apb_pclk";
2236 in-ports {
2239 remote-endpoint = <&replicator_out>;
2246 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2250 clock-names = "apb_pclk";
2254 out-ports {
2257 remote-endpoint = <&merge_funnel_in0>;
2262 in-ports {
2265 remote-endpoint = <&stm_out>;
2272 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2276 clock-names = "apb_pclk";
2280 out-ports {
2283 remote-endpoint = <&merge_funnel_in1>;
2288 in-ports {
2291 remote-endpoint = <&funnel_apss1_out>;
2298 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2302 clock-names = "apb_pclk";
2306 out-ports {
2309 remote-endpoint = <&etf_in>;
2314 in-ports {
2315 #address-cells = <1>;
2316 #size-cells = <0>;
2321 remote-endpoint = <&funnel_in0_out>;
2328 remote-endpoint = <&funnel_in1_out>;
2335 compatible = "arm,coresight-etm4x", "arm,primecell";
2339 clock-names = "apb_pclk";
2340 arm,coresight-loses-context-with-cpu;
2346 out-ports {
2349 remote-endpoint = <&funnel_apss0_in0>;
2356 compatible = "arm,coresight-etm4x", "arm,primecell";
2360 clock-names = "apb_pclk";
2361 arm,coresight-loses-context-with-cpu;
2367 out-ports {
2370 remote-endpoint = <&funnel_apss0_in1>;
2377 compatible = "arm,coresight-etm4x", "arm,primecell";
2381 clock-names = "apb_pclk";
2382 arm,coresight-loses-context-with-cpu;
2388 out-ports {
2391 remote-endpoint = <&funnel_apss0_in2>;
2398 compatible = "arm,coresight-etm4x", "arm,primecell";
2402 clock-names = "apb_pclk";
2403 arm,coresight-loses-context-with-cpu;
2409 out-ports {
2412 remote-endpoint = <&funnel_apss0_in3>;
2419 compatible = "arm,coresight-etm4x", "arm,primecell";
2423 clock-names = "apb_pclk";
2424 arm,coresight-loses-context-with-cpu;
2430 out-ports {
2433 remote-endpoint = <&funnel_apss0_in4>;
2440 compatible = "arm,coresight-etm4x", "arm,primecell";
2444 clock-names = "apb_pclk";
2445 arm,coresight-loses-context-with-cpu;
2451 out-ports {
2454 remote-endpoint = <&funnel_apss0_in5>;
2461 compatible = "arm,coresight-etm4x", "arm,primecell";
2465 clock-names = "apb_pclk";
2466 arm,coresight-loses-context-with-cpu;
2472 out-ports {
2475 remote-endpoint = <&funnel_apss0_in6>;
2482 compatible = "arm,coresight-etm4x", "arm,primecell";
2486 clock-names = "apb_pclk";
2487 arm,coresight-loses-context-with-cpu;
2493 out-ports {
2496 remote-endpoint = <&funnel_apss0_in7>;
2503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2507 clock-names = "apb_pclk";
2511 out-ports {
2514 remote-endpoint = <&funnel_apss1_in>;
2519 in-ports {
2520 #address-cells = <1>;
2521 #size-cells = <0>;
2526 remote-endpoint = <&etm0_out>;
2533 remote-endpoint = <&etm1_out>;
2540 remote-endpoint = <&etm2_out>;
2547 remote-endpoint = <&etm3_out>;
2554 remote-endpoint = <&etm4_out>;
2561 remote-endpoint = <&etm5_out>;
2568 remote-endpoint = <&etm6_out>;
2575 remote-endpoint = <&etm7_out>;
2582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2586 clock-names = "apb_pclk";
2590 out-ports {
2593 remote-endpoint = <&funnel_in1_in>;
2598 in-ports {
2601 remote-endpoint = <&funnel_apss0_out>;
2608 compatible = "qcom,sm6115-adsp-pas";
2611 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2616 interrupt-names = "wdog", "fatal", "ready",
2617 "handover", "stop-ack";
2620 clock-names = "xo";
2622 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2625 memory-region = <&pil_adsp_mem>;
2627 qcom,smem-states = <&adsp_smp2p_out 0>;
2628 qcom,smem-state-names = "stop";
2632 glink-edge {
2635 qcom,remote-pid = <2>;
2640 qcom,glink-channels = "fastrpcglink-apps-dsp";
2642 qcom,non-secure-domain;
2643 #address-cells = <1>;
2644 #size-cells = <0>;
2646 compute-cb@3 {
2647 compatible = "qcom,fastrpc-compute-cb";
2652 compute-cb@4 {
2653 compatible = "qcom,fastrpc-compute-cb";
2658 compute-cb@5 {
2659 compatible = "qcom,fastrpc-compute-cb";
2664 compute-cb@6 {
2665 compatible = "qcom,fastrpc-compute-cb";
2670 compute-cb@7 {
2671 compatible = "qcom,fastrpc-compute-cb";
2680 compatible = "qcom,sm6115-cdsp-pas";
2683 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2688 interrupt-names = "wdog", "fatal", "ready",
2689 "handover", "stop-ack";
2692 clock-names = "xo";
2694 power-domains = <&rpmpd SM6115_VDDCX>;
2696 memory-region = <&pil_cdsp_mem>;
2698 qcom,smem-states = <&cdsp_smp2p_out 0>;
2699 qcom,smem-state-names = "stop";
2703 glink-edge {
2706 qcom,remote-pid = <5>;
2711 qcom,glink-channels = "fastrpcglink-apps-dsp";
2713 qcom,non-secure-domain;
2714 #address-cells = <1>;
2715 #size-cells = <0>;
2717 compute-cb@1 {
2718 compatible = "qcom,fastrpc-compute-cb";
2723 compute-cb@2 {
2724 compatible = "qcom,fastrpc-compute-cb";
2729 compute-cb@3 {
2730 compatible = "qcom,fastrpc-compute-cb";
2735 compute-cb@4 {
2736 compatible = "qcom,fastrpc-compute-cb";
2741 compute-cb@5 {
2742 compatible = "qcom,fastrpc-compute-cb";
2747 compute-cb@6 {
2748 compatible = "qcom,fastrpc-compute-cb";
2759 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2761 #iommu-cells = <2>;
2762 #global-interrupts = <1>;
2832 compatible = "qcom,wcn3990-wifi";
2834 reg-names = "membase";
2835 memory-region = <&wlan_msa_mem>;
2849 qcom,msa-fixed-perm;
2854 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2861 compatible = "qcom,sm6115-apcs-hmss-global",
2862 "qcom,msm8994-apcs-kpss-global";
2865 #mbox-cells = <1>;
2869 compatible = "arm,armv7-timer-mem";
2871 #address-cells = <2>;
2872 #size-cells = <1>;
2874 clock-frequency = <19200000>;
2878 frame-number = <0>;
2885 frame-number = <1>;
2892 frame-number = <2>;
2899 frame-number = <3>;
2906 frame-number = <4>;
2913 frame-number = <5>;
2920 frame-number = <6>;
2926 intc: interrupt-controller@f200000 {
2927 compatible = "arm,gic-v3";
2930 #interrupt-cells = <3>;
2931 interrupt-controller;
2932 interrupt-parent = <&intc>;
2933 #redistributor-regions = <1>;
2934 redistributor-stride = <0x0 0x20000>;
2939 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2943 reg-names = "freq-domain0", "freq-domain1";
2945 clock-names = "xo", "alternate";
2947 #freq-domain-cells = <1>;
2948 #clock-cells = <1>;
2952 thermal-zones {
2953 mapss-thermal {
2954 polling-delay-passive = <0>;
2955 polling-delay = <0>;
2956 thermal-sensors = <&tsens0 0>;
2959 trip-point0 {
2965 trip-point1 {
2973 cdsp-hvx-thermal {
2974 polling-delay-passive = <0>;
2975 polling-delay = <0>;
2976 thermal-sensors = <&tsens0 1>;
2979 trip-point0 {
2985 trip-point1 {
2993 wlan-thermal {
2994 polling-delay-passive = <0>;
2995 polling-delay = <0>;
2996 thermal-sensors = <&tsens0 2>;
2999 trip-point0 {
3005 trip-point1 {
3013 camera-thermal {
3014 polling-delay-passive = <0>;
3015 polling-delay = <0>;
3016 thermal-sensors = <&tsens0 3>;
3019 trip-point0 {
3025 trip-point1 {
3033 video-thermal {
3034 polling-delay-passive = <0>;
3035 polling-delay = <0>;
3036 thermal-sensors = <&tsens0 4>;
3039 trip-point0 {
3045 trip-point1 {
3053 modem1-thermal {
3054 polling-delay-passive = <0>;
3055 polling-delay = <0>;
3056 thermal-sensors = <&tsens0 5>;
3059 trip-point0 {
3065 trip-point1 {
3073 cpu4-thermal {
3074 polling-delay-passive = <0>;
3075 polling-delay = <0>;
3076 thermal-sensors = <&tsens0 6>;
3079 cpu4_alert0: trip-point0 {
3085 cpu4_alert1: trip-point1 {
3099 cpu5-thermal {
3100 polling-delay-passive = <0>;
3101 polling-delay = <0>;
3102 thermal-sensors = <&tsens0 7>;
3105 cpu5_alert0: trip-point0 {
3111 cpu5_alert1: trip-point1 {
3125 cpu6-thermal {
3126 polling-delay-passive = <0>;
3127 polling-delay = <0>;
3128 thermal-sensors = <&tsens0 8>;
3131 cpu6_alert0: trip-point0 {
3137 cpu6_alert1: trip-point1 {
3151 cpu7-thermal {
3152 polling-delay-passive = <0>;
3153 polling-delay = <0>;
3154 thermal-sensors = <&tsens0 9>;
3157 cpu7_alert0: trip-point0 {
3163 cpu7_alert1: trip-point1 {
3177 cpu45-thermal {
3178 polling-delay-passive = <0>;
3179 polling-delay = <0>;
3180 thermal-sensors = <&tsens0 10>;
3183 cpu45_alert0: trip-point0 {
3189 cpu45_alert1: trip-point1 {
3203 cpu67-thermal {
3204 polling-delay-passive = <0>;
3205 polling-delay = <0>;
3206 thermal-sensors = <&tsens0 11>;
3209 cpu67_alert0: trip-point0 {
3215 cpu67_alert1: trip-point1 {
3229 cpu0123-thermal {
3230 polling-delay-passive = <0>;
3231 polling-delay = <0>;
3232 thermal-sensors = <&tsens0 12>;
3235 cpu0123_alert0: trip-point0 {
3241 cpu0123_alert1: trip-point1 {
3255 modem0-thermal {
3256 polling-delay-passive = <0>;
3257 polling-delay = <0>;
3258 thermal-sensors = <&tsens0 13>;
3261 trip-point0 {
3267 trip-point1 {
3275 display-thermal {
3276 polling-delay-passive = <0>;
3277 polling-delay = <0>;
3278 thermal-sensors = <&tsens0 14>;
3281 trip-point0 {
3287 trip-point1 {
3295 gpu-thermal {
3296 polling-delay-passive = <0>;
3297 polling-delay = <0>;
3298 thermal-sensors = <&tsens0 15>;
3301 trip-point0 {
3307 trip-point1 {
3317 compatible = "arm,armv8-timer";