Lines Matching +full:0 +full:x01c40000
29 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #size-cells = <0>;
42 CPU0: cpu@0 {
45 reg = <0x0 0x0>;
46 clocks = <&cpufreq_hw 0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x1>;
65 clocks = <&cpufreq_hw 0>;
70 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x2>;
79 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
92 reg = <0x0 0x3>;
93 clocks = <&cpufreq_hw 0>;
98 qcom,freq-domain = <&cpufreq_hw 0>;
106 reg = <0x0 0x100>;
125 reg = <0x0 0x101>;
139 reg = <0x0 0x102>;
153 reg = <0x0 0x103>;
205 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
208 arm,psci-suspend-param = <0x40000003>;
215 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
218 arm,psci-suspend-param = <0x40000003>;
227 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
230 arm,psci-suspend-param = <0x40000022>;
236 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
239 arm,psci-suspend-param = <0x41000044>;
245 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
248 arm,psci-suspend-param = <0x40000042>;
257 arm,psci-suspend-param = <0x41000044>;
277 reg = <0 0x80000000 0 0>;
309 #power-domain-cells = <0>;
315 #power-domain-cells = <0>;
321 #power-domain-cells = <0>;
327 #power-domain-cells = <0>;
333 #power-domain-cells = <0>;
339 #power-domain-cells = <0>;
345 #power-domain-cells = <0>;
351 #power-domain-cells = <0>;
357 #power-domain-cells = <0>;
362 #power-domain-cells = <0>;
375 mboxes = <&apcs_glb 0>;
439 reg = <0x0 0x45700000 0x0 0x600000>;
444 reg = <0x0 0x45e00000 0x0 0x140000>;
449 reg = <0x0 0x45fff000 0x0 0x1000>;
455 reg = <0x0 0x46000000 0x0 0x200000>;
463 reg = <0x0 0x46200000 0x0 0x1e00000>;
468 reg = <0x0 0x4ab00000 0x0 0x6900000>;
473 reg = <0x0 0x51400000 0x0 0x500000>;
478 reg = <0x0 0x51900000 0x0 0x100000>;
483 reg = <0x0 0x51a00000 0x0 0x1e00000>;
488 reg = <0x0 0x53800000 0x0 0x2800000>;
493 reg = <0x0 0x56100000 0x0 0x10000>;
498 reg = <0x0 0x56110000 0x0 0x5000>;
503 reg = <0x0 0x56115000 0x0 0x2000>;
508 reg = <0x0 0x5c000000 0x0 0x00f00000>;
513 reg = <0x0 0x5cf00000 0x0 0x0100000>;
518 reg = <0x0 0x60000000 0x0 0x3900000>;
524 reg = <0x0 0x89b01000 0x0 0x200000>;
540 qcom,local-pid = <0>;
564 qcom,local-pid = <0>;
588 qcom,local-pid = <0>;
604 soc: soc@0 {
608 ranges = <0 0 0 0 0x10 0>;
609 dma-ranges = <0 0 0 0 0x10 0>;
613 reg = <0x0 0x00340000 0x0 0x20000>;
619 reg = <0x0 0x00500000 0x0 0x400000>,
620 <0x0 0x00900000 0x0 0x400000>,
621 <0x0 0x00d00000 0x0 0x400000>;
625 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
807 reg = <0x0 0x01400000 0x0 0x1f0000>;
817 reg = <0x0 0x01613000 0x0 0x180>;
818 #phy-cells = <0>;
831 reg = <0x0 0x01b04000 0x0 0x24000>;
836 qcom,ee = <0>;
838 iommus = <&apps_smmu 0x92 0>,
839 <&apps_smmu 0x94 0x11>,
840 <&apps_smmu 0x96 0x11>,
841 <&apps_smmu 0x98 0x1>,
842 <&apps_smmu 0x9F 0>;
847 reg = <0x0 0x01b3a000 0x0 0x6000>;
853 iommus = <&apps_smmu 0x92 0>,
854 <&apps_smmu 0x94 0x11>,
855 <&apps_smmu 0x96 0x11>,
856 <&apps_smmu 0x98 0x1>,
857 <&apps_smmu 0x9F 0>;
862 reg = <0x0 0x01615000 0x0 0x1000>;
877 #clock-cells = <0>;
880 #phy-cells = <0>;
887 reg = <0x0 0x01880000 0x0 0x5f080>;
916 reg = <0x0 0x01900000 0x0 0x6200>;
924 reg = <0x0 0x01b40000 0x0 0x7000>;
929 reg = <0x25b 0x1>;
934 reg = <0x6006 0x2>;
941 reg = <0x0 0x01b53000 0x0 0x1000>;
948 reg = <0x0 0x01b8e300 0x0 0x600>;
958 opp-0 {
1002 reg = <0x0 0x01c40000 0x0 0x1100>,
1003 <0x0 0x01e00000 0x0 0x2000000>,
1004 <0x0 0x03e00000 0x0 0x100000>,
1005 <0x0 0x03f00000 0x0 0xa0000>,
1006 <0x0 0x01c0a000 0x0 0x26000>;
1010 qcom,ee = <0>;
1011 qcom,channel = <0>;
1013 #size-cells = <0>;
1020 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1021 <0x0 0x04410000 0x0 0x8>; /* SROT */
1031 reg = <0x0 0x04480000 0x0 0x80000>;
1037 reg = <0x0 0x045f0000 0x0 0x7000>;
1042 reg = <0x0 0x04690000 0x0 0x10000>;
1047 reg = <0x0 0x04744000 0x0 0x1000>,
1048 <0x0 0x04745000 0x0 0x1000>,
1049 <0x0 0x04748000 0x0 0x8000>;
1102 reg = <0x0 0x04784000 0x0 0x1000>;
1116 iommus = <&apps_smmu 0x00a0 0x0>;
1126 qcom,dll-config = <0x0007642c>;
1127 qcom,ddr-config = <0x80040868>;
1151 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1162 iommus = <&apps_smmu 0x100 0>;
1182 <0 0>,
1183 <0 0>,
1185 <0 0>,
1186 <0 0>,
1187 <0 0>,
1195 reg = <0x0 0x04807000 0x0 0x1000>;
1200 resets = <&ufs_mem_hc 0>;
1203 #phy-cells = <0>;
1210 reg = <0x0 0x04a00000 0x0 0x60000>;
1222 dma-channel-mask = <0xf>;
1223 iommus = <&apps_smmu 0xf6 0x0>;
1230 reg = <0x0 0x04ac0000 0x0 0x2000>;
1236 iommus = <&apps_smmu 0xe3 0x0>;
1242 reg = <0x0 0x04a80000 0x0 0x4000>;
1246 pinctrl-0 = <&qup_i2c0_default>;
1248 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1249 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1261 #size-cells = <0>;
1267 reg = <0x0 0x04a80000 0x0 0x4000>;
1271 pinctrl-0 = <&qup_spi0_default>;
1273 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1274 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1286 #size-cells = <0>;
1292 reg = <0x0 0x04a84000 0x0 0x4000>;
1296 pinctrl-0 = <&qup_i2c1_default>;
1298 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1311 #size-cells = <0>;
1317 reg = <0x0 0x04a84000 0x0 0x4000>;
1321 pinctrl-0 = <&qup_spi1_default>;
1323 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1336 #size-cells = <0>;
1342 reg = <0x0 0x04a88000 0x0 0x4000>;
1346 pinctrl-0 = <&qup_i2c2_default>;
1348 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1361 #size-cells = <0>;
1367 reg = <0x0 0x04a88000 0x0 0x4000>;
1371 pinctrl-0 = <&qup_spi2_default>;
1373 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1386 #size-cells = <0>;
1392 reg = <0x0 0x04a8c000 0x0 0x4000>;
1396 pinctrl-0 = <&qup_i2c3_default>;
1398 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1411 #size-cells = <0>;
1417 reg = <0x0 0x04a8c000 0x0 0x4000>;
1421 pinctrl-0 = <&qup_spi3_default>;
1423 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1436 #size-cells = <0>;
1442 reg = <0x0 0x04a8c000 0x0 0x4000>;
1459 reg = <0x0 0x04a90000 0x0 0x4000>;
1463 pinctrl-0 = <&qup_i2c4_default>;
1465 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1478 #size-cells = <0>;
1484 reg = <0x0 0x04a90000 0x0 0x4000>;
1488 pinctrl-0 = <&qup_spi4_default>;
1490 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1503 #size-cells = <0>;
1509 reg = <0x0 0x04a90000 0x0 0x4000>;
1524 reg = <0x0 0x04a94000 0x0 0x4000>;
1528 pinctrl-0 = <&qup_i2c5_default>;
1530 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1543 #size-cells = <0>;
1549 reg = <0x0 0x04a94000 0x0 0x4000>;
1553 pinctrl-0 = <&qup_spi5_default>;
1555 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1568 #size-cells = <0>;
1575 reg = <0x0 0x04ef8800 0x0 0x400>;
1611 reg = <0x0 0x04e00000 0x0 0xcd00>;
1615 iommus = <&apps_smmu 0x120 0x0>;
1619 snps,hird-threshold = /bits/ 8 <0x10>;
1626 reg = <0x0 0x05900000 0x0 0x40000>;
1645 iommus = <&adreno_smmu 0 1>;
1665 opp-supported-hw = <0x1f>;
1671 opp-supported-hw = <0x1f>;
1677 opp-supported-hw = <0x1f>;
1683 opp-supported-hw = <0xf>;
1689 opp-supported-hw = <0x7>;
1695 opp-supported-hw = <0x7>;
1702 opp-supported-hw = <0x4>;
1708 opp-supported-hw = <0x3>;
1715 reg = <0x0 0x0596a000 0x0 0x30000>;
1724 reg = <0x0 0x05990000 0x0 0x9000>;
1736 reg = <0x0 0x059a0000 0x0 0x10000>;
1761 reg = <0x0 0x05e00000 0x0 0x1000>;
1774 iommus = <&apps_smmu 0x420 0x2>,
1775 <&apps_smmu 0x421 0x0>;
1792 reg = <0x0 0x05e01000 0x0 0x8f000>,
1793 <0x0 0x05eb0000 0x0 0x2008>;
1813 interrupts = <0>;
1817 #size-cells = <0>;
1819 port@0 {
1820 reg = <0>;
1859 reg = <0x0 0x05e94000 0x0 0x400>;
1880 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1887 #size-cells = <0>;
1893 #size-cells = <0>;
1895 port@0 {
1896 reg = <0>;
1931 reg = <0x0 0x05e94400 0x0 0x100>,
1932 <0x0 0x05e94500 0x0 0x300>,
1933 <0x0 0x05e94800 0x0 0x188>;
1939 #phy-cells = <0>;
1951 reg = <0x0 0x05f00000 0 0x20000>;
1954 <&mdss_dsi0_phy 0>,
1964 reg = <0x0 0x06080000 0x0 0x100>;
1967 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1982 qcom,smem-states = <&modem_smp2p_out 0>;
1997 reg = <0x0 0x08002000 0x0 0x1000>,
1998 <0x0 0x0e280000 0x0 0x180000>;
2017 reg = <0x0 0x08010000 0x0 0x1000>;
2027 reg = <0x0 0x08011000 0x0 0x1000>;
2037 reg = <0x0 0x08012000 0x0 0x1000>;
2047 reg = <0x0 0x08013000 0x0 0x1000>;
2057 reg = <0x0 0x08014000 0x0 0x1000>;
2067 reg = <0x0 0x08015000 0x0 0x1000>;
2077 reg = <0x0 0x08016000 0x0 0x1000>;
2087 reg = <0x0 0x08017000 0x0 0x1000>;
2097 reg = <0x0 0x08018000 0x0 0x1000>;
2107 reg = <0x0 0x08019000 0x0 0x1000>;
2117 reg = <0x0 0x0801a000 0x0 0x1000>;
2127 reg = <0x0 0x0801b000 0x0 0x1000>;
2137 reg = <0x0 0x0801c000 0x0 0x1000>;
2147 reg = <0x0 0x0801d000 0x0 0x1000>;
2157 reg = <0x0 0x0801e000 0x0 0x1000>;
2167 reg = <0x0 0x0801f000 0x0 0x1000>;
2177 reg = <0x0 0x08046000 0x0 0x1000>;
2203 reg = <0x0 0x08047000 0x0 0x1000>;
2229 reg = <0x0 0x08048000 0x0 0x1000>;
2247 reg = <0x0 0x08041000 0x0 0x1000>;
2273 reg = <0x0 0x08042000 0x0 0x1000>;
2299 reg = <0x0 0x08045000 0x0 0x1000>;
2316 #size-cells = <0>;
2318 port@0 {
2319 reg = <0>;
2336 reg = <0x0 0x09040000 0x0 0x1000>;
2357 reg = <0x0 0x09140000 0x0 0x1000>;
2378 reg = <0x0 0x09240000 0x0 0x1000>;
2399 reg = <0x0 0x09340000 0x0 0x1000>;
2420 reg = <0x0 0x09440000 0x0 0x1000>;
2441 reg = <0x0 0x09540000 0x0 0x1000>;
2462 reg = <0x0 0x09640000 0x0 0x1000>;
2483 reg = <0x0 0x09740000 0x0 0x1000>;
2504 reg = <0x0 0x09800000 0x0 0x1000>;
2521 #size-cells = <0>;
2523 port@0 {
2524 reg = <0>;
2583 reg = <0x0 0x09810000 0x0 0x1000>;
2609 reg = <0x0 0x0ab00000 0x0 0x100>;
2612 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2627 qcom,smem-states = <&adsp_smp2p_out 0>;
2644 #size-cells = <0>;
2649 iommus = <&apps_smmu 0x01c3 0x0>;
2655 iommus = <&apps_smmu 0x01c4 0x0>;
2661 iommus = <&apps_smmu 0x01c5 0x0>;
2667 iommus = <&apps_smmu 0x01c6 0x0>;
2673 iommus = <&apps_smmu 0x01c7 0x0>;
2681 reg = <0x0 0x0b300000 0x0 0x100000>;
2684 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2698 qcom,smem-states = <&cdsp_smp2p_out 0>;
2715 #size-cells = <0>;
2720 iommus = <&apps_smmu 0x0c01 0x0>;
2726 iommus = <&apps_smmu 0x0c02 0x0>;
2732 iommus = <&apps_smmu 0x0c03 0x0>;
2738 iommus = <&apps_smmu 0x0c04 0x0>;
2744 iommus = <&apps_smmu 0x0c05 0x0>;
2750 iommus = <&apps_smmu 0x0c06 0x0>;
2760 reg = <0x0 0x0c600000 0x0 0x80000>;
2833 reg = <0x0 0x0c800000 0x0 0x800000>;
2848 iommus = <&apps_smmu 0x1a0 0x1>;
2855 reg = <0x0 0x0f017000 0x0 0x1000>;
2863 reg = <0x0 0x0f111000 0x0 0x1000>;
2870 reg = <0x0 0x0f120000 0x0 0x1000>;
2873 ranges = <0x0 0x0 0x0 0x0 0x20000000>;
2877 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
2878 frame-number = <0>;
2884 reg = <0x0 0x0f123000 0x1000>;
2891 reg = <0x0 0x0f124000 0x1000>;
2898 reg = <0x0 0x0f125000 0x1000>;
2905 reg = <0x0 0x0f126000 0x1000>;
2912 reg = <0x0 0x0f127000 0x1000>;
2919 reg = <0x0 0x0f128000 0x1000>;
2928 reg = <0x0 0x0f200000 0x0 0x10000>,
2929 <0x0 0x0f300000 0x0 0x100000>;
2934 redistributor-stride = <0x0 0x20000>;
2940 reg = <0x0 0x0f521000 0x0 0x1000>,
2941 <0x0 0x0f523000 0x0 0x1000>;
2954 polling-delay-passive = <0>;
2955 polling-delay = <0>;
2956 thermal-sensors = <&tsens0 0>;
2974 polling-delay-passive = <0>;
2975 polling-delay = <0>;
2994 polling-delay-passive = <0>;
2995 polling-delay = <0>;
3014 polling-delay-passive = <0>;
3015 polling-delay = <0>;
3034 polling-delay-passive = <0>;
3035 polling-delay = <0>;
3054 polling-delay-passive = <0>;
3055 polling-delay = <0>;
3074 polling-delay-passive = <0>;
3075 polling-delay = <0>;
3100 polling-delay-passive = <0>;
3101 polling-delay = <0>;
3126 polling-delay-passive = <0>;
3127 polling-delay = <0>;
3152 polling-delay-passive = <0>;
3153 polling-delay = <0>;
3178 polling-delay-passive = <0>;
3179 polling-delay = <0>;
3204 polling-delay-passive = <0>;
3205 polling-delay = <0>;
3230 polling-delay-passive = <0>;
3231 polling-delay = <0>;
3256 polling-delay-passive = <0>;
3257 polling-delay = <0>;
3276 polling-delay-passive = <0>;
3277 polling-delay = <0>;
3296 polling-delay-passive = <0>;
3297 polling-delay = <0>;
3321 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;