Lines Matching +full:sdm845 +full:- +full:videocc
1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sdm845.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/phy/phy-qcom-qmp.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
23 #include <dt-bindings/power/qcom-rpmpd.h>
24 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
25 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
26 #include <dt-bindings/soc/qcom,apr.h>
27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
28 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
29 #include <dt-bindings/thermal/thermal.h>
32 interrupt-parent = <&intc>;
34 #address-cells = <2>;
35 #size-cells = <2>;
75 xo_board: xo-board {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <38400000>;
79 clock-output-names = "xo_board";
82 sleep_clk: sleep-clk {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32764>;
90 #address-cells = <2>;
91 #size-cells = <0>;
98 enable-method = "psci";
99 capacity-dmips-mhz = <611>;
100 dynamic-power-coefficient = <154>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 operating-points-v2 = <&cpu0_opp_table>;
105 power-domains = <&CPU_PD0>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
114 L3_0: l3-cache {
116 cache-level = <3>;
117 cache-unified;
127 enable-method = "psci";
128 capacity-dmips-mhz = <611>;
129 dynamic-power-coefficient = <154>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
134 power-domains = <&CPU_PD1>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
137 next-level-cache = <&L2_100>;
138 L2_100: l2-cache {
140 cache-level = <2>;
141 cache-unified;
142 next-level-cache = <&L3_0>;
151 enable-method = "psci";
152 capacity-dmips-mhz = <611>;
153 dynamic-power-coefficient = <154>;
154 qcom,freq-domain = <&cpufreq_hw 0>;
155 operating-points-v2 = <&cpu0_opp_table>;
158 power-domains = <&CPU_PD2>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
161 next-level-cache = <&L2_200>;
162 L2_200: l2-cache {
164 cache-level = <2>;
165 cache-unified;
166 next-level-cache = <&L3_0>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <611>;
177 dynamic-power-coefficient = <154>;
178 qcom,freq-domain = <&cpufreq_hw 0>;
179 operating-points-v2 = <&cpu0_opp_table>;
182 #cooling-cells = <2>;
183 power-domains = <&CPU_PD3>;
184 power-domain-names = "psci";
185 next-level-cache = <&L2_300>;
186 L2_300: l2-cache {
188 cache-level = <2>;
189 cache-unified;
190 next-level-cache = <&L3_0>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 dynamic-power-coefficient = <442>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
206 power-domains = <&CPU_PD4>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_400>;
210 L2_400: l2-cache {
212 cache-level = <2>;
213 cache-unified;
214 next-level-cache = <&L3_0>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 dynamic-power-coefficient = <442>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
230 power-domains = <&CPU_PD5>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 next-level-cache = <&L2_500>;
234 L2_500: l2-cache {
236 cache-level = <2>;
237 cache-unified;
238 next-level-cache = <&L3_0>;
247 enable-method = "psci";
248 capacity-dmips-mhz = <1024>;
249 dynamic-power-coefficient = <442>;
250 qcom,freq-domain = <&cpufreq_hw 1>;
251 operating-points-v2 = <&cpu4_opp_table>;
254 power-domains = <&CPU_PD6>;
255 power-domain-names = "psci";
256 #cooling-cells = <2>;
257 next-level-cache = <&L2_600>;
258 L2_600: l2-cache {
260 cache-level = <2>;
261 cache-unified;
262 next-level-cache = <&L3_0>;
271 enable-method = "psci";
272 capacity-dmips-mhz = <1024>;
273 dynamic-power-coefficient = <442>;
274 qcom,freq-domain = <&cpufreq_hw 1>;
275 operating-points-v2 = <&cpu4_opp_table>;
278 power-domains = <&CPU_PD7>;
279 power-domain-names = "psci";
280 #cooling-cells = <2>;
281 next-level-cache = <&L2_700>;
282 L2_700: l2-cache {
284 cache-level = <2>;
285 cache-unified;
286 next-level-cache = <&L3_0>;
290 cpu-map {
326 cpu_idle_states: idle-states {
327 entry-method = "psci";
329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
330 compatible = "arm,idle-state";
331 idle-state-name = "little-rail-power-collapse";
332 arm,psci-suspend-param = <0x40000004>;
333 entry-latency-us = <350>;
334 exit-latency-us = <461>;
335 min-residency-us = <1890>;
336 local-timer-stop;
339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
340 compatible = "arm,idle-state";
341 idle-state-name = "big-rail-power-collapse";
342 arm,psci-suspend-param = <0x40000004>;
343 entry-latency-us = <264>;
344 exit-latency-us = <621>;
345 min-residency-us = <952>;
346 local-timer-stop;
350 domain-idle-states {
351 CLUSTER_SLEEP_0: cluster-sleep-0 {
352 compatible = "domain-idle-state";
353 arm,psci-suspend-param = <0x4100c244>;
354 entry-latency-us = <3263>;
355 exit-latency-us = <6562>;
356 min-residency-us = <9987>;
363 compatible = "qcom,scm-sdm845", "qcom,scm";
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points-v2";
375 opp-shared;
377 cpu0_opp1: opp-300000000 {
378 opp-hz = /bits/ 64 <300000000>;
379 opp-peak-kBps = <800000 4800000>;
382 cpu0_opp2: opp-403200000 {
383 opp-hz = /bits/ 64 <403200000>;
384 opp-peak-kBps = <800000 4800000>;
387 cpu0_opp3: opp-480000000 {
388 opp-hz = /bits/ 64 <480000000>;
389 opp-peak-kBps = <800000 6451200>;
392 cpu0_opp4: opp-576000000 {
393 opp-hz = /bits/ 64 <576000000>;
394 opp-peak-kBps = <800000 6451200>;
397 cpu0_opp5: opp-652800000 {
398 opp-hz = /bits/ 64 <652800000>;
399 opp-peak-kBps = <800000 7680000>;
402 cpu0_opp6: opp-748800000 {
403 opp-hz = /bits/ 64 <748800000>;
404 opp-peak-kBps = <1804000 9216000>;
407 cpu0_opp7: opp-825600000 {
408 opp-hz = /bits/ 64 <825600000>;
409 opp-peak-kBps = <1804000 9216000>;
412 cpu0_opp8: opp-902400000 {
413 opp-hz = /bits/ 64 <902400000>;
414 opp-peak-kBps = <1804000 10444800>;
417 cpu0_opp9: opp-979200000 {
418 opp-hz = /bits/ 64 <979200000>;
419 opp-peak-kBps = <1804000 11980800>;
422 cpu0_opp10: opp-1056000000 {
423 opp-hz = /bits/ 64 <1056000000>;
424 opp-peak-kBps = <1804000 11980800>;
427 cpu0_opp11: opp-1132800000 {
428 opp-hz = /bits/ 64 <1132800000>;
429 opp-peak-kBps = <2188000 13516800>;
432 cpu0_opp12: opp-1228800000 {
433 opp-hz = /bits/ 64 <1228800000>;
434 opp-peak-kBps = <2188000 15052800>;
437 cpu0_opp13: opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <2188000 16588800>;
442 cpu0_opp14: opp-1420800000 {
443 opp-hz = /bits/ 64 <1420800000>;
444 opp-peak-kBps = <3072000 18124800>;
447 cpu0_opp15: opp-1516800000 {
448 opp-hz = /bits/ 64 <1516800000>;
449 opp-peak-kBps = <3072000 19353600>;
452 cpu0_opp16: opp-1612800000 {
453 opp-hz = /bits/ 64 <1612800000>;
454 opp-peak-kBps = <4068000 19353600>;
457 cpu0_opp17: opp-1689600000 {
458 opp-hz = /bits/ 64 <1689600000>;
459 opp-peak-kBps = <4068000 20889600>;
462 cpu0_opp18: opp-1766400000 {
463 opp-hz = /bits/ 64 <1766400000>;
464 opp-peak-kBps = <4068000 22425600>;
468 cpu4_opp_table: opp-table-cpu4 {
469 compatible = "operating-points-v2";
470 opp-shared;
472 cpu4_opp1: opp-300000000 {
473 opp-hz = /bits/ 64 <300000000>;
474 opp-peak-kBps = <800000 4800000>;
477 cpu4_opp2: opp-403200000 {
478 opp-hz = /bits/ 64 <403200000>;
479 opp-peak-kBps = <800000 4800000>;
482 cpu4_opp3: opp-480000000 {
483 opp-hz = /bits/ 64 <480000000>;
484 opp-peak-kBps = <1804000 4800000>;
487 cpu4_opp4: opp-576000000 {
488 opp-hz = /bits/ 64 <576000000>;
489 opp-peak-kBps = <1804000 4800000>;
492 cpu4_opp5: opp-652800000 {
493 opp-hz = /bits/ 64 <652800000>;
494 opp-peak-kBps = <1804000 4800000>;
497 cpu4_opp6: opp-748800000 {
498 opp-hz = /bits/ 64 <748800000>;
499 opp-peak-kBps = <1804000 4800000>;
502 cpu4_opp7: opp-825600000 {
503 opp-hz = /bits/ 64 <825600000>;
504 opp-peak-kBps = <2188000 9216000>;
507 cpu4_opp8: opp-902400000 {
508 opp-hz = /bits/ 64 <902400000>;
509 opp-peak-kBps = <2188000 9216000>;
512 cpu4_opp9: opp-979200000 {
513 opp-hz = /bits/ 64 <979200000>;
514 opp-peak-kBps = <2188000 9216000>;
517 cpu4_opp10: opp-1056000000 {
518 opp-hz = /bits/ 64 <1056000000>;
519 opp-peak-kBps = <3072000 9216000>;
522 cpu4_opp11: opp-1132800000 {
523 opp-hz = /bits/ 64 <1132800000>;
524 opp-peak-kBps = <3072000 11980800>;
527 cpu4_opp12: opp-1209600000 {
528 opp-hz = /bits/ 64 <1209600000>;
529 opp-peak-kBps = <4068000 11980800>;
532 cpu4_opp13: opp-1286400000 {
533 opp-hz = /bits/ 64 <1286400000>;
534 opp-peak-kBps = <4068000 11980800>;
537 cpu4_opp14: opp-1363200000 {
538 opp-hz = /bits/ 64 <1363200000>;
539 opp-peak-kBps = <4068000 15052800>;
542 cpu4_opp15: opp-1459200000 {
543 opp-hz = /bits/ 64 <1459200000>;
544 opp-peak-kBps = <4068000 15052800>;
547 cpu4_opp16: opp-1536000000 {
548 opp-hz = /bits/ 64 <1536000000>;
549 opp-peak-kBps = <5412000 15052800>;
552 cpu4_opp17: opp-1612800000 {
553 opp-hz = /bits/ 64 <1612800000>;
554 opp-peak-kBps = <5412000 15052800>;
557 cpu4_opp18: opp-1689600000 {
558 opp-hz = /bits/ 64 <1689600000>;
559 opp-peak-kBps = <5412000 19353600>;
562 cpu4_opp19: opp-1766400000 {
563 opp-hz = /bits/ 64 <1766400000>;
564 opp-peak-kBps = <6220000 19353600>;
567 cpu4_opp20: opp-1843200000 {
568 opp-hz = /bits/ 64 <1843200000>;
569 opp-peak-kBps = <6220000 19353600>;
572 cpu4_opp21: opp-1920000000 {
573 opp-hz = /bits/ 64 <1920000000>;
574 opp-peak-kBps = <7216000 19353600>;
577 cpu4_opp22: opp-1996800000 {
578 opp-hz = /bits/ 64 <1996800000>;
579 opp-peak-kBps = <7216000 20889600>;
582 cpu4_opp23: opp-2092800000 {
583 opp-hz = /bits/ 64 <2092800000>;
584 opp-peak-kBps = <7216000 20889600>;
587 cpu4_opp24: opp-2169600000 {
588 opp-hz = /bits/ 64 <2169600000>;
589 opp-peak-kBps = <7216000 20889600>;
592 cpu4_opp25: opp-2246400000 {
593 opp-hz = /bits/ 64 <2246400000>;
594 opp-peak-kBps = <7216000 20889600>;
597 cpu4_opp26: opp-2323200000 {
598 opp-hz = /bits/ 64 <2323200000>;
599 opp-peak-kBps = <7216000 20889600>;
602 cpu4_opp27: opp-2400000000 {
603 opp-hz = /bits/ 64 <2400000000>;
604 opp-peak-kBps = <7216000 22425600>;
607 cpu4_opp28: opp-2476800000 {
608 opp-hz = /bits/ 64 <2476800000>;
609 opp-peak-kBps = <7216000 22425600>;
612 cpu4_opp29: opp-2553600000 {
613 opp-hz = /bits/ 64 <2553600000>;
614 opp-peak-kBps = <7216000 22425600>;
617 cpu4_opp30: opp-2649600000 {
618 opp-hz = /bits/ 64 <2649600000>;
619 opp-peak-kBps = <7216000 22425600>;
622 cpu4_opp31: opp-2745600000 {
623 opp-hz = /bits/ 64 <2745600000>;
624 opp-peak-kBps = <7216000 25497600>;
627 cpu4_opp32: opp-2803200000 {
628 opp-hz = /bits/ 64 <2803200000>;
629 opp-peak-kBps = <7216000 25497600>;
633 dsi_opp_table: opp-table-dsi {
634 compatible = "operating-points-v2";
636 opp-19200000 {
637 opp-hz = /bits/ 64 <19200000>;
638 required-opps = <&rpmhpd_opp_min_svs>;
641 opp-180000000 {
642 opp-hz = /bits/ 64 <180000000>;
643 required-opps = <&rpmhpd_opp_low_svs>;
646 opp-275000000 {
647 opp-hz = /bits/ 64 <275000000>;
648 required-opps = <&rpmhpd_opp_svs>;
651 opp-328580000 {
652 opp-hz = /bits/ 64 <328580000>;
653 required-opps = <&rpmhpd_opp_svs_l1>;
656 opp-358000000 {
657 opp-hz = /bits/ 64 <358000000>;
658 required-opps = <&rpmhpd_opp_nom>;
662 qspi_opp_table: opp-table-qspi {
663 compatible = "operating-points-v2";
665 opp-19200000 {
666 opp-hz = /bits/ 64 <19200000>;
667 required-opps = <&rpmhpd_opp_min_svs>;
670 opp-100000000 {
671 opp-hz = /bits/ 64 <100000000>;
672 required-opps = <&rpmhpd_opp_low_svs>;
675 opp-150000000 {
676 opp-hz = /bits/ 64 <150000000>;
677 required-opps = <&rpmhpd_opp_svs>;
680 opp-300000000 {
681 opp-hz = /bits/ 64 <300000000>;
682 required-opps = <&rpmhpd_opp_nom>;
686 qup_opp_table: opp-table-qup {
687 compatible = "operating-points-v2";
689 opp-50000000 {
690 opp-hz = /bits/ 64 <50000000>;
691 required-opps = <&rpmhpd_opp_min_svs>;
694 opp-75000000 {
695 opp-hz = /bits/ 64 <75000000>;
696 required-opps = <&rpmhpd_opp_low_svs>;
699 opp-100000000 {
700 opp-hz = /bits/ 64 <100000000>;
701 required-opps = <&rpmhpd_opp_svs>;
704 opp-128000000 {
705 opp-hz = /bits/ 64 <128000000>;
706 required-opps = <&rpmhpd_opp_nom>;
711 compatible = "arm,armv8-pmuv3";
716 compatible = "arm,psci-1.0";
719 CPU_PD0: power-domain-cpu0 {
720 #power-domain-cells = <0>;
721 power-domains = <&CLUSTER_PD>;
722 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
725 CPU_PD1: power-domain-cpu1 {
726 #power-domain-cells = <0>;
727 power-domains = <&CLUSTER_PD>;
728 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
731 CPU_PD2: power-domain-cpu2 {
732 #power-domain-cells = <0>;
733 power-domains = <&CLUSTER_PD>;
734 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
737 CPU_PD3: power-domain-cpu3 {
738 #power-domain-cells = <0>;
739 power-domains = <&CLUSTER_PD>;
740 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
743 CPU_PD4: power-domain-cpu4 {
744 #power-domain-cells = <0>;
745 power-domains = <&CLUSTER_PD>;
746 domain-idle-states = <&BIG_CPU_SLEEP_0>;
749 CPU_PD5: power-domain-cpu5 {
750 #power-domain-cells = <0>;
751 power-domains = <&CLUSTER_PD>;
752 domain-idle-states = <&BIG_CPU_SLEEP_0>;
755 CPU_PD6: power-domain-cpu6 {
756 #power-domain-cells = <0>;
757 power-domains = <&CLUSTER_PD>;
758 domain-idle-states = <&BIG_CPU_SLEEP_0>;
761 CPU_PD7: power-domain-cpu7 {
762 #power-domain-cells = <0>;
763 power-domains = <&CLUSTER_PD>;
764 domain-idle-states = <&BIG_CPU_SLEEP_0>;
767 CLUSTER_PD: power-domain-cluster {
768 #power-domain-cells = <0>;
769 domain-idle-states = <&CLUSTER_SLEEP_0>;
773 reserved-memory {
774 #address-cells = <2>;
775 #size-cells = <2>;
778 hyp_mem: hyp-mem@85700000 {
780 no-map;
783 xbl_mem: xbl-mem@85e00000 {
785 no-map;
788 aop_mem: aop-mem@85fc0000 {
790 no-map;
793 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
794 compatible = "qcom,cmd-db";
796 no-map;
802 no-map;
808 no-map;
812 compatible = "qcom,rmtfs-mem";
814 no-map;
816 qcom,client-id = <1>;
822 no-map;
825 camera_mem: camera-mem@8bf00000 {
827 no-map;
830 ipa_fw_mem: ipa-fw@8c400000 {
832 no-map;
835 ipa_gsi_mem: ipa-gsi@8c410000 {
837 no-map;
842 no-map;
847 no-map;
850 wlan_msa_mem: wlan-msa@8df00000 {
852 no-map;
857 no-map;
862 no-map;
867 no-map;
872 no-map;
877 no-map;
882 no-map;
885 mdata_mem: mpss-metadata {
886 alloc-ranges = <0 0xa0000000 0 0x20000000>;
888 no-map;
892 compatible = "shared-dma-pool";
893 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
900 adsp_pas: remoteproc-adsp {
901 compatible = "qcom,sdm845-adsp-pas";
903 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
908 interrupt-names = "wdog", "fatal", "ready",
909 "handover", "stop-ack";
912 clock-names = "xo";
914 memory-region = <&adsp_mem>;
918 qcom,smem-states = <&adsp_smp2p_out 0>;
919 qcom,smem-state-names = "stop";
923 glink-edge {
926 qcom,remote-pid = <2>;
930 compatible = "qcom,apr-v2";
931 qcom,glink-channels = "apr_audio_svc";
933 #address-cells = <1>;
934 #size-cells = <0>;
940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
946 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 compatible = "qcom,q6afe-dais";
949 #address-cells = <1>;
950 #size-cells = <0>;
951 #sound-dai-cells = <1>;
958 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 compatible = "qcom,q6asm-dais";
961 #address-cells = <1>;
962 #size-cells = <0>;
963 #sound-dai-cells = <1>;
971 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 compatible = "qcom,q6adm-routing";
974 #sound-dai-cells = <0>;
981 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 qcom,non-secure-domain;
984 #address-cells = <1>;
985 #size-cells = <0>;
987 compute-cb@3 {
988 compatible = "qcom,fastrpc-compute-cb";
993 compute-cb@4 {
994 compatible = "qcom,fastrpc-compute-cb";
1002 cdsp_pas: remoteproc-cdsp {
1003 compatible = "qcom,sdm845-cdsp-pas";
1005 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1010 interrupt-names = "wdog", "fatal", "ready",
1011 "handover", "stop-ack";
1014 clock-names = "xo";
1016 memory-region = <&cdsp_mem>;
1020 qcom,smem-states = <&cdsp_smp2p_out 0>;
1021 qcom,smem-state-names = "stop";
1025 glink-edge {
1028 qcom,remote-pid = <5>;
1032 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 qcom,non-secure-domain;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1038 compute-cb@1 {
1039 compatible = "qcom,fastrpc-compute-cb";
1044 compute-cb@2 {
1045 compatible = "qcom,fastrpc-compute-cb";
1050 compute-cb@3 {
1051 compatible = "qcom,fastrpc-compute-cb";
1056 compute-cb@4 {
1057 compatible = "qcom,fastrpc-compute-cb";
1062 compute-cb@5 {
1063 compatible = "qcom,fastrpc-compute-cb";
1068 compute-cb@6 {
1069 compatible = "qcom,fastrpc-compute-cb";
1074 compute-cb@7 {
1075 compatible = "qcom,fastrpc-compute-cb";
1080 compute-cb@8 {
1081 compatible = "qcom,fastrpc-compute-cb";
1089 smp2p-cdsp {
1097 qcom,local-pid = <0>;
1098 qcom,remote-pid = <5>;
1100 cdsp_smp2p_out: master-kernel {
1101 qcom,entry-name = "master-kernel";
1102 #qcom,smem-state-cells = <1>;
1105 cdsp_smp2p_in: slave-kernel {
1106 qcom,entry-name = "slave-kernel";
1108 interrupt-controller;
1109 #interrupt-cells = <2>;
1113 smp2p-lpass {
1121 qcom,local-pid = <0>;
1122 qcom,remote-pid = <2>;
1124 adsp_smp2p_out: master-kernel {
1125 qcom,entry-name = "master-kernel";
1126 #qcom,smem-state-cells = <1>;
1129 adsp_smp2p_in: slave-kernel {
1130 qcom,entry-name = "slave-kernel";
1132 interrupt-controller;
1133 #interrupt-cells = <2>;
1137 smp2p-mpss {
1142 qcom,local-pid = <0>;
1143 qcom,remote-pid = <1>;
1145 modem_smp2p_out: master-kernel {
1146 qcom,entry-name = "master-kernel";
1147 #qcom,smem-state-cells = <1>;
1150 modem_smp2p_in: slave-kernel {
1151 qcom,entry-name = "slave-kernel";
1152 interrupt-controller;
1153 #interrupt-cells = <2>;
1156 ipa_smp2p_out: ipa-ap-to-modem {
1157 qcom,entry-name = "ipa";
1158 #qcom,smem-state-cells = <1>;
1161 ipa_smp2p_in: ipa-modem-to-ap {
1162 qcom,entry-name = "ipa";
1163 interrupt-controller;
1164 #interrupt-cells = <2>;
1168 smp2p-slpi {
1173 qcom,local-pid = <0>;
1174 qcom,remote-pid = <3>;
1176 slpi_smp2p_out: master-kernel {
1177 qcom,entry-name = "master-kernel";
1178 #qcom,smem-state-cells = <1>;
1181 slpi_smp2p_in: slave-kernel {
1182 qcom,entry-name = "slave-kernel";
1183 interrupt-controller;
1184 #interrupt-cells = <2>;
1189 #address-cells = <2>;
1190 #size-cells = <2>;
1192 dma-ranges = <0 0 0 0 0x10 0>;
1193 compatible = "simple-bus";
1195 gcc: clock-controller@100000 {
1196 compatible = "qcom,gcc-sdm845";
1203 clock-names = "bi_tcxo",
1208 #clock-cells = <1>;
1209 #reset-cells = <1>;
1210 #power-domain-cells = <1>;
1211 power-domains = <&rpmhpd SDM845_CX>;
1215 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 #address-cells = <1>;
1218 #size-cells = <1>;
1220 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1225 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1232 compatible = "qcom,prng-ee";
1235 clock-names = "core";
1238 gpi_dma0: dma-controller@800000 {
1239 #dma-cells = <3>;
1240 compatible = "qcom,sdm845-gpi-dma";
1255 dma-channels = <13>;
1256 dma-channel-mask = <0xfa>;
1262 compatible = "qcom,geni-se-qup";
1264 clock-names = "m-ahb", "s-ahb";
1268 #address-cells = <2>;
1269 #size-cells = <2>;
1272 interconnect-names = "qup-core";
1276 compatible = "qcom,geni-i2c";
1278 clock-names = "se";
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_i2c0_default>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 power-domains = <&rpmhpd SDM845_CX>;
1286 operating-points-v2 = <&qup_opp_table>;
1290 interconnect-names = "qup-core", "qup-config", "qup-memory";
1293 dma-names = "tx", "rx";
1298 compatible = "qcom,geni-spi";
1300 clock-names = "se";
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_spi0_default>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1309 interconnect-names = "qup-core", "qup-config";
1312 dma-names = "tx", "rx";
1317 compatible = "qcom,geni-uart";
1319 clock-names = "se";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_uart0_default>;
1324 power-domains = <&rpmhpd SDM845_CX>;
1325 operating-points-v2 = <&qup_opp_table>;
1328 interconnect-names = "qup-core", "qup-config";
1333 compatible = "qcom,geni-i2c";
1335 clock-names = "se";
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&qup_i2c1_default>;
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342 power-domains = <&rpmhpd SDM845_CX>;
1343 operating-points-v2 = <&qup_opp_table>;
1347 interconnect-names = "qup-core", "qup-config", "qup-memory";
1350 dma-names = "tx", "rx";
1355 compatible = "qcom,geni-spi";
1357 clock-names = "se";
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_spi1_default>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1366 interconnect-names = "qup-core", "qup-config";
1369 dma-names = "tx", "rx";
1374 compatible = "qcom,geni-uart";
1376 clock-names = "se";
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&qup_uart1_default>;
1381 power-domains = <&rpmhpd SDM845_CX>;
1382 operating-points-v2 = <&qup_opp_table>;
1385 interconnect-names = "qup-core", "qup-config";
1390 compatible = "qcom,geni-i2c";
1392 clock-names = "se";
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&qup_i2c2_default>;
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1399 power-domains = <&rpmhpd SDM845_CX>;
1400 operating-points-v2 = <&qup_opp_table>;
1404 interconnect-names = "qup-core", "qup-config", "qup-memory";
1407 dma-names = "tx", "rx";
1412 compatible = "qcom,geni-spi";
1414 clock-names = "se";
1416 pinctrl-names = "default";
1417 pinctrl-0 = <&qup_spi2_default>;
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1423 interconnect-names = "qup-core", "qup-config";
1426 dma-names = "tx", "rx";
1431 compatible = "qcom,geni-uart";
1433 clock-names = "se";
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_uart2_default>;
1438 power-domains = <&rpmhpd SDM845_CX>;
1439 operating-points-v2 = <&qup_opp_table>;
1442 interconnect-names = "qup-core", "qup-config";
1447 compatible = "qcom,geni-i2c";
1449 clock-names = "se";
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&qup_i2c3_default>;
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456 power-domains = <&rpmhpd SDM845_CX>;
1457 operating-points-v2 = <&qup_opp_table>;
1461 interconnect-names = "qup-core", "qup-config", "qup-memory";
1464 dma-names = "tx", "rx";
1469 compatible = "qcom,geni-spi";
1471 clock-names = "se";
1473 pinctrl-names = "default";
1474 pinctrl-0 = <&qup_spi3_default>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1480 interconnect-names = "qup-core", "qup-config";
1483 dma-names = "tx", "rx";
1488 compatible = "qcom,geni-uart";
1490 clock-names = "se";
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&qup_uart3_default>;
1495 power-domains = <&rpmhpd SDM845_CX>;
1496 operating-points-v2 = <&qup_opp_table>;
1499 interconnect-names = "qup-core", "qup-config";
1504 compatible = "qcom,geni-i2c";
1506 clock-names = "se";
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&qup_i2c4_default>;
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1513 power-domains = <&rpmhpd SDM845_CX>;
1514 operating-points-v2 = <&qup_opp_table>;
1518 interconnect-names = "qup-core", "qup-config", "qup-memory";
1521 dma-names = "tx", "rx";
1526 compatible = "qcom,geni-spi";
1528 clock-names = "se";
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_spi4_default>;
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1537 interconnect-names = "qup-core", "qup-config";
1540 dma-names = "tx", "rx";
1545 compatible = "qcom,geni-uart";
1547 clock-names = "se";
1549 pinctrl-names = "default";
1550 pinctrl-0 = <&qup_uart4_default>;
1552 power-domains = <&rpmhpd SDM845_CX>;
1553 operating-points-v2 = <&qup_opp_table>;
1556 interconnect-names = "qup-core", "qup-config";
1561 compatible = "qcom,geni-i2c";
1563 clock-names = "se";
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c5_default>;
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1570 power-domains = <&rpmhpd SDM845_CX>;
1571 operating-points-v2 = <&qup_opp_table>;
1575 interconnect-names = "qup-core", "qup-config", "qup-memory";
1578 dma-names = "tx", "rx";
1583 compatible = "qcom,geni-spi";
1585 clock-names = "se";
1587 pinctrl-names = "default";
1588 pinctrl-0 = <&qup_spi5_default>;
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1594 interconnect-names = "qup-core", "qup-config";
1597 dma-names = "tx", "rx";
1602 compatible = "qcom,geni-uart";
1604 clock-names = "se";
1606 pinctrl-names = "default";
1607 pinctrl-0 = <&qup_uart5_default>;
1609 power-domains = <&rpmhpd SDM845_CX>;
1610 operating-points-v2 = <&qup_opp_table>;
1613 interconnect-names = "qup-core", "qup-config";
1618 compatible = "qcom,geni-i2c";
1620 clock-names = "se";
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&qup_i2c6_default>;
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1627 power-domains = <&rpmhpd SDM845_CX>;
1628 operating-points-v2 = <&qup_opp_table>;
1632 interconnect-names = "qup-core", "qup-config", "qup-memory";
1635 dma-names = "tx", "rx";
1640 compatible = "qcom,geni-spi";
1642 clock-names = "se";
1644 pinctrl-names = "default";
1645 pinctrl-0 = <&qup_spi6_default>;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1651 interconnect-names = "qup-core", "qup-config";
1654 dma-names = "tx", "rx";
1659 compatible = "qcom,geni-uart";
1661 clock-names = "se";
1663 pinctrl-names = "default";
1664 pinctrl-0 = <&qup_uart6_default>;
1666 power-domains = <&rpmhpd SDM845_CX>;
1667 operating-points-v2 = <&qup_opp_table>;
1670 interconnect-names = "qup-core", "qup-config";
1675 compatible = "qcom,geni-i2c";
1677 clock-names = "se";
1679 pinctrl-names = "default";
1680 pinctrl-0 = <&qup_i2c7_default>;
1682 #address-cells = <1>;
1683 #size-cells = <0>;
1684 power-domains = <&rpmhpd SDM845_CX>;
1685 operating-points-v2 = <&qup_opp_table>;
1690 compatible = "qcom,geni-spi";
1692 clock-names = "se";
1694 pinctrl-names = "default";
1695 pinctrl-0 = <&qup_spi7_default>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1701 interconnect-names = "qup-core", "qup-config";
1704 dma-names = "tx", "rx";
1709 compatible = "qcom,geni-uart";
1711 clock-names = "se";
1713 pinctrl-names = "default";
1714 pinctrl-0 = <&qup_uart7_default>;
1716 power-domains = <&rpmhpd SDM845_CX>;
1717 operating-points-v2 = <&qup_opp_table>;
1720 interconnect-names = "qup-core", "qup-config";
1725 gpi_dma1: dma-controller@a00000 {
1726 #dma-cells = <3>;
1727 compatible = "qcom,sdm845-gpi-dma";
1742 dma-channels = <13>;
1743 dma-channel-mask = <0xfa>;
1749 compatible = "qcom,geni-se-qup";
1751 clock-names = "m-ahb", "s-ahb";
1755 #address-cells = <2>;
1756 #size-cells = <2>;
1759 interconnect-names = "qup-core";
1763 compatible = "qcom,geni-i2c";
1765 clock-names = "se";
1767 pinctrl-names = "default";
1768 pinctrl-0 = <&qup_i2c8_default>;
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1772 power-domains = <&rpmhpd SDM845_CX>;
1773 operating-points-v2 = <&qup_opp_table>;
1777 interconnect-names = "qup-core", "qup-config", "qup-memory";
1780 dma-names = "tx", "rx";
1785 compatible = "qcom,geni-spi";
1787 clock-names = "se";
1789 pinctrl-names = "default";
1790 pinctrl-0 = <&qup_spi8_default>;
1792 #address-cells = <1>;
1793 #size-cells = <0>;
1796 interconnect-names = "qup-core", "qup-config";
1799 dma-names = "tx", "rx";
1804 compatible = "qcom,geni-uart";
1806 clock-names = "se";
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_uart8_default>;
1811 power-domains = <&rpmhpd SDM845_CX>;
1812 operating-points-v2 = <&qup_opp_table>;
1815 interconnect-names = "qup-core", "qup-config";
1820 compatible = "qcom,geni-i2c";
1822 clock-names = "se";
1824 pinctrl-names = "default";
1825 pinctrl-0 = <&qup_i2c9_default>;
1827 #address-cells = <1>;
1828 #size-cells = <0>;
1829 power-domains = <&rpmhpd SDM845_CX>;
1830 operating-points-v2 = <&qup_opp_table>;
1834 interconnect-names = "qup-core", "qup-config", "qup-memory";
1837 dma-names = "tx", "rx";
1842 compatible = "qcom,geni-spi";
1844 clock-names = "se";
1846 pinctrl-names = "default";
1847 pinctrl-0 = <&qup_spi9_default>;
1849 #address-cells = <1>;
1850 #size-cells = <0>;
1853 interconnect-names = "qup-core", "qup-config";
1856 dma-names = "tx", "rx";
1861 compatible = "qcom,geni-debug-uart";
1863 clock-names = "se";
1865 pinctrl-names = "default";
1866 pinctrl-0 = <&qup_uart9_default>;
1868 power-domains = <&rpmhpd SDM845_CX>;
1869 operating-points-v2 = <&qup_opp_table>;
1872 interconnect-names = "qup-core", "qup-config";
1877 compatible = "qcom,geni-i2c";
1879 clock-names = "se";
1881 pinctrl-names = "default";
1882 pinctrl-0 = <&qup_i2c10_default>;
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1886 power-domains = <&rpmhpd SDM845_CX>;
1887 operating-points-v2 = <&qup_opp_table>;
1891 interconnect-names = "qup-core", "qup-config", "qup-memory";
1894 dma-names = "tx", "rx";
1899 compatible = "qcom,geni-spi";
1901 clock-names = "se";
1903 pinctrl-names = "default";
1904 pinctrl-0 = <&qup_spi10_default>;
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1910 interconnect-names = "qup-core", "qup-config";
1913 dma-names = "tx", "rx";
1918 compatible = "qcom,geni-uart";
1920 clock-names = "se";
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&qup_uart10_default>;
1925 power-domains = <&rpmhpd SDM845_CX>;
1926 operating-points-v2 = <&qup_opp_table>;
1929 interconnect-names = "qup-core", "qup-config";
1934 compatible = "qcom,geni-i2c";
1936 clock-names = "se";
1938 pinctrl-names = "default";
1939 pinctrl-0 = <&qup_i2c11_default>;
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1943 power-domains = <&rpmhpd SDM845_CX>;
1944 operating-points-v2 = <&qup_opp_table>;
1948 interconnect-names = "qup-core", "qup-config", "qup-memory";
1951 dma-names = "tx", "rx";
1956 compatible = "qcom,geni-spi";
1958 clock-names = "se";
1960 pinctrl-names = "default";
1961 pinctrl-0 = <&qup_spi11_default>;
1963 #address-cells = <1>;
1964 #size-cells = <0>;
1967 interconnect-names = "qup-core", "qup-config";
1970 dma-names = "tx", "rx";
1975 compatible = "qcom,geni-uart";
1977 clock-names = "se";
1979 pinctrl-names = "default";
1980 pinctrl-0 = <&qup_uart11_default>;
1982 power-domains = <&rpmhpd SDM845_CX>;
1983 operating-points-v2 = <&qup_opp_table>;
1986 interconnect-names = "qup-core", "qup-config";
1991 compatible = "qcom,geni-i2c";
1993 clock-names = "se";
1995 pinctrl-names = "default";
1996 pinctrl-0 = <&qup_i2c12_default>;
1998 #address-cells = <1>;
1999 #size-cells = <0>;
2000 power-domains = <&rpmhpd SDM845_CX>;
2001 operating-points-v2 = <&qup_opp_table>;
2005 interconnect-names = "qup-core", "qup-config", "qup-memory";
2008 dma-names = "tx", "rx";
2013 compatible = "qcom,geni-spi";
2015 clock-names = "se";
2017 pinctrl-names = "default";
2018 pinctrl-0 = <&qup_spi12_default>;
2020 #address-cells = <1>;
2021 #size-cells = <0>;
2024 interconnect-names = "qup-core", "qup-config";
2027 dma-names = "tx", "rx";
2032 compatible = "qcom,geni-uart";
2034 clock-names = "se";
2036 pinctrl-names = "default";
2037 pinctrl-0 = <&qup_uart12_default>;
2039 power-domains = <&rpmhpd SDM845_CX>;
2040 operating-points-v2 = <&qup_opp_table>;
2043 interconnect-names = "qup-core", "qup-config";
2048 compatible = "qcom,geni-i2c";
2050 clock-names = "se";
2052 pinctrl-names = "default";
2053 pinctrl-0 = <&qup_i2c13_default>;
2055 #address-cells = <1>;
2056 #size-cells = <0>;
2057 power-domains = <&rpmhpd SDM845_CX>;
2058 operating-points-v2 = <&qup_opp_table>;
2062 interconnect-names = "qup-core", "qup-config", "qup-memory";
2065 dma-names = "tx", "rx";
2070 compatible = "qcom,geni-spi";
2072 clock-names = "se";
2074 pinctrl-names = "default";
2075 pinctrl-0 = <&qup_spi13_default>;
2077 #address-cells = <1>;
2078 #size-cells = <0>;
2081 interconnect-names = "qup-core", "qup-config";
2084 dma-names = "tx", "rx";
2089 compatible = "qcom,geni-uart";
2091 clock-names = "se";
2093 pinctrl-names = "default";
2094 pinctrl-0 = <&qup_uart13_default>;
2096 power-domains = <&rpmhpd SDM845_CX>;
2097 operating-points-v2 = <&qup_opp_table>;
2100 interconnect-names = "qup-core", "qup-config";
2105 compatible = "qcom,geni-i2c";
2107 clock-names = "se";
2109 pinctrl-names = "default";
2110 pinctrl-0 = <&qup_i2c14_default>;
2112 #address-cells = <1>;
2113 #size-cells = <0>;
2114 power-domains = <&rpmhpd SDM845_CX>;
2115 operating-points-v2 = <&qup_opp_table>;
2119 interconnect-names = "qup-core", "qup-config", "qup-memory";
2122 dma-names = "tx", "rx";
2127 compatible = "qcom,geni-spi";
2129 clock-names = "se";
2131 pinctrl-names = "default";
2132 pinctrl-0 = <&qup_spi14_default>;
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2138 interconnect-names = "qup-core", "qup-config";
2141 dma-names = "tx", "rx";
2146 compatible = "qcom,geni-uart";
2148 clock-names = "se";
2150 pinctrl-names = "default";
2151 pinctrl-0 = <&qup_uart14_default>;
2153 power-domains = <&rpmhpd SDM845_CX>;
2154 operating-points-v2 = <&qup_opp_table>;
2157 interconnect-names = "qup-core", "qup-config";
2162 compatible = "qcom,geni-i2c";
2164 clock-names = "se";
2166 pinctrl-names = "default";
2167 pinctrl-0 = <&qup_i2c15_default>;
2169 #address-cells = <1>;
2170 #size-cells = <0>;
2171 power-domains = <&rpmhpd SDM845_CX>;
2172 operating-points-v2 = <&qup_opp_table>;
2177 interconnect-names = "qup-core", "qup-config", "qup-memory";
2180 dma-names = "tx", "rx";
2184 compatible = "qcom,geni-spi";
2186 clock-names = "se";
2188 pinctrl-names = "default";
2189 pinctrl-0 = <&qup_spi15_default>;
2191 #address-cells = <1>;
2192 #size-cells = <0>;
2195 interconnect-names = "qup-core", "qup-config";
2198 dma-names = "tx", "rx";
2203 compatible = "qcom,geni-uart";
2205 clock-names = "se";
2207 pinctrl-names = "default";
2208 pinctrl-0 = <&qup_uart15_default>;
2210 power-domains = <&rpmhpd SDM845_CX>;
2211 operating-points-v2 = <&qup_opp_table>;
2214 interconnect-names = "qup-core", "qup-config";
2219 llcc: system-cache-controller@1100000 {
2220 compatible = "qcom,sdm845-llcc";
2224 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2230 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2236 compatible = "qcom,sdm845-llcc-bwmon";
2241 operating-points-v2 = <&llcc_bwmon_opp_table>;
2243 llcc_bwmon_opp_table: opp-table {
2244 compatible = "operating-points-v2";
2248 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2250 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2251 * bus width: 4 bytes) from msm-4.9 downstream
2254 opp-0 {
2255 opp-peak-kBps = <800000>;
2257 opp-1 {
2258 opp-peak-kBps = <1804000>;
2260 opp-2 {
2261 opp-peak-kBps = <3072000>;
2263 opp-3 {
2264 opp-peak-kBps = <5412000>;
2266 opp-4 {
2267 opp-peak-kBps = <7216000>;
2273 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2278 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 cpu_bwmon_opp_table: opp-table {
2281 compatible = "operating-points-v2";
2287 * from bandwidth table of qcom,cpu4-l3lat-mon
2288 * (qcom,core-dev-table, bus width: 16 bytes)
2289 * from msm-4.9 downstream kernel.
2291 opp-0 {
2292 opp-peak-kBps = <4800000>;
2294 opp-1 {
2295 opp-peak-kBps = <9216000>;
2297 opp-2 {
2298 opp-peak-kBps = <15052800>;
2300 opp-3 {
2301 opp-peak-kBps = <20889600>;
2303 opp-4 {
2304 opp-peak-kBps = <25497600>;
2310 compatible = "qcom,pcie-sdm845";
2316 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2318 linux,pci-domain = <0>;
2319 bus-range = <0x00 0xff>;
2320 num-lanes = <1>;
2322 #address-cells = <3>;
2323 #size-cells = <2>;
2329 interrupt-names = "msi";
2330 #interrupt-cells = <1>;
2331 interrupt-map-mask = <0 0 0 0x7>;
2332 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2344 clock-names = "pipe",
2352 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2370 reset-names = "pci";
2372 power-domains = <&gcc PCIE_0_GDSC>;
2375 phy-names = "pciephy";
2381 compatible = "qcom,sdm845-qmp-pcie-phy";
2388 clock-names = "aux",
2394 clock-output-names = "pcie_0_pipe_clk";
2395 #clock-cells = <0>;
2397 #phy-cells = <0>;
2400 reset-names = "phy";
2402 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2403 assigned-clock-rates = <100000000>;
2409 compatible = "qcom,pcie-sdm845";
2415 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2417 linux,pci-domain = <1>;
2418 bus-range = <0x00 0xff>;
2419 num-lanes = <1>;
2421 #address-cells = <3>;
2422 #size-cells = <2>;
2428 interrupt-names = "msi";
2429 #interrupt-cells = <1>;
2430 interrupt-map-mask = <0 0 0 0x7>;
2431 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2444 clock-names = "pipe",
2453 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2454 assigned-clock-rates = <19200000>;
2456 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2474 reset-names = "pci";
2476 power-domains = <&gcc PCIE_1_GDSC>;
2479 phy-names = "pciephy";
2485 compatible = "qcom,sdm845-qhp-pcie-phy";
2492 clock-names = "aux",
2498 clock-output-names = "pcie_1_pipe_clk";
2499 #clock-cells = <0>;
2501 #phy-cells = <0>;
2504 reset-names = "phy";
2506 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2507 assigned-clock-rates = <100000000>;
2513 compatible = "qcom,sdm845-mem-noc";
2515 #interconnect-cells = <2>;
2516 qcom,bcm-voters = <&apps_bcm_voter>;
2520 compatible = "qcom,sdm845-dc-noc";
2522 #interconnect-cells = <2>;
2523 qcom,bcm-voters = <&apps_bcm_voter>;
2527 compatible = "qcom,sdm845-config-noc";
2529 #interconnect-cells = <2>;
2530 qcom,bcm-voters = <&apps_bcm_voter>;
2534 compatible = "qcom,sdm845-system-noc";
2536 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&apps_bcm_voter>;
2541 compatible = "qcom,sdm845-aggre1-noc";
2543 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&apps_bcm_voter>;
2548 compatible = "qcom,sdm845-aggre2-noc";
2550 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&apps_bcm_voter>;
2555 compatible = "qcom,sdm845-mmss-noc";
2557 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&apps_bcm_voter>;
2562 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2563 "jedec,ufs-2.0";
2566 reg-names = "std", "ice";
2569 phy-names = "ufsphy";
2570 lanes-per-direction = <2>;
2571 power-domains = <&gcc UFS_PHY_GDSC>;
2572 #reset-cells = <1>;
2574 reset-names = "rst";
2578 clock-names =
2599 operating-points-v2 = <&ufs_opp_table>;
2603 interconnect-names = "ufs-ddr", "cpu-ufs";
2607 ufs_opp_table: opp-table {
2608 compatible = "operating-points-v2";
2610 opp-50000000 {
2611 opp-hz = /bits/ 64 <50000000>,
2620 required-opps = <&rpmhpd_opp_low_svs>;
2623 opp-200000000 {
2624 opp-hz = /bits/ 64 <200000000>,
2633 required-opps = <&rpmhpd_opp_nom>;
2639 compatible = "qcom,sdm845-qmp-ufs-phy";
2642 clock-names = "ref",
2648 reset-names = "ufsphy";
2650 #phy-cells = <0>;
2654 cryptobam: dma-controller@1dc4000 {
2655 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2659 clock-names = "bam_clk";
2660 #dma-cells = <1>;
2662 qcom,controlled-remotely;
2670 compatible = "qcom,crypto-v5.4";
2675 clock-names = "iface", "bus", "core";
2677 dma-names = "rx", "tx";
2685 compatible = "qcom,sdm845-ipa";
2692 reg-names = "ipa-reg",
2693 "ipa-shared",
2696 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2700 interrupt-names = "ipa",
2702 "ipa-clock-query",
2703 "ipa-setup-ready";
2706 clock-names = "core";
2711 interconnect-names = "memory",
2715 qcom,smem-states = <&ipa_smp2p_out 0>,
2717 qcom,smem-state-names = "ipa-clock-enabled-valid",
2718 "ipa-clock-enabled";
2724 compatible = "qcom,tcsr-mutex";
2726 #hwlock-cells = <1>;
2730 compatible = "qcom,sdm845-tcsr", "syscon";
2735 compatible = "qcom,sdm845-pinctrl";
2738 gpio-controller;
2739 #gpio-cells = <2>;
2740 interrupt-controller;
2741 #interrupt-cells = <2>;
2742 gpio-ranges = <&tlmm 0 0 151>;
2743 wakeup-parent = <&pdc_intc>;
2745 cci0_default: cci0-default-state {
2750 bias-pull-up;
2751 drive-strength = <2>; /* 2 mA */
2754 cci0_sleep: cci0-sleep-state {
2759 drive-strength = <2>; /* 2 mA */
2760 bias-pull-down;
2763 cci1_default: cci1-default-state {
2768 bias-pull-up;
2769 drive-strength = <2>; /* 2 mA */
2772 cci1_sleep: cci1-sleep-state {
2777 drive-strength = <2>; /* 2 mA */
2778 bias-pull-down;
2781 qspi_clk: qspi-clk-state {
2786 qspi_cs0: qspi-cs0-state {
2791 qspi_cs1: qspi-cs1-state {
2796 qspi_data0: qspi-data0-state {
2801 qspi_data1: qspi-data1-state {
2806 qspi_data23: qspi-data23-state {
2811 qup_i2c0_default: qup-i2c0-default-state {
2816 qup_i2c1_default: qup-i2c1-default-state {
2821 qup_i2c2_default: qup-i2c2-default-state {
2826 qup_i2c3_default: qup-i2c3-default-state {
2831 qup_i2c4_default: qup-i2c4-default-state {
2836 qup_i2c5_default: qup-i2c5-default-state {
2841 qup_i2c6_default: qup-i2c6-default-state {
2846 qup_i2c7_default: qup-i2c7-default-state {
2851 qup_i2c8_default: qup-i2c8-default-state {
2856 qup_i2c9_default: qup-i2c9-default-state {
2861 qup_i2c10_default: qup-i2c10-default-state {
2866 qup_i2c11_default: qup-i2c11-default-state {
2871 qup_i2c12_default: qup-i2c12-default-state {
2876 qup_i2c13_default: qup-i2c13-default-state {
2881 qup_i2c14_default: qup-i2c14-default-state {
2886 qup_i2c15_default: qup-i2c15-default-state {
2891 qup_spi0_default: qup-spi0-default-state {
2896 qup_spi1_default: qup-spi1-default-state {
2901 qup_spi2_default: qup-spi2-default-state {
2906 qup_spi3_default: qup-spi3-default-state {
2911 qup_spi4_default: qup-spi4-default-state {
2916 qup_spi5_default: qup-spi5-default-state {
2921 qup_spi6_default: qup-spi6-default-state {
2926 qup_spi7_default: qup-spi7-default-state {
2931 qup_spi8_default: qup-spi8-default-state {
2936 qup_spi9_default: qup-spi9-default-state {
2941 qup_spi10_default: qup-spi10-default-state {
2946 qup_spi11_default: qup-spi11-default-state {
2951 qup_spi12_default: qup-spi12-default-state {
2956 qup_spi13_default: qup-spi13-default-state {
2961 qup_spi14_default: qup-spi14-default-state {
2966 qup_spi15_default: qup-spi15-default-state {
2971 qup_uart0_default: qup-uart0-default-state {
2972 qup_uart0_tx: tx-pins {
2977 qup_uart0_rx: rx-pins {
2983 qup_uart1_default: qup-uart1-default-state {
2984 qup_uart1_tx: tx-pins {
2989 qup_uart1_rx: rx-pins {
2995 qup_uart2_default: qup-uart2-default-state {
2996 qup_uart2_tx: tx-pins {
3001 qup_uart2_rx: rx-pins {
3007 qup_uart3_default: qup-uart3-default-state {
3008 qup_uart3_tx: tx-pins {
3013 qup_uart3_rx: rx-pins {
3019 qup_uart3_4pin: qup-uart3-4pin-state {
3020 qup_uart3_4pin_cts: cts-pins {
3025 qup_uart3_4pin_rts_tx: rts-tx-pins {
3030 qup_uart3_4pin_rx: rx-pins {
3036 qup_uart4_default: qup-uart4-default-state {
3037 qup_uart4_tx: tx-pins {
3042 qup_uart4_rx: rx-pins {
3048 qup_uart5_default: qup-uart5-default-state {
3049 qup_uart5_tx: tx-pins {
3054 qup_uart5_rx: rx-pins {
3060 qup_uart6_default: qup-uart6-default-state {
3061 qup_uart6_tx: tx-pins {
3066 qup_uart6_rx: rx-pins {
3072 qup_uart6_4pin: qup-uart6-4pin-state {
3073 qup_uart6_4pin_cts: cts-pins {
3076 bias-pull-down;
3079 qup_uart6_4pin_rts_tx: rts-tx-pins {
3082 drive-strength = <2>;
3083 bias-disable;
3086 qup_uart6_4pin_rx: rx-pins {
3089 bias-pull-up;
3093 qup_uart7_default: qup-uart7-default-state {
3094 qup_uart7_tx: tx-pins {
3099 qup_uart7_rx: rx-pins {
3105 qup_uart8_default: qup-uart8-default-state {
3106 qup_uart8_tx: tx-pins {
3111 qup_uart8_rx: rx-pins {
3117 qup_uart9_default: qup-uart9-default-state {
3118 qup_uart9_tx: tx-pins {
3123 qup_uart9_rx: rx-pins {
3129 qup_uart10_default: qup-uart10-default-state {
3130 qup_uart10_tx: tx-pins {
3135 qup_uart10_rx: rx-pins {
3141 qup_uart11_default: qup-uart11-default-state {
3142 qup_uart11_tx: tx-pins {
3147 qup_uart11_rx: rx-pins {
3153 qup_uart12_default: qup-uart12-default-state {
3154 qup_uart12_tx: tx-pins {
3159 qup_uart12_rx: rx-pins {
3165 qup_uart13_default: qup-uart13-default-state {
3166 qup_uart13_tx: tx-pins {
3171 qup_uart13_rx: rx-pins {
3177 qup_uart14_default: qup-uart14-default-state {
3178 qup_uart14_tx: tx-pins {
3183 qup_uart14_rx: rx-pins {
3189 qup_uart15_default: qup-uart15-default-state {
3190 qup_uart15_tx: tx-pins {
3195 qup_uart15_rx: rx-pins {
3201 quat_mi2s_sleep: quat-mi2s-sleep-state {
3204 drive-strength = <2>;
3205 bias-pull-down;
3208 quat_mi2s_active: quat-mi2s-active-state {
3211 drive-strength = <8>;
3212 bias-disable;
3213 output-high;
3216 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3219 drive-strength = <2>;
3220 bias-pull-down;
3223 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3226 drive-strength = <8>;
3227 bias-disable;
3230 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3233 drive-strength = <2>;
3234 bias-pull-down;
3237 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3240 drive-strength = <8>;
3241 bias-disable;
3244 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3247 drive-strength = <2>;
3248 bias-pull-down;
3251 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3254 drive-strength = <8>;
3255 bias-disable;
3258 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3261 drive-strength = <2>;
3262 bias-pull-down;
3265 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3268 drive-strength = <8>;
3269 bias-disable;
3274 compatible = "qcom,sdm845-mss-pil";
3276 reg-names = "qdsp6", "rmb";
3278 interrupts-extended =
3285 interrupt-names = "wdog", "fatal", "ready",
3286 "handover", "stop-ack",
3287 "shutdown-ack";
3297 clock-names = "iface", "bus", "mem", "gpll0_mss",
3302 qcom,smem-states = <&modem_smp2p_out 0>;
3303 qcom,smem-state-names = "stop";
3307 reset-names = "mss_restart", "pdc_reset";
3309 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3311 power-domains = <&rpmhpd SDM845_CX>,
3314 power-domain-names = "cx", "mx", "mss";
3319 memory-region = <&mba_region>;
3323 memory-region = <&mpss_region>;
3327 memory-region = <&mdata_mem>;
3330 glink-edge {
3333 qcom,remote-pid = <1>;
3338 gpucc: clock-controller@5090000 {
3339 compatible = "qcom,sdm845-gpucc";
3341 #clock-cells = <1>;
3342 #reset-cells = <1>;
3343 #power-domain-cells = <1>;
3347 clock-names = "bi_tcxo",
3353 compatible = "qcom,sdm845-slpi-pas";
3356 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3361 interrupt-names = "wdog", "fatal", "ready",
3362 "handover", "stop-ack";
3365 clock-names = "xo";
3369 power-domains = <&rpmhpd SDM845_CX>,
3371 power-domain-names = "lcx", "lmx";
3373 memory-region = <&slpi_mem>;
3375 qcom,smem-states = <&slpi_smp2p_out 0>;
3376 qcom,smem-state-names = "stop";
3380 glink-edge {
3383 qcom,remote-pid = <3>;
3388 qcom,glink-channels = "fastrpcglink-apps-dsp";
3390 qcom,non-secure-domain;
3393 memory-region = <&fastrpc_mem>;
3394 #address-cells = <1>;
3395 #size-cells = <0>;
3397 compute-cb@0 {
3398 compatible = "qcom,fastrpc-compute-cb";
3406 compatible = "arm,coresight-stm", "arm,primecell";
3409 reg-names = "stm-base", "stm-stimulus-base";
3412 clock-names = "apb_pclk";
3414 out-ports {
3417 remote-endpoint =
3425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3429 clock-names = "apb_pclk";
3431 out-ports {
3434 remote-endpoint =
3440 in-ports {
3441 #address-cells = <1>;
3442 #size-cells = <0>;
3447 remote-endpoint = <&stm_out>;
3454 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3458 clock-names = "apb_pclk";
3460 out-ports {
3463 remote-endpoint =
3469 in-ports {
3470 #address-cells = <1>;
3471 #size-cells = <0>;
3476 remote-endpoint =
3484 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3488 clock-names = "apb_pclk";
3490 out-ports {
3493 remote-endpoint = <&etf_in>;
3498 in-ports {
3499 #address-cells = <1>;
3500 #size-cells = <0>;
3505 remote-endpoint =
3513 remote-endpoint =
3521 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3525 clock-names = "apb_pclk";
3527 out-ports {
3530 remote-endpoint = <&etr_in>;
3535 in-ports {
3538 remote-endpoint = <&etf_out>;
3545 compatible = "arm,coresight-tmc", "arm,primecell";
3549 clock-names = "apb_pclk";
3551 out-ports {
3554 remote-endpoint =
3560 in-ports {
3564 remote-endpoint =
3572 compatible = "arm,coresight-tmc", "arm,primecell";
3576 clock-names = "apb_pclk";
3577 arm,scatter-gather;
3579 in-ports {
3582 remote-endpoint =
3590 compatible = "arm,coresight-etm4x", "arm,primecell";
3596 clock-names = "apb_pclk";
3597 arm,coresight-loses-context-with-cpu;
3599 out-ports {
3602 remote-endpoint =
3610 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 clock-names = "apb_pclk";
3617 arm,coresight-loses-context-with-cpu;
3619 out-ports {
3622 remote-endpoint =
3630 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 clock-names = "apb_pclk";
3637 arm,coresight-loses-context-with-cpu;
3639 out-ports {
3642 remote-endpoint =
3650 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 clock-names = "apb_pclk";
3657 arm,coresight-loses-context-with-cpu;
3659 out-ports {
3662 remote-endpoint =
3670 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 clock-names = "apb_pclk";
3677 arm,coresight-loses-context-with-cpu;
3679 out-ports {
3682 remote-endpoint =
3690 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 clock-names = "apb_pclk";
3697 arm,coresight-loses-context-with-cpu;
3699 out-ports {
3702 remote-endpoint =
3710 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 clock-names = "apb_pclk";
3717 arm,coresight-loses-context-with-cpu;
3719 out-ports {
3722 remote-endpoint =
3730 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 clock-names = "apb_pclk";
3737 arm,coresight-loses-context-with-cpu;
3739 out-ports {
3742 remote-endpoint =
3750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3754 clock-names = "apb_pclk";
3756 out-ports {
3759 remote-endpoint =
3765 in-ports {
3766 #address-cells = <1>;
3767 #size-cells = <0>;
3772 remote-endpoint =
3780 remote-endpoint =
3788 remote-endpoint =
3796 remote-endpoint =
3804 remote-endpoint =
3812 remote-endpoint =
3820 remote-endpoint =
3828 remote-endpoint =
3836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3840 clock-names = "apb_pclk";
3842 out-ports {
3845 remote-endpoint =
3851 in-ports {
3854 remote-endpoint =
3862 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3867 interrupt-names = "hc_irq", "pwr_irq";
3872 clock-names = "iface", "core", "xo";
3874 power-domains = <&rpmhpd SDM845_CX>;
3875 operating-points-v2 = <&sdhc2_opp_table>;
3879 sdhc2_opp_table: opp-table {
3880 compatible = "operating-points-v2";
3882 opp-9600000 {
3883 opp-hz = /bits/ 64 <9600000>;
3884 required-opps = <&rpmhpd_opp_min_svs>;
3887 opp-19200000 {
3888 opp-hz = /bits/ 64 <19200000>;
3889 required-opps = <&rpmhpd_opp_low_svs>;
3892 opp-100000000 {
3893 opp-hz = /bits/ 64 <100000000>;
3894 required-opps = <&rpmhpd_opp_svs>;
3897 opp-201500000 {
3898 opp-hz = /bits/ 64 <201500000>;
3899 required-opps = <&rpmhpd_opp_svs_l1>;
3905 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3908 #address-cells = <1>;
3909 #size-cells = <0>;
3913 clock-names = "iface", "core";
3914 power-domains = <&rpmhpd SDM845_CX>;
3915 operating-points-v2 = <&qspi_opp_table>;
3919 slim: slim-ngd@171c0000 {
3920 compatible = "qcom,slim-ngd-v2.1.0";
3925 dma-names = "rx", "tx";
3928 #address-cells = <1>;
3929 #size-cells = <0>;
3934 compatible = "qcom,sdm845-lmh";
3938 qcom,lmh-temp-arm-millicelsius = <65000>;
3939 qcom,lmh-temp-low-millicelsius = <94500>;
3940 qcom,lmh-temp-high-millicelsius = <95000>;
3941 interrupt-controller;
3942 #interrupt-cells = <1>;
3946 compatible = "qcom,sdm845-lmh";
3950 qcom,lmh-temp-arm-millicelsius = <65000>;
3951 qcom,lmh-temp-low-millicelsius = <94500>;
3952 qcom,lmh-temp-high-millicelsius = <95000>;
3953 interrupt-controller;
3954 #interrupt-cells = <1>;
3958 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3961 #phy-cells = <0>;
3965 clock-names = "cfg_ahb", "ref";
3969 nvmem-cells = <&qusb2p_hstx_trim>;
3973 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3976 #phy-cells = <0>;
3980 clock-names = "cfg_ahb", "ref";
3984 nvmem-cells = <&qusb2s_hstx_trim>;
3988 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
3997 clock-names = "aux",
4005 reset-names = "phy", "common";
4007 #clock-cells = <1>;
4008 #phy-cells = <1>;
4012 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4020 clock-names = "aux",
4025 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4026 #clock-cells = <0>;
4027 #phy-cells = <0>;
4031 reset-names = "phy",
4038 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4041 #address-cells = <2>;
4042 #size-cells = <2>;
4044 dma-ranges;
4051 clock-names = "cfg_noc",
4057 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4059 assigned-clock-rates = <19200000>, <150000000>;
4061 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4065 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4068 power-domains = <&gcc USB30_PRIM_GDSC>;
4074 interconnect-names = "usb-ddr", "apps-usb";
4084 phy-names = "usb2-phy", "usb3-phy";
4089 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4092 #address-cells = <2>;
4093 #size-cells = <2>;
4095 dma-ranges;
4102 clock-names = "cfg_noc",
4108 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4110 assigned-clock-rates = <19200000>, <150000000>;
4112 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4116 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4119 power-domains = <&gcc USB30_SEC_GDSC>;
4125 interconnect-names = "usb-ddr", "apps-usb";
4135 phy-names = "usb2-phy", "usb3-phy";
4139 venus: video-codec@aa00000 {
4140 compatible = "qcom,sdm845-venus-v2";
4143 power-domains = <&videocc VENUS_GDSC>,
4144 <&videocc VCODEC0_GDSC>,
4145 <&videocc VCODEC1_GDSC>,
4147 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4148 operating-points-v2 = <&venus_opp_table>;
4149 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4150 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4151 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4152 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4153 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4154 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4155 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4156 clock-names = "core", "iface", "bus",
4161 memory-region = <&venus_mem>;
4164 interconnect-names = "video-mem", "cpu-cfg";
4168 video-core0 {
4169 compatible = "venus-decoder";
4172 video-core1 {
4173 compatible = "venus-encoder";
4176 venus_opp_table: opp-table {
4177 compatible = "operating-points-v2";
4179 opp-100000000 {
4180 opp-hz = /bits/ 64 <100000000>;
4181 required-opps = <&rpmhpd_opp_min_svs>;
4184 opp-200000000 {
4185 opp-hz = /bits/ 64 <200000000>;
4186 required-opps = <&rpmhpd_opp_low_svs>;
4189 opp-320000000 {
4190 opp-hz = /bits/ 64 <320000000>;
4191 required-opps = <&rpmhpd_opp_svs>;
4194 opp-380000000 {
4195 opp-hz = /bits/ 64 <380000000>;
4196 required-opps = <&rpmhpd_opp_svs_l1>;
4199 opp-444000000 {
4200 opp-hz = /bits/ 64 <444000000>;
4201 required-opps = <&rpmhpd_opp_nom>;
4204 opp-533000097 {
4205 opp-hz = /bits/ 64 <533000097>;
4206 required-opps = <&rpmhpd_opp_turbo>;
4211 videocc: clock-controller@ab00000 {
4212 compatible = "qcom,sdm845-videocc";
4215 clock-names = "bi_tcxo";
4216 #clock-cells = <1>;
4217 #power-domain-cells = <1>;
4218 #reset-cells = <1>;
4222 compatible = "qcom,sdm845-camss";
4234 reg-names = "csid0",
4255 interrupt-names = "csid0",
4266 power-domains = <&clock_camcc IFE_0_GDSC>,
4306 clock-names = "camnoc_axi",
4351 #address-cells = <1>;
4352 #size-cells = <0>;
4373 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4374 #address-cells = <1>;
4375 #size-cells = <0>;
4379 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4387 clock-names = "camnoc_axi",
4394 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4396 assigned-clock-rates = <80000000>, <37500000>;
4398 pinctrl-names = "default", "sleep";
4399 pinctrl-0 = <&cci0_default &cci1_default>;
4400 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4404 cci_i2c0: i2c-bus@0 {
4406 clock-frequency = <1000000>;
4407 #address-cells = <1>;
4408 #size-cells = <0>;
4411 cci_i2c1: i2c-bus@1 {
4413 clock-frequency = <1000000>;
4414 #address-cells = <1>;
4415 #size-cells = <0>;
4419 clock_camcc: clock-controller@ad00000 {
4420 compatible = "qcom,sdm845-camcc";
4422 #clock-cells = <1>;
4423 #reset-cells = <1>;
4424 #power-domain-cells = <1>;
4426 clock-names = "bi_tcxo";
4429 mdss: display-subsystem@ae00000 {
4430 compatible = "qcom,sdm845-mdss";
4432 reg-names = "mdss";
4434 power-domains = <&dispcc MDSS_GDSC>;
4438 clock-names = "iface", "core";
4441 interrupt-controller;
4442 #interrupt-cells = <1>;
4446 interconnect-names = "mdp0-mem", "mdp1-mem";
4453 #address-cells = <2>;
4454 #size-cells = <2>;
4457 mdss_mdp: display-controller@ae01000 {
4458 compatible = "qcom,sdm845-dpu";
4461 reg-names = "mdp", "vbif";
4468 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4470 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4471 assigned-clock-rates = <19200000>;
4472 operating-points-v2 = <&mdp_opp_table>;
4473 power-domains = <&rpmhpd SDM845_CX>;
4475 interrupt-parent = <&mdss>;
4479 #address-cells = <1>;
4480 #size-cells = <0>;
4485 remote-endpoint = <&dp_in>;
4492 remote-endpoint = <&mdss_dsi0_in>;
4499 remote-endpoint = <&mdss_dsi1_in>;
4504 mdp_opp_table: opp-table {
4505 compatible = "operating-points-v2";
4507 opp-19200000 {
4508 opp-hz = /bits/ 64 <19200000>;
4509 required-opps = <&rpmhpd_opp_min_svs>;
4512 opp-171428571 {
4513 opp-hz = /bits/ 64 <171428571>;
4514 required-opps = <&rpmhpd_opp_low_svs>;
4517 opp-344000000 {
4518 opp-hz = /bits/ 64 <344000000>;
4519 required-opps = <&rpmhpd_opp_svs_l1>;
4522 opp-430000000 {
4523 opp-hz = /bits/ 64 <430000000>;
4524 required-opps = <&rpmhpd_opp_nom>;
4529 mdss_dp: displayport-controller@ae90000 {
4531 compatible = "qcom,sdm845-dp";
4539 interrupt-parent = <&mdss>;
4547 clock-names = "core_iface", "core_aux", "ctrl_link",
4549 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4551 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4554 phy-names = "dp";
4556 operating-points-v2 = <&dp_opp_table>;
4557 power-domains = <&rpmhpd SDM845_CX>;
4560 #address-cells = <1>;
4561 #size-cells = <0>;
4565 remote-endpoint = <&dpu_intf0_out>;
4575 dp_opp_table: opp-table {
4576 compatible = "operating-points-v2";
4578 opp-162000000 {
4579 opp-hz = /bits/ 64 <162000000>;
4580 required-opps = <&rpmhpd_opp_low_svs>;
4583 opp-270000000 {
4584 opp-hz = /bits/ 64 <270000000>;
4585 required-opps = <&rpmhpd_opp_svs>;
4588 opp-540000000 {
4589 opp-hz = /bits/ 64 <540000000>;
4590 required-opps = <&rpmhpd_opp_svs_l1>;
4593 opp-810000000 {
4594 opp-hz = /bits/ 64 <810000000>;
4595 required-opps = <&rpmhpd_opp_nom>;
4601 compatible = "qcom,sdm845-dsi-ctrl",
4602 "qcom,mdss-dsi-ctrl";
4604 reg-names = "dsi_ctrl";
4606 interrupt-parent = <&mdss>;
4615 clock-names = "byte",
4621 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4622 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4624 operating-points-v2 = <&dsi_opp_table>;
4625 power-domains = <&rpmhpd SDM845_CX>;
4631 #address-cells = <1>;
4632 #size-cells = <0>;
4635 #address-cells = <1>;
4636 #size-cells = <0>;
4641 remote-endpoint = <&dpu_intf1_out>;
4654 compatible = "qcom,dsi-phy-10nm";
4658 reg-names = "dsi_phy",
4662 #clock-cells = <1>;
4663 #phy-cells = <0>;
4667 clock-names = "iface", "ref";
4673 compatible = "qcom,sdm845-dsi-ctrl",
4674 "qcom,mdss-dsi-ctrl";
4676 reg-names = "dsi_ctrl";
4678 interrupt-parent = <&mdss>;
4687 clock-names = "byte",
4693 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4694 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4696 operating-points-v2 = <&dsi_opp_table>;
4697 power-domains = <&rpmhpd SDM845_CX>;
4703 #address-cells = <1>;
4704 #size-cells = <0>;
4707 #address-cells = <1>;
4708 #size-cells = <0>;
4713 remote-endpoint = <&dpu_intf2_out>;
4726 compatible = "qcom,dsi-phy-10nm";
4730 reg-names = "dsi_phy",
4734 #clock-cells = <1>;
4735 #phy-cells = <0>;
4739 clock-names = "iface", "ref";
4746 compatible = "qcom,adreno-630.2", "qcom,adreno";
4749 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4760 operating-points-v2 = <&gpu_opp_table>;
4765 interconnect-names = "gfx-mem";
4769 gpu_opp_table: opp-table {
4770 compatible = "operating-points-v2";
4772 opp-710000000 {
4773 opp-hz = /bits/ 64 <710000000>;
4774 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4775 opp-peak-kBps = <7216000>;
4778 opp-675000000 {
4779 opp-hz = /bits/ 64 <675000000>;
4780 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4781 opp-peak-kBps = <7216000>;
4784 opp-596000000 {
4785 opp-hz = /bits/ 64 <596000000>;
4786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4787 opp-peak-kBps = <6220000>;
4790 opp-520000000 {
4791 opp-hz = /bits/ 64 <520000000>;
4792 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4793 opp-peak-kBps = <6220000>;
4796 opp-414000000 {
4797 opp-hz = /bits/ 64 <414000000>;
4798 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4799 opp-peak-kBps = <4068000>;
4802 opp-342000000 {
4803 opp-hz = /bits/ 64 <342000000>;
4804 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4805 opp-peak-kBps = <2724000>;
4808 opp-257000000 {
4809 opp-hz = /bits/ 64 <257000000>;
4810 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4811 opp-peak-kBps = <1648000>;
4817 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4819 #iommu-cells = <1>;
4820 #global-interrupts = <2>;
4833 clock-names = "bus", "iface";
4835 power-domains = <&gpucc GPU_CX_GDSC>;
4839 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4844 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4848 interrupt-names = "hfi", "gmu";
4854 clock-names = "gmu", "cxo", "axi", "memnoc";
4856 power-domains = <&gpucc GPU_CX_GDSC>,
4858 power-domain-names = "cx", "gx";
4862 operating-points-v2 = <&gmu_opp_table>;
4866 gmu_opp_table: opp-table {
4867 compatible = "operating-points-v2";
4869 opp-400000000 {
4870 opp-hz = /bits/ 64 <400000000>;
4871 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4874 opp-200000000 {
4875 opp-hz = /bits/ 64 <200000000>;
4876 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4881 dispcc: clock-controller@af00000 {
4882 compatible = "qcom,sdm845-dispcc";
4893 clock-names = "bi_tcxo",
4902 #clock-cells = <1>;
4903 #reset-cells = <1>;
4904 #power-domain-cells = <1>;
4907 pdc_intc: interrupt-controller@b220000 {
4908 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4910 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4911 #interrupt-cells = <2>;
4912 interrupt-parent = <&intc>;
4913 interrupt-controller;
4916 pdc_reset: reset-controller@b2e0000 {
4917 compatible = "qcom,sdm845-pdc-global";
4919 #reset-cells = <1>;
4922 tsens0: thermal-sensor@c263000 {
4923 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4929 interrupt-names = "uplow", "critical";
4930 #thermal-sensor-cells = <1>;
4933 tsens1: thermal-sensor@c265000 {
4934 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4940 interrupt-names = "uplow", "critical";
4941 #thermal-sensor-cells = <1>;
4944 aoss_reset: reset-controller@c2a0000 {
4945 compatible = "qcom,sdm845-aoss-cc";
4947 #reset-cells = <1>;
4950 aoss_qmp: power-management@c300000 {
4951 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4956 #clock-cells = <0>;
4959 #cooling-cells = <2>;
4963 #cooling-cells = <2>;
4968 compatible = "qcom,sdm845-rpmh-stats";
4973 compatible = "qcom,spmi-pmic-arb";
4979 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4980 interrupt-names = "periph_irq";
4984 #address-cells = <2>;
4985 #size-cells = <0>;
4986 interrupt-controller;
4987 #interrupt-cells = <4>;
4991 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
4994 #address-cells = <1>;
4995 #size-cells = <1>;
4999 pil-reloc@94c {
5000 compatible = "qcom,pil-reloc-info";
5006 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5008 #iommu-cells = <2>;
5009 #global-interrupts = <1>;
5077 lpasscc: clock-controller@17014000 {
5078 compatible = "qcom,sdm845-lpasscc";
5080 reg-names = "cc", "qdsp6ss";
5081 #clock-cells = <1>;
5086 compatible = "qcom,sdm845-gladiator-noc";
5088 #interconnect-cells = <2>;
5089 qcom,bcm-voters = <&apps_bcm_voter>;
5093 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5100 compatible = "qcom,sdm845-apss-shared";
5102 #mbox-cells = <1>;
5107 compatible = "qcom,rpmh-rsc";
5111 reg-names = "drv-0", "drv-1", "drv-2";
5115 qcom,tcs-offset = <0xd00>;
5116 qcom,drv-id = <2>;
5117 qcom,tcs-config = <ACTIVE_TCS 2>,
5121 power-domains = <&CLUSTER_PD>;
5123 apps_bcm_voter: bcm-voter {
5124 compatible = "qcom,bcm-voter";
5127 rpmhcc: clock-controller {
5128 compatible = "qcom,sdm845-rpmh-clk";
5129 #clock-cells = <1>;
5130 clock-names = "xo";
5134 rpmhpd: power-controller {
5135 compatible = "qcom,sdm845-rpmhpd";
5136 #power-domain-cells = <1>;
5137 operating-points-v2 = <&rpmhpd_opp_table>;
5139 rpmhpd_opp_table: opp-table {
5140 compatible = "operating-points-v2";
5143 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5147 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5151 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5155 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5159 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5163 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5167 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5171 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5175 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5179 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5185 intc: interrupt-controller@17a00000 {
5186 compatible = "arm,gic-v3";
5187 #address-cells = <2>;
5188 #size-cells = <2>;
5190 #interrupt-cells = <3>;
5191 interrupt-controller;
5196 msi-controller@17a40000 {
5197 compatible = "arm,gic-v3-its";
5198 msi-controller;
5199 #msi-cells = <1>;
5205 slimbam: dma-controller@17184000 {
5206 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5207 qcom,controlled-remotely;
5209 num-channels = <31>;
5211 #dma-cells = <1>;
5213 qcom,num-ees = <2>;
5218 #address-cells = <1>;
5219 #size-cells = <1>;
5221 compatible = "arm,armv7-timer-mem";
5225 frame-number = <0>;
5233 frame-number = <1>;
5240 frame-number = <2>;
5247 frame-number = <3>;
5254 frame-number = <4>;
5261 frame-number = <5>;
5268 frame-number = <6>;
5276 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5280 clock-names = "xo", "alternate";
5282 #interconnect-cells = <1>;
5286 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5288 reg-names = "freq-domain0", "freq-domain1";
5290 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5293 clock-names = "xo", "alternate";
5295 #freq-domain-cells = <1>;
5296 #clock-cells = <1>;
5300 compatible = "qcom,wcn3990-wifi";
5303 reg-names = "membase";
5304 memory-region = <&wlan_msa_mem>;
5305 clock-names = "cxo_ref_clk_pin";
5327 thermal-zones {
5328 cpu0-thermal {
5329 polling-delay-passive = <250>;
5330 polling-delay = <1000>;
5332 thermal-sensors = <&tsens0 1>;
5335 cpu0_alert0: trip-point0 {
5341 cpu0_alert1: trip-point1 {
5347 cpu0_crit: cpu-crit {
5355 cpu1-thermal {
5356 polling-delay-passive = <250>;
5357 polling-delay = <1000>;
5359 thermal-sensors = <&tsens0 2>;
5362 cpu1_alert0: trip-point0 {
5368 cpu1_alert1: trip-point1 {
5374 cpu1_crit: cpu-crit {
5382 cpu2-thermal {
5383 polling-delay-passive = <250>;
5384 polling-delay = <1000>;
5386 thermal-sensors = <&tsens0 3>;
5389 cpu2_alert0: trip-point0 {
5395 cpu2_alert1: trip-point1 {
5401 cpu2_crit: cpu-crit {
5409 cpu3-thermal {
5410 polling-delay-passive = <250>;
5411 polling-delay = <1000>;
5413 thermal-sensors = <&tsens0 4>;
5416 cpu3_alert0: trip-point0 {
5422 cpu3_alert1: trip-point1 {
5428 cpu3_crit: cpu-crit {
5436 cpu4-thermal {
5437 polling-delay-passive = <250>;
5438 polling-delay = <1000>;
5440 thermal-sensors = <&tsens0 7>;
5443 cpu4_alert0: trip-point0 {
5449 cpu4_alert1: trip-point1 {
5455 cpu4_crit: cpu-crit {
5463 cpu5-thermal {
5464 polling-delay-passive = <250>;
5465 polling-delay = <1000>;
5467 thermal-sensors = <&tsens0 8>;
5470 cpu5_alert0: trip-point0 {
5476 cpu5_alert1: trip-point1 {
5482 cpu5_crit: cpu-crit {
5490 cpu6-thermal {
5491 polling-delay-passive = <250>;
5492 polling-delay = <1000>;
5494 thermal-sensors = <&tsens0 9>;
5497 cpu6_alert0: trip-point0 {
5503 cpu6_alert1: trip-point1 {
5509 cpu6_crit: cpu-crit {
5517 cpu7-thermal {
5518 polling-delay-passive = <250>;
5519 polling-delay = <1000>;
5521 thermal-sensors = <&tsens0 10>;
5524 cpu7_alert0: trip-point0 {
5530 cpu7_alert1: trip-point1 {
5536 cpu7_crit: cpu-crit {
5544 aoss0-thermal {
5545 polling-delay-passive = <250>;
5546 polling-delay = <1000>;
5548 thermal-sensors = <&tsens0 0>;
5551 aoss0_alert0: trip-point0 {
5559 cluster0-thermal {
5560 polling-delay-passive = <250>;
5561 polling-delay = <1000>;
5563 thermal-sensors = <&tsens0 5>;
5566 cluster0_alert0: trip-point0 {
5579 cluster1-thermal {
5580 polling-delay-passive = <250>;
5581 polling-delay = <1000>;
5583 thermal-sensors = <&tsens0 6>;
5586 cluster1_alert0: trip-point0 {
5599 gpu-top-thermal {
5600 polling-delay-passive = <250>;
5601 polling-delay = <1000>;
5603 thermal-sensors = <&tsens0 11>;
5606 gpu1_alert0: trip-point0 {
5614 gpu-bottom-thermal {
5615 polling-delay-passive = <250>;
5616 polling-delay = <1000>;
5618 thermal-sensors = <&tsens0 12>;
5621 gpu2_alert0: trip-point0 {
5629 aoss1-thermal {
5630 polling-delay-passive = <250>;
5631 polling-delay = <1000>;
5633 thermal-sensors = <&tsens1 0>;
5636 aoss1_alert0: trip-point0 {
5644 q6-modem-thermal {
5645 polling-delay-passive = <250>;
5646 polling-delay = <1000>;
5648 thermal-sensors = <&tsens1 1>;
5651 q6_modem_alert0: trip-point0 {
5659 mem-thermal {
5660 polling-delay-passive = <250>;
5661 polling-delay = <1000>;
5663 thermal-sensors = <&tsens1 2>;
5666 mem_alert0: trip-point0 {
5674 wlan-thermal {
5675 polling-delay-passive = <250>;
5676 polling-delay = <1000>;
5678 thermal-sensors = <&tsens1 3>;
5681 wlan_alert0: trip-point0 {
5689 q6-hvx-thermal {
5690 polling-delay-passive = <250>;
5691 polling-delay = <1000>;
5693 thermal-sensors = <&tsens1 4>;
5696 q6_hvx_alert0: trip-point0 {
5704 camera-thermal {
5705 polling-delay-passive = <250>;
5706 polling-delay = <1000>;
5708 thermal-sensors = <&tsens1 5>;
5711 camera_alert0: trip-point0 {
5719 video-thermal {
5720 polling-delay-passive = <250>;
5721 polling-delay = <1000>;
5723 thermal-sensors = <&tsens1 6>;
5726 video_alert0: trip-point0 {
5734 modem-thermal {
5735 polling-delay-passive = <250>;
5736 polling-delay = <1000>;
5738 thermal-sensors = <&tsens1 7>;
5741 modem_alert0: trip-point0 {
5751 compatible = "arm,armv8-timer";