Lines Matching +full:0 +full:x010a2000
77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
149 reg = <0x0 0x200>;
150 clocks = <&cpufreq_hw 0>;
154 qcom,freq-domain = <&cpufreq_hw 0>;
173 reg = <0x0 0x300>;
174 clocks = <&cpufreq_hw 0>;
178 qcom,freq-domain = <&cpufreq_hw 0>;
197 reg = <0x0 0x400>;
221 reg = <0x0 0x500>;
245 reg = <0x0 0x600>;
269 reg = <0x0 0x700>;
329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
332 arm,psci-suspend-param = <0x40000004>;
339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
342 arm,psci-suspend-param = <0x40000004>;
351 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 arm,psci-suspend-param = <0x4100c244>;
370 reg = <0 0x80000000 0 0>;
720 #power-domain-cells = <0>;
726 #power-domain-cells = <0>;
732 #power-domain-cells = <0>;
738 #power-domain-cells = <0>;
744 #power-domain-cells = <0>;
750 #power-domain-cells = <0>;
756 #power-domain-cells = <0>;
762 #power-domain-cells = <0>;
768 #power-domain-cells = <0>;
779 reg = <0 0x85700000 0 0x600000>;
784 reg = <0 0x85e00000 0 0x100000>;
789 reg = <0 0x85fc0000 0 0x20000>;
795 reg = <0x0 0x85fe0000 0 0x20000>;
801 reg = <0x0 0x86000000 0 0x200000>;
807 reg = <0 0x86200000 0 0x2d00000>;
813 reg = <0 0x88f00000 0 0x200000>;
821 reg = <0 0x8ab00000 0 0x1400000>;
826 reg = <0 0x8bf00000 0 0x500000>;
831 reg = <0 0x8c400000 0 0x10000>;
836 reg = <0 0x8c410000 0 0x5000>;
841 reg = <0 0x8c415000 0 0x2000>;
846 reg = <0 0x8c500000 0 0x1a00000>;
851 reg = <0 0x8df00000 0 0x100000>;
856 reg = <0 0x8e000000 0 0x7800000>;
861 reg = <0 0x95800000 0 0x500000>;
866 reg = <0 0x95d00000 0 0x800000>;
871 reg = <0 0x96500000 0 0x200000>;
876 reg = <0 0x96700000 0 0x1400000>;
881 reg = <0 0x97b00000 0 0x100000>;
886 alloc-ranges = <0 0xa0000000 0 0x20000000>;
887 size = <0 0x4000>;
893 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
894 alignment = <0x0 0x400000>;
895 size = <0x0 0x1000000>;
904 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
918 qcom,smem-states = <&adsp_smp2p_out 0>;
934 #size-cells = <0>;
950 #size-cells = <0>;
962 #size-cells = <0>;
964 iommus = <&apps_smmu 0x1821 0x0>;
974 #sound-dai-cells = <0>;
985 #size-cells = <0>;
990 iommus = <&apps_smmu 0x1823 0x0>;
996 iommus = <&apps_smmu 0x1824 0x0>;
1006 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1020 qcom,smem-states = <&cdsp_smp2p_out 0>;
1036 #size-cells = <0>;
1041 iommus = <&apps_smmu 0x1401 0x30>;
1047 iommus = <&apps_smmu 0x1402 0x30>;
1053 iommus = <&apps_smmu 0x1403 0x30>;
1059 iommus = <&apps_smmu 0x1404 0x30>;
1065 iommus = <&apps_smmu 0x1405 0x30>;
1071 iommus = <&apps_smmu 0x1406 0x30>;
1077 iommus = <&apps_smmu 0x1407 0x30>;
1083 iommus = <&apps_smmu 0x1408 0x30>;
1097 qcom,local-pid = <0>;
1121 qcom,local-pid = <0>;
1142 qcom,local-pid = <0>;
1173 qcom,local-pid = <0>;
1188 soc: soc@0 {
1191 ranges = <0 0 0 0 0x10 0>;
1192 dma-ranges = <0 0 0 0 0x10 0>;
1197 reg = <0 0x00100000 0 0x1f0000>;
1216 reg = <0 0x00784000 0 0x8ff>;
1221 reg = <0x1eb 0x1>;
1226 reg = <0x1eb 0x2>;
1233 reg = <0 0x00793000 0 0x1000>;
1241 reg = <0 0x00800000 0 0x60000>;
1256 dma-channel-mask = <0xfa>;
1257 iommus = <&apps_smmu 0x0016 0x0>;
1263 reg = <0 0x008c0000 0 0x6000>;
1267 iommus = <&apps_smmu 0x3 0x0>;
1271 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1277 reg = <0 0x00880000 0 0x4000>;
1281 pinctrl-0 = <&qup_i2c0_default>;
1284 #size-cells = <0>;
1287 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1288 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1289 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1292 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1299 reg = <0 0x00880000 0 0x4000>;
1303 pinctrl-0 = <&qup_spi0_default>;
1306 #size-cells = <0>;
1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1311 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1318 reg = <0 0x00880000 0 0x4000>;
1322 pinctrl-0 = <&qup_uart0_default>;
1326 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1327 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1334 reg = <0 0x00884000 0 0x4000>;
1338 pinctrl-0 = <&qup_i2c1_default>;
1341 #size-cells = <0>;
1344 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1345 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1346 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1356 reg = <0 0x00884000 0 0x4000>;
1360 pinctrl-0 = <&qup_spi1_default>;
1363 #size-cells = <0>;
1364 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1365 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1375 reg = <0 0x00884000 0 0x4000>;
1379 pinctrl-0 = <&qup_uart1_default>;
1383 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1384 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1391 reg = <0 0x00888000 0 0x4000>;
1395 pinctrl-0 = <&qup_i2c2_default>;
1398 #size-cells = <0>;
1401 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1402 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1403 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1413 reg = <0 0x00888000 0 0x4000>;
1417 pinctrl-0 = <&qup_spi2_default>;
1420 #size-cells = <0>;
1421 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1422 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1432 reg = <0 0x00888000 0 0x4000>;
1436 pinctrl-0 = <&qup_uart2_default>;
1440 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1441 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1448 reg = <0 0x0088c000 0 0x4000>;
1452 pinctrl-0 = <&qup_i2c3_default>;
1455 #size-cells = <0>;
1458 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1459 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1460 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1470 reg = <0 0x0088c000 0 0x4000>;
1474 pinctrl-0 = <&qup_spi3_default>;
1477 #size-cells = <0>;
1478 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1479 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1489 reg = <0 0x0088c000 0 0x4000>;
1493 pinctrl-0 = <&qup_uart3_default>;
1497 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1498 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1505 reg = <0 0x00890000 0 0x4000>;
1509 pinctrl-0 = <&qup_i2c4_default>;
1512 #size-cells = <0>;
1515 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1516 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1517 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1527 reg = <0 0x00890000 0 0x4000>;
1531 pinctrl-0 = <&qup_spi4_default>;
1534 #size-cells = <0>;
1535 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1536 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1546 reg = <0 0x00890000 0 0x4000>;
1550 pinctrl-0 = <&qup_uart4_default>;
1554 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1555 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1562 reg = <0 0x00894000 0 0x4000>;
1566 pinctrl-0 = <&qup_i2c5_default>;
1569 #size-cells = <0>;
1572 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1574 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1584 reg = <0 0x00894000 0 0x4000>;
1588 pinctrl-0 = <&qup_spi5_default>;
1591 #size-cells = <0>;
1592 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1593 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1603 reg = <0 0x00894000 0 0x4000>;
1607 pinctrl-0 = <&qup_uart5_default>;
1611 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1612 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1619 reg = <0 0x00898000 0 0x4000>;
1623 pinctrl-0 = <&qup_i2c6_default>;
1626 #size-cells = <0>;
1629 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1630 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1631 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1641 reg = <0 0x00898000 0 0x4000>;
1645 pinctrl-0 = <&qup_spi6_default>;
1648 #size-cells = <0>;
1649 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1650 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1660 reg = <0 0x00898000 0 0x4000>;
1664 pinctrl-0 = <&qup_uart6_default>;
1668 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1669 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1676 reg = <0 0x0089c000 0 0x4000>;
1680 pinctrl-0 = <&qup_i2c7_default>;
1683 #size-cells = <0>;
1691 reg = <0 0x0089c000 0 0x4000>;
1695 pinctrl-0 = <&qup_spi7_default>;
1698 #size-cells = <0>;
1699 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1700 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1710 reg = <0 0x0089c000 0 0x4000>;
1714 pinctrl-0 = <&qup_uart7_default>;
1718 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1719 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1728 reg = <0 0x00a00000 0 0x60000>;
1743 dma-channel-mask = <0xfa>;
1744 iommus = <&apps_smmu 0x06d6 0x0>;
1750 reg = <0 0x00ac0000 0 0x6000>;
1754 iommus = <&apps_smmu 0x6c3 0x0>;
1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1764 reg = <0 0x00a80000 0 0x4000>;
1768 pinctrl-0 = <&qup_i2c8_default>;
1771 #size-cells = <0>;
1774 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1775 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1776 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1779 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1786 reg = <0 0x00a80000 0 0x4000>;
1790 pinctrl-0 = <&qup_spi8_default>;
1793 #size-cells = <0>;
1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1798 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1805 reg = <0 0x00a80000 0 0x4000>;
1809 pinctrl-0 = <&qup_uart8_default>;
1813 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1814 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1821 reg = <0 0x00a84000 0 0x4000>;
1825 pinctrl-0 = <&qup_i2c9_default>;
1828 #size-cells = <0>;
1831 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1832 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1833 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1843 reg = <0 0x00a84000 0 0x4000>;
1847 pinctrl-0 = <&qup_spi9_default>;
1850 #size-cells = <0>;
1851 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1852 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1862 reg = <0 0x00a84000 0 0x4000>;
1866 pinctrl-0 = <&qup_uart9_default>;
1870 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1871 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1878 reg = <0 0x00a88000 0 0x4000>;
1882 pinctrl-0 = <&qup_i2c10_default>;
1885 #size-cells = <0>;
1888 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1889 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1890 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1900 reg = <0 0x00a88000 0 0x4000>;
1904 pinctrl-0 = <&qup_spi10_default>;
1907 #size-cells = <0>;
1908 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1909 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1919 reg = <0 0x00a88000 0 0x4000>;
1923 pinctrl-0 = <&qup_uart10_default>;
1927 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1928 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1935 reg = <0 0x00a8c000 0 0x4000>;
1939 pinctrl-0 = <&qup_i2c11_default>;
1942 #size-cells = <0>;
1945 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1946 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1947 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1957 reg = <0 0x00a8c000 0 0x4000>;
1961 pinctrl-0 = <&qup_spi11_default>;
1964 #size-cells = <0>;
1965 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1966 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1976 reg = <0 0x00a8c000 0 0x4000>;
1980 pinctrl-0 = <&qup_uart11_default>;
1984 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1985 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1992 reg = <0 0x00a90000 0 0x4000>;
1996 pinctrl-0 = <&qup_i2c12_default>;
1999 #size-cells = <0>;
2002 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2003 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2004 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2014 reg = <0 0x00a90000 0 0x4000>;
2018 pinctrl-0 = <&qup_spi12_default>;
2021 #size-cells = <0>;
2022 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2023 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2033 reg = <0 0x00a90000 0 0x4000>;
2037 pinctrl-0 = <&qup_uart12_default>;
2041 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2042 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2049 reg = <0 0x00a94000 0 0x4000>;
2053 pinctrl-0 = <&qup_i2c13_default>;
2056 #size-cells = <0>;
2059 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2060 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2061 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2071 reg = <0 0x00a94000 0 0x4000>;
2075 pinctrl-0 = <&qup_spi13_default>;
2078 #size-cells = <0>;
2079 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2080 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2090 reg = <0 0x00a94000 0 0x4000>;
2094 pinctrl-0 = <&qup_uart13_default>;
2098 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2106 reg = <0 0x00a98000 0 0x4000>;
2110 pinctrl-0 = <&qup_i2c14_default>;
2113 #size-cells = <0>;
2116 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2117 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2118 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2128 reg = <0 0x00a98000 0 0x4000>;
2132 pinctrl-0 = <&qup_spi14_default>;
2135 #size-cells = <0>;
2136 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2137 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2147 reg = <0 0x00a98000 0 0x4000>;
2151 pinctrl-0 = <&qup_uart14_default>;
2155 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2156 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2163 reg = <0 0x00a9c000 0 0x4000>;
2167 pinctrl-0 = <&qup_i2c15_default>;
2170 #size-cells = <0>;
2174 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2175 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2176 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2185 reg = <0 0x00a9c000 0 0x4000>;
2189 pinctrl-0 = <&qup_spi15_default>;
2192 #size-cells = <0>;
2193 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2194 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2204 reg = <0 0x00a9c000 0 0x4000>;
2208 pinctrl-0 = <&qup_uart15_default>;
2212 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2213 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2221 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2222 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2223 <0 0x01300000 0 0x50000>;
2231 reg = <0x0 0x010a2000 0x0 0x1000>,
2232 <0x0 0x010ae000 0x0 0x2000>;
2237 reg = <0 0x0114a000 0 0x1000>;
2254 opp-0 {
2274 reg = <0 0x01436400 0 0x600>;
2291 opp-0 {
2311 reg = <0 0x01c00000 0 0x2000>,
2312 <0 0x60000000 0 0xf1d>,
2313 <0 0x60000f20 0 0xa8>,
2314 <0 0x60100000 0 0x100000>,
2315 <0 0x01c07000 0 0x1000>;
2318 linux,pci-domain = <0>;
2319 bus-range = <0x00 0xff>;
2325 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2326 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2331 interrupt-map-mask = <0 0 0 0x7>;
2332 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2333 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2334 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2335 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2352 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2353 <0x100 &apps_smmu 0x1c11 0x1>,
2354 <0x200 &apps_smmu 0x1c12 0x1>,
2355 <0x300 &apps_smmu 0x1c13 0x1>,
2356 <0x400 &apps_smmu 0x1c14 0x1>,
2357 <0x500 &apps_smmu 0x1c15 0x1>,
2358 <0x600 &apps_smmu 0x1c16 0x1>,
2359 <0x700 &apps_smmu 0x1c17 0x1>,
2360 <0x800 &apps_smmu 0x1c18 0x1>,
2361 <0x900 &apps_smmu 0x1c19 0x1>,
2362 <0xa00 &apps_smmu 0x1c1a 0x1>,
2363 <0xb00 &apps_smmu 0x1c1b 0x1>,
2364 <0xc00 &apps_smmu 0x1c1c 0x1>,
2365 <0xd00 &apps_smmu 0x1c1d 0x1>,
2366 <0xe00 &apps_smmu 0x1c1e 0x1>,
2367 <0xf00 &apps_smmu 0x1c1f 0x1>;
2382 reg = <0 0x01c06000 0 0x1000>;
2395 #clock-cells = <0>;
2397 #phy-cells = <0>;
2410 reg = <0 0x01c08000 0 0x2000>,
2411 <0 0x40000000 0 0xf1d>,
2412 <0 0x40000f20 0 0xa8>,
2413 <0 0x40100000 0 0x100000>,
2414 <0 0x01c0c000 0 0x1000>;
2418 bus-range = <0x00 0xff>;
2424 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2425 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2430 interrupt-map-mask = <0 0 0 0x7>;
2431 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2432 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2433 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2434 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2456 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2457 <0x100 &apps_smmu 0x1c01 0x1>,
2458 <0x200 &apps_smmu 0x1c02 0x1>,
2459 <0x300 &apps_smmu 0x1c03 0x1>,
2460 <0x400 &apps_smmu 0x1c04 0x1>,
2461 <0x500 &apps_smmu 0x1c05 0x1>,
2462 <0x600 &apps_smmu 0x1c06 0x1>,
2463 <0x700 &apps_smmu 0x1c07 0x1>,
2464 <0x800 &apps_smmu 0x1c08 0x1>,
2465 <0x900 &apps_smmu 0x1c09 0x1>,
2466 <0xa00 &apps_smmu 0x1c0a 0x1>,
2467 <0xb00 &apps_smmu 0x1c0b 0x1>,
2468 <0xc00 &apps_smmu 0x1c0c 0x1>,
2469 <0xd00 &apps_smmu 0x1c0d 0x1>,
2470 <0xe00 &apps_smmu 0x1c0e 0x1>,
2471 <0xf00 &apps_smmu 0x1c0f 0x1>;
2486 reg = <0 0x01c0a000 0 0x2000>;
2499 #clock-cells = <0>;
2501 #phy-cells = <0>;
2514 reg = <0 0x01380000 0 0x27200>;
2521 reg = <0 0x014e0000 0 0x400>;
2528 reg = <0 0x01500000 0 0x5080>;
2535 reg = <0 0x01620000 0 0x18080>;
2542 reg = <0 0x016e0000 0 0x15080>;
2549 reg = <0 0x01700000 0 0x1f300>;
2556 reg = <0 0x01740000 0 0x1c100>;
2564 reg = <0 0x01d84000 0 0x2500>,
2565 <0 0x01d90000 0 0x8000>;
2576 iommus = <&apps_smmu 0x100 0xf>;
2601 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2602 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2612 /bits/ 64 <0>,
2613 /bits/ 64 <0>,
2615 /bits/ 64 <0>,
2616 /bits/ 64 <0>,
2617 /bits/ 64 <0>,
2618 /bits/ 64 <0>,
2625 /bits/ 64 <0>,
2626 /bits/ 64 <0>,
2628 /bits/ 64 <0>,
2629 /bits/ 64 <0>,
2630 /bits/ 64 <0>,
2631 /bits/ 64 <0>,
2640 reg = <0 0x01d87000 0 0x1000>;
2647 resets = <&ufs_mem_hc 0>;
2650 #phy-cells = <0>;
2656 reg = <0 0x01dc4000 0 0x24000>;
2661 qcom,ee = <0>;
2663 iommus = <&apps_smmu 0x704 0x1>,
2664 <&apps_smmu 0x706 0x1>,
2665 <&apps_smmu 0x714 0x1>,
2666 <&apps_smmu 0x716 0x1>;
2671 reg = <0 0x01dfa000 0 0x6000>;
2678 iommus = <&apps_smmu 0x704 0x1>,
2679 <&apps_smmu 0x706 0x1>,
2680 <&apps_smmu 0x714 0x1>,
2681 <&apps_smmu 0x716 0x1>;
2687 iommus = <&apps_smmu 0x720 0x0>,
2688 <&apps_smmu 0x722 0x0>;
2689 reg = <0 0x01e40000 0 0x7000>,
2690 <0 0x01e47000 0 0x2000>,
2691 <0 0x01e04000 0 0x2c000>;
2698 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2708 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2709 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2710 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2715 qcom,smem-states = <&ipa_smp2p_out 0>,
2725 reg = <0 0x01f40000 0 0x20000>;
2731 reg = <0 0x01f60000 0 0x20000>;
2736 reg = <0 0x03400000 0 0xc00000>;
2742 gpio-ranges = <&tlmm 0 0 151>;
3275 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3280 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3302 qcom,smem-states = <&modem_smp2p_out 0>;
3309 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3340 reg = <0 0x05090000 0 0x9000>;
3354 reg = <0 0x5c00000 0 0x4000>;
3357 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3375 qcom,smem-states = <&slpi_smp2p_out 0>;
3395 #size-cells = <0>;
3397 compute-cb@0 {
3399 reg = <0>;
3407 reg = <0 0x06002000 0 0x1000>,
3408 <0 0x16280000 0 0x180000>;
3426 reg = <0 0x06041000 0 0x1000>;
3442 #size-cells = <0>;
3455 reg = <0 0x06043000 0 0x1000>;
3471 #size-cells = <0>;
3485 reg = <0 0x06045000 0 0x1000>;
3500 #size-cells = <0>;
3502 port@0 {
3503 reg = <0>;
3522 reg = <0 0x06046000 0 0x1000>;
3546 reg = <0 0x06047000 0 0x1000>;
3573 reg = <0 0x06048000 0 0x1000>;
3591 reg = <0 0x07040000 0 0x1000>;
3611 reg = <0 0x07140000 0 0x1000>;
3631 reg = <0 0x07240000 0 0x1000>;
3651 reg = <0 0x07340000 0 0x1000>;
3671 reg = <0 0x07440000 0 0x1000>;
3691 reg = <0 0x07540000 0 0x1000>;
3711 reg = <0 0x07640000 0 0x1000>;
3731 reg = <0 0x07740000 0 0x1000>;
3751 reg = <0 0x07800000 0 0x1000>;
3767 #size-cells = <0>;
3769 port@0 {
3770 reg = <0>;
3837 reg = <0 0x07810000 0 0x1000>;
3863 reg = <0 0x08804000 0 0x1000>;
3873 iommus = <&apps_smmu 0xa0 0xf>;
3906 reg = <0 0x088df000 0 0x600>;
3907 iommus = <&apps_smmu 0x160 0x0>;
3909 #size-cells = <0>;
3921 reg = <0 0x171c0000 0 0x2c000>;
3927 iommus = <&apps_smmu 0x1806 0x0>;
3929 #size-cells = <0>;
3935 reg = <0 0x17d70800 0 0x400>;
3947 reg = <0 0x17d78800 0 0x400>;
3959 reg = <0 0x088e2000 0 0x400>;
3961 #phy-cells = <0>;
3974 reg = <0 0x088e3000 0 0x400>;
3976 #phy-cells = <0>;
3989 reg = <0 0x088e8000 0 0x3000>;
4013 reg = <0 0x088eb000 0 0x1000>;
4026 #clock-cells = <0>;
4027 #phy-cells = <0>;
4039 reg = <0 0x0a6f8800 0 0x400>;
4072 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4073 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4078 reg = <0 0x0a600000 0 0xcd00>;
4080 iommus = <&apps_smmu 0x740 0>;
4090 reg = <0 0x0a8f8800 0 0x400>;
4123 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4124 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4129 reg = <0 0x0a800000 0 0xcd00>;
4131 iommus = <&apps_smmu 0x760 0>;
4141 reg = <0 0x0aa00000 0 0xff000>;
4159 iommus = <&apps_smmu 0x10a0 0x8>,
4160 <&apps_smmu 0x10b0 0x0>;
4162 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4163 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4213 reg = <0 0x0ab00000 0 0x10000>;
4224 reg = <0 0x0acb3000 0 0x1000>,
4225 <0 0x0acba000 0 0x1000>,
4226 <0 0x0acc8000 0 0x1000>,
4227 <0 0x0ac65000 0 0x1000>,
4228 <0 0x0ac66000 0 0x1000>,
4229 <0 0x0ac67000 0 0x1000>,
4230 <0 0x0ac68000 0 0x1000>,
4231 <0 0x0acaf000 0 0x4000>,
4232 <0 0x0acb6000 0 0x4000>,
4233 <0 0x0acc4000 0 0x4000>;
4343 iommus = <&apps_smmu 0x0808 0x0>,
4344 <&apps_smmu 0x0810 0x8>,
4345 <&apps_smmu 0x0c08 0x0>,
4346 <&apps_smmu 0x0c10 0x8>;
4352 #size-cells = <0>;
4354 port@0 {
4355 reg = <0>;
4375 #size-cells = <0>;
4377 reg = <0 0x0ac4a000 0 0x4000>;
4399 pinctrl-0 = <&cci0_default &cci1_default>;
4404 cci_i2c0: i2c-bus@0 {
4405 reg = <0>;
4408 #size-cells = <0>;
4415 #size-cells = <0>;
4421 reg = <0 0x0ad00000 0 0x10000>;
4431 reg = <0 0x0ae00000 0 0x1000>;
4444 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4445 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4448 iommus = <&apps_smmu 0x880 0x8>,
4449 <&apps_smmu 0xc80 0x8>;
4459 reg = <0 0x0ae01000 0 0x8f000>,
4460 <0 0x0aeb0000 0 0x2008>;
4476 interrupts = <0>;
4480 #size-cells = <0>;
4482 port@0 {
4483 reg = <0>;
4533 reg = <0 0x0ae90000 0 0x200>,
4534 <0 0x0ae90200 0 0x200>,
4535 <0 0x0ae90400 0 0x600>,
4536 <0 0x0ae90a00 0 0x600>,
4537 <0 0x0ae91000 0 0x600>;
4561 #size-cells = <0>;
4562 port@0 {
4563 reg = <0>;
4603 reg = <0 0x0ae94000 0 0x400>;
4622 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4632 #size-cells = <0>;
4636 #size-cells = <0>;
4638 port@0 {
4639 reg = <0>;
4655 reg = <0 0x0ae94400 0 0x200>,
4656 <0 0x0ae94600 0 0x280>,
4657 <0 0x0ae94a00 0 0x1e0>;
4663 #phy-cells = <0>;
4675 reg = <0 0x0ae96000 0 0x400>;
4694 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4704 #size-cells = <0>;
4708 #size-cells = <0>;
4710 port@0 {
4711 reg = <0>;
4727 reg = <0 0x0ae96400 0 0x200>,
4728 <0 0x0ae96600 0 0x280>,
4729 <0 0x0ae96a00 0 0x10e>;
4735 #phy-cells = <0>;
4748 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4758 iommus = <&adreno_smmu 0>;
4764 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4818 reg = <0 0x05040000 0 0x10000>;
4841 reg = <0 0x0506a000 0 0x30000>,
4842 <0 0x0b280000 0 0x10000>,
4843 <0 0x0b480000 0 0x10000>;
4883 reg = <0 0x0af00000 0 0x10000>;
4887 <&mdss_dsi0_phy 0>,
4889 <&mdss_dsi1_phy 0>,
4909 reg = <0 0x0b220000 0 0x30000>;
4910 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4918 reg = <0 0x0b2e0000 0 0x20000>;
4924 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4925 <0 0x0c222000 0 0x1ff>; /* SROT */
4935 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4936 <0 0x0c223000 0 0x1ff>; /* SROT */
4946 reg = <0 0x0c2a0000 0 0x31000>;
4952 reg = <0 0x0c300000 0 0x400>;
4954 mboxes = <&apss_shared 0>;
4956 #clock-cells = <0>;
4969 reg = <0 0x0c3f0000 0 0x400>;
4974 reg = <0 0x0c440000 0 0x1100>,
4975 <0 0x0c600000 0 0x2000000>,
4976 <0 0x0e600000 0 0x100000>,
4977 <0 0x0e700000 0 0xa0000>,
4978 <0 0x0c40a000 0 0x26000>;
4982 qcom,ee = <0>;
4983 qcom,channel = <0>;
4985 #size-cells = <0>;
4992 reg = <0 0x146bf000 0 0x1000>;
4997 ranges = <0 0 0x146bf000 0x1000>;
5001 reg = <0x94c 0xc8>;
5007 reg = <0 0x15000000 0 0x80000>;
5079 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5087 reg = <0 0x17900000 0 0xd080>;
5094 reg = <0 0x17980000 0 0x1000>;
5096 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5101 reg = <0 0x17990000 0 0x1000>;
5108 reg = <0 0x179c0000 0 0x10000>,
5109 <0 0x179d0000 0 0x10000>,
5110 <0 0x179e0000 0 0x10000>;
5111 reg-names = "drv-0", "drv-1", "drv-2";
5115 qcom,tcs-offset = <0xd00>;
5192 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5193 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5200 reg = <0 0x17a40000 0 0x20000>;
5208 reg = <0 0x17184000 0 0x2a000>;
5214 iommus = <&apps_smmu 0x1806 0x0>;
5220 ranges = <0 0 0 0x20000000>;
5222 reg = <0 0x17c90000 0 0x1000>;
5225 frame-number = <0>;
5228 reg = <0x17ca0000 0x1000>,
5229 <0x17cb0000 0x1000>;
5235 reg = <0x17cc0000 0x1000>;
5242 reg = <0x17cd0000 0x1000>;
5249 reg = <0x17ce0000 0x1000>;
5256 reg = <0x17cf0000 0x1000>;
5263 reg = <0x17d00000 0x1000>;
5270 reg = <0x17d10000 0x1000>;
5277 reg = <0 0x17d41000 0 0x1400>;
5287 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5290 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5302 reg = <0 0x18800000 0 0x800000>;
5320 iommus = <&apps_smmu 0x0040 0x1>;
5548 thermal-sensors = <&tsens0 0>;
5633 thermal-sensors = <&tsens1 0>;
5755 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;