Lines Matching +full:ddr +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
32 #address-cells = <2>;
33 #size-cells = <0>;
39 enable-method = "psci";
40 capacity-dmips-mhz = <610>;
41 dynamic-power-coefficient = <203>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
43 operating-points-v2 = <&cpu0_opp_table>;
46 power-domains = <&CPU_PD0>;
47 power-domain-names = "psci";
48 next-level-cache = <&L2_0>;
49 L2_0: l2-cache {
51 next-level-cache = <&L3_0>;
52 cache-level = <2>;
53 cache-unified;
54 L3_0: l3-cache {
56 cache-level = <3>;
57 cache-unified;
66 enable-method = "psci";
67 capacity-dmips-mhz = <610>;
68 dynamic-power-coefficient = <203>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
70 operating-points-v2 = <&cpu0_opp_table>;
73 power-domains = <&CPU_PD1>;
74 power-domain-names = "psci";
75 next-level-cache = <&L2_100>;
76 L2_100: l2-cache {
78 cache-level = <2>;
79 cache-unified;
80 next-level-cache = <&L3_0>;
88 enable-method = "psci";
89 capacity-dmips-mhz = <610>;
90 dynamic-power-coefficient = <203>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
92 operating-points-v2 = <&cpu0_opp_table>;
95 power-domains = <&CPU_PD2>;
96 power-domain-names = "psci";
97 next-level-cache = <&L2_200>;
98 L2_200: l2-cache {
100 cache-level = <2>;
101 cache-unified;
102 next-level-cache = <&L3_0>;
110 enable-method = "psci";
111 capacity-dmips-mhz = <610>;
112 dynamic-power-coefficient = <203>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <&cpu0_opp_table>;
117 power-domains = <&CPU_PD3>;
118 power-domain-names = "psci";
119 next-level-cache = <&L2_300>;
120 L2_300: l2-cache {
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&L3_0>;
132 enable-method = "psci";
133 capacity-dmips-mhz = <610>;
134 dynamic-power-coefficient = <203>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
136 operating-points-v2 = <&cpu0_opp_table>;
139 power-domains = <&CPU_PD4>;
140 power-domain-names = "psci";
141 next-level-cache = <&L2_400>;
142 L2_400: l2-cache {
144 cache-level = <2>;
145 cache-unified;
146 next-level-cache = <&L3_0>;
154 enable-method = "psci";
155 capacity-dmips-mhz = <610>;
156 dynamic-power-coefficient = <203>;
157 qcom,freq-domain = <&cpufreq_hw 0>;
158 operating-points-v2 = <&cpu0_opp_table>;
161 power-domains = <&CPU_PD5>;
162 power-domain-names = "psci";
163 next-level-cache = <&L2_500>;
164 L2_500: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
176 enable-method = "psci";
177 capacity-dmips-mhz = <1024>;
178 dynamic-power-coefficient = <393>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu6_opp_table>;
183 power-domains = <&CPU_PD6>;
184 power-domain-names = "psci";
185 next-level-cache = <&L2_600>;
186 L2_600: l2-cache {
188 cache-level = <2>;
189 cache-unified;
190 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <393>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu6_opp_table>;
205 power-domains = <&CPU_PD7>;
206 power-domain-names = "psci";
207 next-level-cache = <&L2_700>;
208 L2_700: l2-cache {
210 cache-level = <2>;
211 cache-unified;
212 next-level-cache = <&L3_0>;
216 cpu-map {
252 idle-states {
253 entry-method = "psci";
255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
256 compatible = "arm,idle-state";
257 idle-state-name = "little-rail-power-collapse";
258 arm,psci-suspend-param = <0x40000004>;
259 entry-latency-us = <702>;
260 exit-latency-us = <915>;
261 min-residency-us = <1617>;
262 local-timer-stop;
265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
266 compatible = "arm,idle-state";
267 idle-state-name = "big-rail-power-collapse";
268 arm,psci-suspend-param = <0x40000004>;
269 entry-latency-us = <526>;
270 exit-latency-us = <1854>;
271 min-residency-us = <2380>;
272 local-timer-stop;
276 domain-idle-states {
277 CLUSTER_SLEEP_0: cluster-sleep-0 {
278 compatible = "domain-idle-state";
279 arm,psci-suspend-param = <0x4100c244>;
280 entry-latency-us = <3263>;
281 exit-latency-us = <6562>;
282 min-residency-us = <9825>;
289 compatible = "qcom,scm-sdm670", "qcom,scm";
299 cpu0_opp_table: opp-table-cpu0 {
300 compatible = "operating-points-v2";
301 opp-shared;
303 cpu0_opp1: opp-300000000 {
304 opp-hz = /bits/ 64 <300000000>;
305 opp-peak-kBps = <400000 4800000>;
308 cpu0_opp2: opp-576000000 {
309 opp-hz = /bits/ 64 <576000000>;
310 opp-peak-kBps = <400000 4800000>;
313 cpu0_opp3: opp-748800000 {
314 opp-hz = /bits/ 64 <748800000>;
315 opp-peak-kBps = <1200000 4800000>;
318 cpu0_opp4: opp-998400000 {
319 opp-hz = /bits/ 64 <998400000>;
320 opp-peak-kBps = <1804000 8908800>;
323 cpu0_opp5: opp-1209600000 {
324 opp-hz = /bits/ 64 <1209600000>;
325 opp-peak-kBps = <2188000 8908800>;
328 cpu0_opp6: opp-1324800000 {
329 opp-hz = /bits/ 64 <1324800000>;
330 opp-peak-kBps = <2188000 13516800>;
333 cpu0_opp7: opp-1516800000 {
334 opp-hz = /bits/ 64 <1516800000>;
335 opp-peak-kBps = <3072000 15052800>;
338 cpu0_opp8: opp-1612800000 {
339 opp-hz = /bits/ 64 <1612800000>;
340 opp-peak-kBps = <3072000 22118400>;
343 cpu0_opp9: opp-1708800000 {
344 opp-hz = /bits/ 64 <1708800000>;
345 opp-peak-kBps = <4068000 23040000>;
349 cpu6_opp_table: opp-table-cpu6 {
350 compatible = "operating-points-v2";
351 opp-shared;
353 cpu6_opp1: opp-300000000 {
354 opp-hz = /bits/ 64 <300000000>;
355 opp-peak-kBps = <400000 4800000>;
358 cpu6_opp2: opp-652800000 {
359 opp-hz = /bits/ 64 <652800000>;
360 opp-peak-kBps = <400000 4800000>;
363 cpu6_opp3: opp-825600000 {
364 opp-hz = /bits/ 64 <825600000>;
365 opp-peak-kBps = <1200000 4800000>;
368 cpu6_opp4: opp-979200000 {
369 opp-hz = /bits/ 64 <979200000>;
370 opp-peak-kBps = <1200000 4800000>;
373 cpu6_opp5: opp-1132800000 {
374 opp-hz = /bits/ 64 <1132800000>;
375 opp-peak-kBps = <2188000 8908800>;
378 cpu6_opp6: opp-1363200000 {
379 opp-hz = /bits/ 64 <1363200000>;
380 opp-peak-kBps = <4068000 12902400>;
383 cpu6_opp7: opp-1536000000 {
384 opp-hz = /bits/ 64 <1536000000>;
385 opp-peak-kBps = <4068000 12902400>;
388 cpu6_opp8: opp-1747200000 {
389 opp-hz = /bits/ 64 <1747200000>;
390 opp-peak-kBps = <4068000 15052800>;
393 cpu6_opp9: opp-1843200000 {
394 opp-hz = /bits/ 64 <1843200000>;
395 opp-peak-kBps = <4068000 15052800>;
398 cpu6_opp10: opp-1996800000 {
399 opp-hz = /bits/ 64 <1996800000>;
400 opp-peak-kBps = <6220000 19046400>;
404 dsi_opp_table: opp-table-dsi {
405 compatible = "operating-points-v2";
407 opp-19200000 {
408 opp-hz = /bits/ 64 <19200000>;
409 required-opps = <&rpmhpd_opp_min_svs>;
412 opp-180000000 {
413 opp-hz = /bits/ 64 <180000000>;
414 required-opps = <&rpmhpd_opp_low_svs>;
417 opp-275000000 {
418 opp-hz = /bits/ 64 <275000000>;
419 required-opps = <&rpmhpd_opp_svs>;
422 opp-358000000 {
423 opp-hz = /bits/ 64 <358000000>;
424 required-opps = <&rpmhpd_opp_svs_l1>;
429 compatible = "arm,psci-1.0";
432 CPU_PD0: power-domain-cpu0 {
433 #power-domain-cells = <0>;
434 power-domains = <&CLUSTER_PD>;
435 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
438 CPU_PD1: power-domain-cpu1 {
439 #power-domain-cells = <0>;
440 power-domains = <&CLUSTER_PD>;
441 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
444 CPU_PD2: power-domain-cpu2 {
445 #power-domain-cells = <0>;
446 power-domains = <&CLUSTER_PD>;
447 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
450 CPU_PD3: power-domain-cpu3 {
451 #power-domain-cells = <0>;
452 power-domains = <&CLUSTER_PD>;
453 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
456 CPU_PD4: power-domain-cpu4 {
457 #power-domain-cells = <0>;
458 power-domains = <&CLUSTER_PD>;
459 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
462 CPU_PD5: power-domain-cpu5 {
463 #power-domain-cells = <0>;
464 power-domains = <&CLUSTER_PD>;
465 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
468 CPU_PD6: power-domain-cpu6 {
469 #power-domain-cells = <0>;
470 power-domains = <&CLUSTER_PD>;
471 domain-idle-states = <&BIG_CPU_SLEEP_0>;
474 CPU_PD7: power-domain-cpu7 {
475 #power-domain-cells = <0>;
476 power-domains = <&CLUSTER_PD>;
477 domain-idle-states = <&BIG_CPU_SLEEP_0>;
480 CLUSTER_PD: power-domain-cluster {
481 #power-domain-cells = <0>;
482 domain-idle-states = <&CLUSTER_SLEEP_0>;
486 reserved-memory {
487 #address-cells = <2>;
488 #size-cells = <2>;
491 hyp_mem: hyp-mem@85700000 {
493 no-map;
496 xbl_mem: xbl-mem@85e00000 {
498 no-map;
501 aop_mem: aop-mem@85fc0000 {
503 no-map;
506 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
507 compatible = "qcom,cmd-db";
509 no-map;
512 camera_mem: camera-mem@8ab00000 {
514 no-map;
519 no-map;
524 no-map;
527 wlan_msa_mem: wlan-msa@93300000 {
529 no-map;
534 no-map;
539 no-map;
544 no-map;
547 ipa_fw_mem: ipa-fw@95c00000 {
549 no-map;
552 ipa_gsi_mem: ipa-gsi@95c10000 {
554 no-map;
559 no-map;
564 no-map;
569 no-map;
574 compatible = "arm,armv8-timer";
582 #address-cells = <2>;
583 #size-cells = <2>;
585 dma-ranges = <0 0 0 0 0x10 0>;
586 compatible = "simple-bus";
588 gcc: clock-controller@100000 {
589 compatible = "qcom,gcc-sdm670";
594 clock-names = "bi_tcxo",
597 #clock-cells = <1>;
598 #reset-cells = <1>;
599 #power-domain-cells = <1>;
603 compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
605 #address-cells = <1>;
606 #size-cells = <1>;
608 qusb2_hstx_trim: hstx-trim@1eb {
615 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
619 reg-names = "hc", "cqhci", "ice";
623 interrupt-names = "hc_irq", "pwr_irq";
630 clock-names = "iface", "core", "xo", "ice", "bus";
633 interconnect-names = "sdhc-ddr", "cpu-sdhc";
634 operating-points-v2 = <&sdhc1_opp_table>;
638 pinctrl-names = "default", "sleep";
639 pinctrl-0 = <&sdc1_state_on>;
640 pinctrl-1 = <&sdc1_state_off>;
641 power-domains = <&rpmhpd SDM670_CX>;
643 bus-width = <8>;
644 non-removable;
648 sdhc1_opp_table: opp-table {
649 compatible = "operating-points-v2";
651 opp-20000000 {
652 opp-hz = /bits/ 64 <20000000>;
653 required-opps = <&rpmhpd_opp_min_svs>;
654 opp-peak-kBps = <80000 80000>;
655 opp-avg-kBps = <52286 80000>;
658 opp-50000000 {
659 opp-hz = /bits/ 64 <50000000>;
660 required-opps = <&rpmhpd_opp_low_svs>;
661 opp-peak-kBps = <200000 100000>;
662 opp-avg-kBps = <130718 100000>;
665 opp-100000000 {
666 opp-hz = /bits/ 64 <100000000>;
667 required-opps = <&rpmhpd_opp_svs>;
668 opp-peak-kBps = <200000 130000>;
669 opp-avg-kBps = <130718 130000>;
672 opp-384000000 {
673 opp-hz = /bits/ 64 <384000000>;
674 required-opps = <&rpmhpd_opp_nom>;
675 opp-peak-kBps = <4096000 4096000>;
676 opp-avg-kBps = <1338562 1338562>;
681 gpi_dma0: dma-controller@800000 {
682 #dma-cells = <3>;
683 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
698 dma-channels = <13>;
699 dma-channel-mask = <0xfa>;
705 compatible = "qcom,geni-se-qup";
707 clock-names = "m-ahb", "s-ahb";
711 #address-cells = <2>;
712 #size-cells = <2>;
715 interconnect-names = "qup-core";
719 compatible = "qcom,geni-i2c";
721 clock-names = "se";
723 pinctrl-names = "default";
724 pinctrl-0 = <&qup_i2c0_default>;
726 #address-cells = <1>;
727 #size-cells = <0>;
728 power-domains = <&rpmhpd SDM670_CX>;
732 interconnect-names = "qup-core", "qup-config", "qup-memory";
735 dma-names = "tx", "rx";
740 compatible = "qcom,geni-i2c";
742 clock-names = "se";
744 pinctrl-names = "default";
745 pinctrl-0 = <&qup_i2c1_default>;
747 #address-cells = <1>;
748 #size-cells = <0>;
749 power-domains = <&rpmhpd SDM670_CX>;
753 interconnect-names = "qup-core", "qup-config", "qup-memory";
756 dma-names = "tx", "rx";
761 compatible = "qcom,geni-i2c";
763 clock-names = "se";
765 pinctrl-names = "default";
766 pinctrl-0 = <&qup_i2c2_default>;
768 #address-cells = <1>;
769 #size-cells = <0>;
770 power-domains = <&rpmhpd SDM670_CX>;
774 interconnect-names = "qup-core", "qup-config", "qup-memory";
777 dma-names = "tx", "rx";
782 compatible = "qcom,geni-i2c";
784 clock-names = "se";
786 pinctrl-names = "default";
787 pinctrl-0 = <&qup_i2c3_default>;
789 #address-cells = <1>;
790 #size-cells = <0>;
791 power-domains = <&rpmhpd SDM670_CX>;
795 interconnect-names = "qup-core", "qup-config", "qup-memory";
798 dma-names = "tx", "rx";
803 compatible = "qcom,geni-i2c";
805 clock-names = "se";
807 pinctrl-names = "default";
808 pinctrl-0 = <&qup_i2c4_default>;
810 #address-cells = <1>;
811 #size-cells = <0>;
812 power-domains = <&rpmhpd SDM670_CX>;
816 interconnect-names = "qup-core", "qup-config", "qup-memory";
819 dma-names = "tx", "rx";
824 compatible = "qcom,geni-i2c";
826 clock-names = "se";
828 pinctrl-names = "default";
829 pinctrl-0 = <&qup_i2c5_default>;
831 #address-cells = <1>;
832 #size-cells = <0>;
833 power-domains = <&rpmhpd SDM670_CX>;
837 interconnect-names = "qup-core", "qup-config", "qup-memory";
840 dma-names = "tx", "rx";
845 compatible = "qcom,geni-i2c";
847 clock-names = "se";
849 pinctrl-names = "default";
850 pinctrl-0 = <&qup_i2c6_default>;
852 #address-cells = <1>;
853 #size-cells = <0>;
854 power-domains = <&rpmhpd SDM670_CX>;
858 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dma-names = "tx", "rx";
866 compatible = "qcom,geni-i2c";
868 clock-names = "se";
870 pinctrl-names = "default";
871 pinctrl-0 = <&qup_i2c7_default>;
873 #address-cells = <1>;
874 #size-cells = <0>;
875 power-domains = <&rpmhpd SDM670_CX>;
879 interconnect-names = "qup-core", "qup-config", "qup-memory";
882 dma-names = "tx", "rx";
887 gpi_dma1: dma-controller@a00000 {
888 #dma-cells = <3>;
889 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
904 dma-channels = <13>;
905 dma-channel-mask = <0xfa>;
911 compatible = "qcom,geni-se-qup";
913 clock-names = "m-ahb", "s-ahb";
917 #address-cells = <2>;
918 #size-cells = <2>;
921 interconnect-names = "qup-core";
925 compatible = "qcom,geni-i2c";
927 clock-names = "se";
929 pinctrl-names = "default";
930 pinctrl-0 = <&qup_i2c8_default>;
932 #address-cells = <1>;
933 #size-cells = <0>;
934 power-domains = <&rpmhpd SDM670_CX>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
941 dma-names = "tx", "rx";
946 compatible = "qcom,geni-i2c";
948 clock-names = "se";
950 pinctrl-names = "default";
951 pinctrl-0 = <&qup_i2c9_default>;
953 #address-cells = <1>;
954 #size-cells = <0>;
955 power-domains = <&rpmhpd SDM670_CX>;
959 interconnect-names = "qup-core", "qup-config", "qup-memory";
962 dma-names = "tx", "rx";
967 compatible = "qcom,geni-i2c";
969 clock-names = "se";
971 pinctrl-names = "default";
972 pinctrl-0 = <&qup_i2c10_default>;
974 #address-cells = <1>;
975 #size-cells = <0>;
976 power-domains = <&rpmhpd SDM670_CX>;
980 interconnect-names = "qup-core", "qup-config", "qup-memory";
983 dma-names = "tx", "rx";
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c11_default>;
995 #address-cells = <1>;
996 #size-cells = <0>;
997 power-domains = <&rpmhpd SDM670_CX>;
1001 interconnect-names = "qup-core", "qup-config", "qup-memory";
1004 dma-names = "tx", "rx";
1009 compatible = "qcom,geni-i2c";
1011 clock-names = "se";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&qup_i2c12_default>;
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 power-domains = <&rpmhpd SDM670_CX>;
1022 interconnect-names = "qup-core", "qup-config", "qup-memory";
1025 dma-names = "tx", "rx";
1030 compatible = "qcom,geni-i2c";
1032 clock-names = "se";
1034 pinctrl-names = "default";
1035 pinctrl-0 = <&qup_i2c13_default>;
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 power-domains = <&rpmhpd SDM670_CX>;
1043 interconnect-names = "qup-core", "qup-config", "qup-memory";
1046 dma-names = "tx", "rx";
1051 compatible = "qcom,geni-i2c";
1053 clock-names = "se";
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&qup_i2c14_default>;
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 power-domains = <&rpmhpd SDM670_CX>;
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1067 dma-names = "tx", "rx";
1072 compatible = "qcom,geni-i2c";
1074 clock-names = "se";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c15_default>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081 power-domains = <&rpmhpd SDM670_CX>;
1085 interconnect-names = "qup-core", "qup-config", "qup-memory";
1088 dma-names = "tx", "rx";
1094 compatible = "qcom,sdm670-mem-noc";
1096 #interconnect-cells = <2>;
1097 qcom,bcm-voters = <&apps_bcm_voter>;
1101 compatible = "qcom,sdm670-dc-noc";
1103 #interconnect-cells = <2>;
1104 qcom,bcm-voters = <&apps_bcm_voter>;
1108 compatible = "qcom,sdm670-config-noc";
1110 #interconnect-cells = <2>;
1111 qcom,bcm-voters = <&apps_bcm_voter>;
1115 compatible = "qcom,sdm670-system-noc";
1117 #interconnect-cells = <2>;
1118 qcom,bcm-voters = <&apps_bcm_voter>;
1122 compatible = "qcom,sdm670-aggre1-noc";
1124 #interconnect-cells = <2>;
1125 qcom,bcm-voters = <&apps_bcm_voter>;
1129 compatible = "qcom,sdm670-aggre2-noc";
1131 #interconnect-cells = <2>;
1132 qcom,bcm-voters = <&apps_bcm_voter>;
1136 compatible = "qcom,sdm670-mmss-noc";
1138 #interconnect-cells = <2>;
1139 qcom,bcm-voters = <&apps_bcm_voter>;
1143 compatible = "qcom,sdm670-tlmm";
1146 gpio-controller;
1147 #gpio-cells = <2>;
1148 interrupt-controller;
1149 #interrupt-cells = <2>;
1150 gpio-ranges = <&tlmm 0 0 151>;
1151 wakeup-parent = <&pdc>;
1153 qup_i2c0_default: qup-i2c0-default-state {
1158 qup_i2c1_default: qup-i2c1-default-state {
1163 qup_i2c2_default: qup-i2c2-default-state {
1168 qup_i2c3_default: qup-i2c3-default-state {
1173 qup_i2c4_default: qup-i2c4-default-state {
1178 qup_i2c5_default: qup-i2c5-default-state {
1183 qup_i2c6_default: qup-i2c6-default-state {
1188 qup_i2c7_default: qup-i2c7-default-state {
1193 qup_i2c8_default: qup-i2c8-default-state {
1198 qup_i2c9_default: qup-i2c9-default-state {
1203 qup_i2c10_default: qup-i2c10-default-state {
1208 qup_i2c11_default: qup-i2c11-default-state {
1213 qup_i2c12_default: qup-i2c12-default-state {
1218 qup_i2c13_default: qup-i2c13-default-state {
1223 qup_i2c14_default: qup-i2c14-default-state {
1228 qup_i2c15_default: qup-i2c15-default-state {
1233 sdc1_state_on: sdc1-on-state {
1234 clk-pins {
1236 bias-disable;
1237 drive-strength = <16>;
1240 cmd-pins {
1242 bias-pull-up;
1243 drive-strength = <10>;
1246 data-pins {
1248 bias-pull-up;
1249 drive-strength = <10>;
1252 rclk-pins {
1254 bias-pull-down;
1258 sdc1_state_off: sdc1-off-state {
1259 clk-pins {
1261 bias-disable;
1262 drive-strength = <2>;
1265 cmd-pins {
1267 bias-pull-up;
1268 drive-strength = <2>;
1271 data-pins {
1273 bias-pull-up;
1274 drive-strength = <2>;
1277 rclk-pins {
1279 bias-pull-down;
1285 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1287 #phy-cells = <0>;
1291 clock-names = "cfg_ahb", "ref";
1295 nvmem-cells = <&qusb2_hstx_trim>;
1301 compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1303 #address-cells = <2>;
1304 #size-cells = <2>;
1306 dma-ranges;
1313 clock-names = "cfg_noc",
1319 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1321 assigned-clock-rates = <19200000>, <150000000>;
1323 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1327 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1330 power-domains = <&gcc USB30_PRIM_GDSC>;
1336 interconnect-names = "usb-ddr", "apps-usb";
1348 phy-names = "usb2-phy";
1352 pdc: interrupt-controller@b220000 {
1353 compatible = "qcom,sdm670-pdc", "qcom,pdc";
1355 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1358 #interrupt-cells = <2>;
1359 interrupt-parent = <&intc>;
1360 interrupt-controller;
1364 compatible = "qcom,spmi-pmic-arb";
1370 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1371 interrupt-names = "periph_irq";
1375 #address-cells = <2>;
1376 #size-cells = <0>;
1377 interrupt-controller;
1378 #interrupt-cells = <4>;
1381 mdss: display-subsystem@ae00000 {
1382 compatible = "qcom,sdm670-mdss";
1384 reg-names = "mdss";
1386 power-domains = <&dispcc MDSS_GDSC>;
1390 clock-names = "iface", "core";
1393 interrupt-controller;
1394 #interrupt-cells = <1>;
1398 interconnect-names = "mdp0-mem", "mdp1-mem";
1403 #address-cells = <2>;
1404 #size-cells = <2>;
1409 mdss_mdp: display-controller@ae01000 {
1410 compatible = "qcom,sdm670-dpu";
1413 reg-names = "mdp", "vbif";
1420 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
1422 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1423 assigned-clock-rates = <19200000>;
1424 operating-points-v2 = <&mdp_opp_table>;
1425 power-domains = <&rpmhpd SDM670_CX>;
1427 interrupt-parent = <&mdss>;
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1437 remote-endpoint = <&mdss_dsi0_in>;
1444 remote-endpoint = <&mdss_dsi1_in>;
1449 mdp_opp_table: opp-table {
1450 compatible = "operating-points-v2";
1452 opp-19200000 {
1453 opp-hz = /bits/ 64 <19200000>;
1454 required-opps = <&rpmhpd_opp_min_svs>;
1457 opp-171428571 {
1458 opp-hz = /bits/ 64 <171428571>;
1459 required-opps = <&rpmhpd_opp_low_svs>;
1462 opp-358000000 {
1463 opp-hz = /bits/ 64 <358000000>;
1464 required-opps = <&rpmhpd_opp_svs_l1>;
1467 opp-430000000 {
1468 opp-hz = /bits/ 64 <430000000>;
1469 required-opps = <&rpmhpd_opp_nom>;
1475 compatible = "qcom,sdm670-dsi-ctrl",
1476 "qcom,mdss-dsi-ctrl";
1478 reg-names = "dsi_ctrl";
1480 interrupt-parent = <&mdss>;
1489 clock-names = "byte",
1495 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1497 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1500 operating-points-v2 = <&dsi_opp_table>;
1501 power-domains = <&rpmhpd SDM670_CX>;
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1517 remote-endpoint = <&dpu_intf0_out>;
1530 compatible = "qcom,dsi-phy-10nm";
1534 reg-names = "dsi_phy",
1538 #clock-cells = <1>;
1539 #phy-cells = <0>;
1543 clock-names = "iface", "ref";
1549 compatible = "qcom,sdm670-dsi-ctrl",
1550 "qcom,mdss-dsi-ctrl";
1552 reg-names = "dsi_ctrl";
1554 interrupt-parent = <&mdss>;
1563 clock-names = "byte",
1569 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
1571 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1573 operating-points-v2 = <&dsi_opp_table>;
1574 power-domains = <&rpmhpd SDM670_CX>;
1578 #address-cells = <1>;
1579 #size-cells = <0>;
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1590 remote-endpoint = <&dpu_intf1_out>;
1603 compatible = "qcom,dsi-phy-10nm";
1607 reg-names = "dsi_phy",
1611 #clock-cells = <1>;
1612 #phy-cells = <0>;
1616 clock-names = "iface", "ref";
1622 dispcc: clock-controller@af00000 {
1623 compatible = "qcom,sdm845-dispcc";
1634 clock-names = "bi_tcxo",
1643 #clock-cells = <1>;
1644 #reset-cells = <1>;
1645 #power-domain-cells = <1>;
1649 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1651 #iommu-cells = <2>;
1652 #global-interrupts = <1>;
1721 compatible = "qcom,sdm670-gladiator-noc";
1723 #interconnect-cells = <2>;
1724 qcom,bcm-voters = <&apps_bcm_voter>;
1728 compatible = "qcom,rpmh-rsc";
1732 reg-names = "drv-0", "drv-1", "drv-2";
1737 qcom,tcs-offset = <0xd00>;
1738 qcom,drv-id = <2>;
1739 qcom,tcs-config = <ACTIVE_TCS 2>,
1743 power-domains = <&CLUSTER_PD>;
1745 apps_bcm_voter: bcm-voter {
1746 compatible = "qcom,bcm-voter";
1749 rpmhcc: clock-controller {
1750 compatible = "qcom,sdm670-rpmh-clk";
1751 #clock-cells = <1>;
1752 clock-names = "xo";
1756 rpmhpd: power-controller {
1757 compatible = "qcom,sdm670-rpmhpd";
1758 #power-domain-cells = <1>;
1759 operating-points-v2 = <&rpmhpd_opp_table>;
1761 rpmhpd_opp_table: opp-table {
1762 compatible = "operating-points-v2";
1765 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1769 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1773 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1777 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1781 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1785 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1789 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1793 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1797 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1801 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1807 intc: interrupt-controller@17a00000 {
1808 compatible = "arm,gic-v3";
1811 interrupt-controller;
1813 #interrupt-cells = <3>;
1817 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
1821 clock-names = "xo", "alternate";
1823 #interconnect-cells = <1>;
1827 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
1829 reg-names = "freq-domain0", "freq-domain1";
1832 clock-names = "xo", "alternate";
1834 #freq-domain-cells = <1>;