Lines Matching +full:1 +full:f40000

179 			qcom,freq-domain = <&cpufreq_hw 1>;
201 			qcom,freq-domain = <&cpufreq_hw 1>;
265 			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
587 		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
609 			#clock-cells = <1>;
610 			#reset-cells = <1>;
611 			#power-domain-cells = <1>;
617 			#address-cells = <1>;
618 			#size-cells = <1>;
620 			qusb2_hstx_trim: hstx-trim@1eb {
622 				bits = <1 4>;
652 			pinctrl-1 = <&sdc1_state_off>;
738 				#address-cells = <1>;
746 				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
759 				#address-cells = <1>;
766 				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
767 				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
780 				#address-cells = <1>;
788 				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
801 				#address-cells = <1>;
809 				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
822 				#address-cells = <1>;
830 				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
843 				#address-cells = <1>;
851 				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
864 				#address-cells = <1>;
872 				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
885 				#address-cells = <1>;
893 				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
944 				#address-cells = <1>;
952 				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
965 				#address-cells = <1>;
972 				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
973 				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
986 				#address-cells = <1>;
994 				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1007 				#address-cells = <1>;
1015 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1028 				#address-cells = <1>;
1036 				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1049 				#address-cells = <1>;
1057 				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1070 				#address-cells = <1>;
1078 				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1091 				#address-cells = <1>;
1099 				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1154 		tcsr_mutex: hwlock@1f40000 {
1157 			#hwlock-cells = <1>;
1416 			#interrupt-cells = <1>;
1453 					#address-cells = <1>;
1463 					port@1 {
1464 						reg = <1>;
1520 							 <&mdss_dsi0_phy 1>;
1527 				#address-cells = <1>;
1533 					#address-cells = <1>;
1543 					port@1 {
1544 						reg = <1>;
1560 				#clock-cells = <1>;
1593 				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1600 				#address-cells = <1>;
1606 					#address-cells = <1>;
1616 					port@1 {
1617 						reg = <1>;
1633 				#clock-cells = <1>;
1651 				 <&mdss_dsi0_phy 1>,
1653 				 <&mdss_dsi1_phy 1>,
1665 			#clock-cells = <1>;
1666 			#reset-cells = <1>;
1667 			#power-domain-cells = <1>;
1674 			#global-interrupts = <1>;
1754 			reg-names = "drv-0", "drv-1", "drv-2";
1764 					  <CONTROL_TCS 1>;
1773 				#clock-cells = <1>;
1780 				#power-domain-cells = <1>;
1845 			#interconnect-cells = <1>;
1856 			#freq-domain-cells = <1>;