Lines Matching +full:1 +full:a98000
179 qcom,freq-domain = <&cpufreq_hw 1>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
575 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
597 #clock-cells = <1>;
598 #reset-cells = <1>;
599 #power-domain-cells = <1>;
605 #address-cells = <1>;
606 #size-cells = <1>;
608 qusb2_hstx_trim: hstx-trim@1eb {
610 bits = <1 4>;
640 pinctrl-1 = <&sdc1_state_off>;
726 #address-cells = <1>;
734 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
747 #address-cells = <1>;
754 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
755 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
768 #address-cells = <1>;
776 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
789 #address-cells = <1>;
797 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
810 #address-cells = <1>;
818 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
831 #address-cells = <1>;
839 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
852 #address-cells = <1>;
860 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
873 #address-cells = <1>;
881 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
932 #address-cells = <1>;
940 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
953 #address-cells = <1>;
960 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
961 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
974 #address-cells = <1>;
982 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
995 #address-cells = <1>;
1003 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1016 #address-cells = <1>;
1024 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1037 #address-cells = <1>;
1045 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1050 i2c14: i2c@a98000 {
1058 #address-cells = <1>;
1066 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1079 #address-cells = <1>;
1087 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1394 #interrupt-cells = <1>;
1431 #address-cells = <1>;
1441 port@1 {
1442 reg = <1>;
1498 <&mdss_dsi0_phy 1>;
1505 #address-cells = <1>;
1511 #address-cells = <1>;
1521 port@1 {
1522 reg = <1>;
1538 #clock-cells = <1>;
1571 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1578 #address-cells = <1>;
1584 #address-cells = <1>;
1594 port@1 {
1595 reg = <1>;
1611 #clock-cells = <1>;
1629 <&mdss_dsi0_phy 1>,
1631 <&mdss_dsi1_phy 1>,
1643 #clock-cells = <1>;
1644 #reset-cells = <1>;
1645 #power-domain-cells = <1>;
1652 #global-interrupts = <1>;
1732 reg-names = "drv-0", "drv-1", "drv-2";
1742 <CONTROL_TCS 1>;
1751 #clock-cells = <1>;
1758 #power-domain-cells = <1>;
1823 #interconnect-cells = <1>;
1834 #freq-domain-cells = <1>;