Lines Matching +full:opp +full:- +full:0

1 // SPDX-License-Identifier: GPL-2.0-only
13 	compatible = "qcom,adreno-512.0", "qcom,adreno";
14 	operating-points-v2 = <&gpu_sdm660_opp_table>;
16 	gpu_sdm660_opp_table: opp-table {
17 		compatible = "operating-points-v2";
23 		 * at the same opp-level
25 		opp-750000000 {
26 			opp-hz = /bits/ 64 <750000000>;
27 			opp-level = <RPM_SMD_LEVEL_TURBO>;
28 			opp-peak-kBps = <5412000>;
29 			opp-supported-hw = <0xCHECKME>;
36 		opp-700000000 {
37 			opp-hz = /bits/ 64 <700000000>;
38 			opp-level = <RPM_SMD_LEVEL_TURBO>;
39 			opp-peak-kBps = <5184000>;
40 			opp-supported-hw = <0xff>;
43 		opp-647000000 {
44 			opp-hz = /bits/ 64 <647000000>;
45 			opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
46 			opp-peak-kBps = <4068000>;
47 			opp-supported-hw = <0xff>;
50 		opp-588000000 {
51 			opp-hz = /bits/ 64 <588000000>;
52 			opp-level = <RPM_SMD_LEVEL_NOM>;
53 			opp-peak-kBps = <3072000>;
54 			opp-supported-hw = <0xff>;
57 		opp-465000000 {
58 			opp-hz = /bits/ 64 <465000000>;
59 			opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
60 			opp-peak-kBps = <2724000>;
61 			opp-supported-hw = <0xff>;
64 		opp-370000000 {
65 			opp-hz = /bits/ 64 <370000000>;
66 			opp-level = <RPM_SMD_LEVEL_SVS>;
67 			opp-peak-kBps = <2188000>;
68 			opp-supported-hw = <0xff>;
72 		opp-266000000 {
73 			opp-hz = /bits/ 64 <266000000>;
74 			opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
75 			opp-peak-kBps = <1648000>;
76 			opp-supported-hw = <0xff>;
79 		opp-160000000 {
80 			opp-hz = /bits/ 64 <160000000>;
81 			opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
82 			opp-peak-kBps = <1200000>;
83 			opp-supported-hw = <0xff>;
90 	capacity-dmips-mhz = <1024>;
91 	/delete-property/ operating-points-v2;
96 	capacity-dmips-mhz = <1024>;
97 	/delete-property/ operating-points-v2;
102 	capacity-dmips-mhz = <1024>;
103 	/delete-property/ operating-points-v2;
108 	capacity-dmips-mhz = <1024>;
109 	/delete-property/ operating-points-v2;
114 	capacity-dmips-mhz = <640>;
115 	/delete-property/ operating-points-v2;
120 	capacity-dmips-mhz = <640>;
121 	/delete-property/ operating-points-v2;
126 	capacity-dmips-mhz = <640>;
127 	/delete-property/ operating-points-v2;
132 	capacity-dmips-mhz = <640>;
133 	/delete-property/ operating-points-v2;
137 	compatible = "qcom,gcc-sdm660";
141 	compatible = "qcom,gpucc-sdm660";
145 	compatible = "qcom,sdm660-mdp5", "qcom,mdp5";
151 				remote-endpoint = <&mdss_dsi1_in>;
159 		compatible = "qcom,sdm660-dsi-ctrl",
160 			     "qcom,mdss-dsi-ctrl";
161 		reg = <0x0c996000 0x400>;
162 		reg-names = "dsi_ctrl";
164 		/* DSI1 shares the OPP table with DSI0 */
165 		operating-points-v2 = <&dsi_opp_table>;
166 		power-domains = <&rpmpd SDM660_VDDCX>;
168 		interrupt-parent = <&mdss>;
171 		assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
173 		assigned-clock-parents = <&mdss_dsi1_phy 0>,
185 		clock-names = "mdp_core",
200 			#address-cells = <1>;
201 			#size-cells = <0>;
203 			port@0 {
204 				reg = <0>;
206 					remote-endpoint = <&mdp5_intf2_out>;
219 		compatible = "qcom,dsi-phy-14nm-660";
220 		reg = <0x0c996400 0x100>,
221 				<0x0c996500 0x300>,
222 				<0x0c996800 0x188>;
223 		reg-names = "dsi_phy",
227 		#clock-cells = <1>;
228 		#phy-cells = <0>;
231 		clock-names = "iface", "ref";
237 	compatible = "qcom,mmcc-sdm660";
243 			<&mdss_dsi0_phy 0>,
245 			<&mdss_dsi1_phy 0>,
246 			<0>,
247 			<0>;
251 	compatible = "qcom,sdm660-pinctrl";