Lines Matching +full:gcc +full:- +full:sdm630
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/soc/qcom,apr.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <19200000>;
36 clock-output-names = "xo_board";
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <32764>;
43 clock-output-names = "sleep_clk";
48 #address-cells = <2>;
49 #size-cells = <0>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&PERF_CPU_SLEEP_0
61 capacity-dmips-mhz = <1126>;
62 #cooling-cells = <2>;
63 next-level-cache = <&L2_1>;
64 L2_1: l2-cache {
66 cache-level = <2>;
67 cache-unified;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 cpu-idle-states = <&PERF_CPU_SLEEP_0
81 capacity-dmips-mhz = <1126>;
82 #cooling-cells = <2>;
83 next-level-cache = <&L2_1>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 cpu-idle-states = <&PERF_CPU_SLEEP_0
96 capacity-dmips-mhz = <1126>;
97 #cooling-cells = <2>;
98 next-level-cache = <&L2_1>;
103 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 cpu-idle-states = <&PERF_CPU_SLEEP_0
111 capacity-dmips-mhz = <1126>;
112 #cooling-cells = <2>;
113 next-level-cache = <&L2_1>;
118 compatible = "arm,cortex-a53";
120 enable-method = "psci";
121 cpu-idle-states = <&PWR_CPU_SLEEP_0
126 capacity-dmips-mhz = <1024>;
127 #cooling-cells = <2>;
128 next-level-cache = <&L2_0>;
129 L2_0: l2-cache {
131 cache-level = <2>;
132 cache-unified;
138 compatible = "arm,cortex-a53";
140 enable-method = "psci";
141 cpu-idle-states = <&PWR_CPU_SLEEP_0
146 capacity-dmips-mhz = <1024>;
147 #cooling-cells = <2>;
148 next-level-cache = <&L2_0>;
153 compatible = "arm,cortex-a53";
155 enable-method = "psci";
156 cpu-idle-states = <&PWR_CPU_SLEEP_0
161 capacity-dmips-mhz = <1024>;
162 #cooling-cells = <2>;
163 next-level-cache = <&L2_0>;
168 compatible = "arm,cortex-a53";
170 enable-method = "psci";
171 cpu-idle-states = <&PWR_CPU_SLEEP_0
176 capacity-dmips-mhz = <1024>;
177 #cooling-cells = <2>;
178 next-level-cache = <&L2_0>;
181 cpu-map {
219 idle-states {
220 entry-method = "psci";
222 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
223 compatible = "arm,idle-state";
224 idle-state-name = "pwr-retention";
225 arm,psci-suspend-param = <0x40000002>;
226 entry-latency-us = <338>;
227 exit-latency-us = <423>;
228 min-residency-us = <200>;
231 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
232 compatible = "arm,idle-state";
233 idle-state-name = "pwr-power-collapse";
234 arm,psci-suspend-param = <0x40000003>;
235 entry-latency-us = <515>;
236 exit-latency-us = <1821>;
237 min-residency-us = <1000>;
238 local-timer-stop;
241 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
242 compatible = "arm,idle-state";
243 idle-state-name = "perf-retention";
244 arm,psci-suspend-param = <0x40000002>;
245 entry-latency-us = <154>;
246 exit-latency-us = <87>;
247 min-residency-us = <200>;
250 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
251 compatible = "arm,idle-state";
252 idle-state-name = "perf-power-collapse";
253 arm,psci-suspend-param = <0x40000003>;
254 entry-latency-us = <262>;
255 exit-latency-us = <301>;
256 min-residency-us = <1000>;
257 local-timer-stop;
260 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "pwr-cluster-dynamic-retention";
263 arm,psci-suspend-param = <0x400000F2>;
264 entry-latency-us = <284>;
265 exit-latency-us = <384>;
266 min-residency-us = <9987>;
267 local-timer-stop;
270 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
271 compatible = "arm,idle-state";
272 idle-state-name = "pwr-cluster-retention";
273 arm,psci-suspend-param = <0x400000F3>;
274 entry-latency-us = <338>;
275 exit-latency-us = <423>;
276 min-residency-us = <9987>;
277 local-timer-stop;
280 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
281 compatible = "arm,idle-state";
282 idle-state-name = "pwr-cluster-retention";
283 arm,psci-suspend-param = <0x400000F4>;
284 entry-latency-us = <515>;
285 exit-latency-us = <1821>;
286 min-residency-us = <9987>;
287 local-timer-stop;
290 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
291 compatible = "arm,idle-state";
292 idle-state-name = "perf-cluster-dynamic-retention";
293 arm,psci-suspend-param = <0x400000F2>;
294 entry-latency-us = <272>;
295 exit-latency-us = <329>;
296 min-residency-us = <9987>;
297 local-timer-stop;
300 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
301 compatible = "arm,idle-state";
302 idle-state-name = "perf-cluster-retention";
303 arm,psci-suspend-param = <0x400000F3>;
304 entry-latency-us = <332>;
305 exit-latency-us = <368>;
306 min-residency-us = <9987>;
307 local-timer-stop;
310 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
311 compatible = "arm,idle-state";
312 idle-state-name = "perf-cluster-retention";
313 arm,psci-suspend-param = <0x400000F4>;
314 entry-latency-us = <545>;
315 exit-latency-us = <1609>;
316 min-residency-us = <9987>;
317 local-timer-stop;
324 compatible = "qcom,scm-msm8998", "qcom,scm";
334 dsi_opp_table: opp-table-dsi {
335 compatible = "operating-points-v2";
337 opp-131250000 {
338 opp-hz = /bits/ 64 <131250000>;
339 required-opps = <&rpmpd_opp_svs>;
342 opp-210000000 {
343 opp-hz = /bits/ 64 <210000000>;
344 required-opps = <&rpmpd_opp_svs_plus>;
347 opp-262500000 {
348 opp-hz = /bits/ 64 <262500000>;
349 required-opps = <&rpmpd_opp_nom>;
354 compatible = "arm,armv8-pmuv3";
359 compatible = "arm,psci-1.0";
364 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
366 glink-edge {
367 compatible = "qcom,glink-rpm";
370 qcom,rpm-msg-ram = <&rpm_msg_ram>;
373 rpm_requests: rpm-requests {
374 compatible = "qcom,rpm-sdm660";
375 qcom,glink-channels = "rpm_requests";
377 rpmcc: clock-controller {
378 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
379 #clock-cells = <1>;
382 rpmpd: power-controller {
383 compatible = "qcom,sdm660-rpmpd";
384 #power-domain-cells = <1>;
385 operating-points-v2 = <&rpmpd_opp_table>;
387 rpmpd_opp_table: opp-table {
388 compatible = "operating-points-v2";
391 opp-level = <RPM_SMD_LEVEL_RETENTION>;
395 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
399 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
403 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
407 opp-level = <RPM_SMD_LEVEL_SVS>;
411 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
415 opp-level = <RPM_SMD_LEVEL_NOM>;
419 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
423 opp-level = <RPM_SMD_LEVEL_TURBO>;
431 reserved-memory {
432 #address-cells = <2>;
433 #size-cells = <2>;
436 wlan_msa_guard: wlan-msa-guard@85600000 {
438 no-map;
441 wlan_msa_mem: wlan-msa-mem@85700000 {
443 no-map;
446 qhee_code: qhee-code@85800000 {
448 no-map;
452 compatible = "qcom,rmtfs-mem";
454 no-map;
456 qcom,client-id = <1>;
460 smem_region: smem-mem@86000000 {
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
495 adsp_mem: adsp-region@f6000000 {
497 no-map;
500 qseecom_mem: qseecom-region@f6800000 {
502 no-map;
506 compatible = "shared-dma-pool";
508 no-map;
514 memory-region = <&smem_region>;
518 smp2p-adsp {
523 qcom,local-pid = <0>;
524 qcom,remote-pid = <2>;
526 adsp_smp2p_out: master-kernel {
527 qcom,entry-name = "master-kernel";
528 #qcom,smem-state-cells = <1>;
531 adsp_smp2p_in: slave-kernel {
532 qcom,entry-name = "slave-kernel";
533 interrupt-controller;
534 #interrupt-cells = <2>;
538 smp2p-mpss {
543 qcom,local-pid = <0>;
544 qcom,remote-pid = <1>;
546 modem_smp2p_out: master-kernel {
547 qcom,entry-name = "master-kernel";
548 #qcom,smem-state-cells = <1>;
551 modem_smp2p_in: slave-kernel {
552 qcom,entry-name = "slave-kernel";
553 interrupt-controller;
554 #interrupt-cells = <2>;
559 #address-cells = <1>;
560 #size-cells = <1>;
562 compatible = "simple-bus";
564 gcc: clock-controller@100000 {
565 compatible = "qcom,gcc-sdm630";
566 #clock-cells = <1>;
567 #reset-cells = <1>;
568 #power-domain-cells = <1>;
571 clock-names = "xo", "sleep_clk";
577 compatible = "qcom,rpm-msg-ram";
582 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
584 #address-cells = <1>;
585 #size-cells = <1>;
587 qusb2_hstx_trim: hstx-trim@240 {
592 gpu_speed_bin: gpu-speed-bin@41a0 {
599 compatible = "qcom,prng-ee";
601 clocks = <&gcc GCC_PRNG_AHB_CLK>;
602 clock-names = "core";
606 compatible = "qcom,sdm660-bimc";
608 #interconnect-cells = <1>;
617 compatible = "qcom,sdm660-cnoc";
619 #interconnect-cells = <1>;
623 compatible = "qcom,sdm660-snoc";
625 #interconnect-cells = <1>;
629 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 #global-interrupts = <2>;
632 #iommu-cells = <1>;
672 compatible = "qcom,sdm660-a2noc";
674 #interconnect-cells = <1>;
675 clock-names = "ipa",
681 <&gcc GCC_UFS_AXI_CLK>,
682 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
683 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
684 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
688 compatible = "qcom,sdm660-mnoc";
690 #interconnect-cells = <1>;
691 clock-names = "iface";
695 tsens: thermal-sensor@10ae000 {
696 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
702 interrupt-names = "uplow", "critical";
703 #thermal-sensor-cells = <1>;
707 compatible = "qcom,tcsr-mutex";
709 #hwlock-cells = <1>;
713 compatible = "qcom,sdm630-tcsr", "syscon";
718 compatible = "qcom,sdm630-pinctrl";
722 reg-names = "south", "center", "north";
724 gpio-controller;
725 gpio-ranges = <&tlmm 0 0 114>;
726 #gpio-cells = <2>;
727 interrupt-controller;
728 #interrupt-cells = <2>;
730 blsp1_uart1_default: blsp1-uart1-default-state {
733 drive-strength = <2>;
734 bias-disable;
737 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
740 drive-strength = <2>;
741 bias-disable;
744 blsp1_uart2_default: blsp1-uart2-default-state {
747 drive-strength = <2>;
748 bias-disable;
751 blsp2_uart1_default: blsp2-uart1-active-state {
752 tx-rts-pins {
755 drive-strength = <2>;
756 bias-disable;
759 rx-pins {
766 drive-strength = <2>;
767 bias-pull-up;
770 cts-pins {
774 drive-strength = <2>;
775 bias-pull-down;
779 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
780 tx-pins {
783 drive-strength = <2>;
784 bias-pull-up;
787 rx-cts-rts-pins {
790 drive-strength = <2>;
791 bias-disable;
795 i2c1_default: i2c1-default-state {
798 drive-strength = <2>;
799 bias-disable;
802 i2c1_sleep: i2c1-sleep-state {
805 drive-strength = <2>;
806 bias-pull-up;
809 i2c2_default: i2c2-default-state {
812 drive-strength = <2>;
813 bias-disable;
816 i2c2_sleep: i2c2-sleep-state {
819 drive-strength = <2>;
820 bias-pull-up;
823 i2c3_default: i2c3-default-state {
826 drive-strength = <2>;
827 bias-disable;
830 i2c3_sleep: i2c3-sleep-state {
833 drive-strength = <2>;
834 bias-pull-up;
837 i2c4_default: i2c4-default-state {
840 drive-strength = <2>;
841 bias-disable;
844 i2c4_sleep: i2c4-sleep-state {
847 drive-strength = <2>;
848 bias-pull-up;
851 i2c5_default: i2c5-default-state {
854 drive-strength = <2>;
855 bias-disable;
858 i2c5_sleep: i2c5-sleep-state {
861 drive-strength = <2>;
862 bias-pull-up;
865 i2c6_default: i2c6-default-state {
868 drive-strength = <2>;
869 bias-disable;
872 i2c6_sleep: i2c6-sleep-state {
875 drive-strength = <2>;
876 bias-pull-up;
879 i2c7_default: i2c7-default-state {
882 drive-strength = <2>;
883 bias-disable;
886 i2c7_sleep: i2c7-sleep-state {
889 drive-strength = <2>;
890 bias-pull-up;
893 i2c8_default: i2c8-default-state {
896 drive-strength = <2>;
897 bias-disable;
900 i2c8_sleep: i2c8-sleep-state {
903 drive-strength = <2>;
904 bias-pull-up;
907 cci0_default: cci0-default-state {
910 bias-pull-up;
911 drive-strength = <2>;
914 cci1_default: cci1-default-state {
917 bias-pull-up;
918 drive-strength = <2>;
921 sdc1_state_on: sdc1-on-state {
922 clk-pins {
924 bias-disable;
925 drive-strength = <16>;
928 cmd-pins {
930 bias-pull-up;
931 drive-strength = <10>;
934 data-pins {
936 bias-pull-up;
937 drive-strength = <10>;
940 rclk-pins {
942 bias-pull-down;
946 sdc1_state_off: sdc1-off-state {
947 clk-pins {
949 bias-disable;
950 drive-strength = <2>;
953 cmd-pins {
955 bias-pull-up;
956 drive-strength = <2>;
959 data-pins {
961 bias-pull-up;
962 drive-strength = <2>;
965 rclk-pins {
967 bias-pull-down;
971 sdc2_state_on: sdc2-on-state {
972 clk-pins {
974 bias-disable;
975 drive-strength = <16>;
978 cmd-pins {
980 bias-pull-up;
981 drive-strength = <10>;
984 data-pins {
986 bias-pull-up;
987 drive-strength = <10>;
991 sdc2_state_off: sdc2-off-state {
992 clk-pins {
994 bias-disable;
995 drive-strength = <2>;
998 cmd-pins {
1000 bias-pull-up;
1001 drive-strength = <2>;
1004 data-pins {
1006 bias-pull-up;
1007 drive-strength = <2>;
1013 compatible = "qcom,sdm660-mss-pil";
1015 reg-names = "qdsp6", "rmb";
1017 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1023 interrupt-names = "wdog",
1027 "stop-ack",
1028 "shutdown-ack";
1030 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1031 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1032 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1033 <&gcc GPLL0_OUT_MSSCC>,
1034 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1035 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1038 clock-names = "iface",
1047 qcom,smem-states = <&modem_smp2p_out 0>;
1048 qcom,smem-state-names = "stop";
1050 resets = <&gcc GCC_MSS_RESTART>;
1051 reset-names = "mss_restart";
1053 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1055 power-domains = <&rpmpd SDM660_VDDCX>,
1057 power-domain-names = "cx", "mx";
1059 memory-region = <&mba_region>, <&mpss_region>;
1063 glink-edge {
1066 qcom,remote-pid = <1>;
1072 compatible = "qcom,adreno-508.0", "qcom,adreno";
1075 reg-names = "kgsl_3d0_reg_memory";
1079 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1081 <&gcc GCC_BIMC_GFX_CLK>,
1082 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1086 clock-names = "iface",
1093 power-domains = <&rpmpd SDM660_VDDMX>;
1096 nvmem-cells = <&gpu_speed_bin>;
1097 nvmem-cell-names = "speed_bin";
1100 interconnect-names = "gfx-mem";
1102 operating-points-v2 = <&gpu_sdm630_opp_table>;
1106 gpu_sdm630_opp_table: opp-table {
1107 compatible = "operating-points-v2";
1108 opp-775000000 {
1109 opp-hz = /bits/ 64 <775000000>;
1110 opp-level = <RPM_SMD_LEVEL_TURBO>;
1111 opp-peak-kBps = <5412000>;
1112 opp-supported-hw = <0xa2>;
1114 opp-647000000 {
1115 opp-hz = /bits/ 64 <647000000>;
1116 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1117 opp-peak-kBps = <4068000>;
1118 opp-supported-hw = <0xff>;
1120 opp-588000000 {
1121 opp-hz = /bits/ 64 <588000000>;
1122 opp-level = <RPM_SMD_LEVEL_NOM>;
1123 opp-peak-kBps = <3072000>;
1124 opp-supported-hw = <0xff>;
1126 opp-465000000 {
1127 opp-hz = /bits/ 64 <465000000>;
1128 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1129 opp-peak-kBps = <2724000>;
1130 opp-supported-hw = <0xff>;
1132 opp-370000000 {
1133 opp-hz = /bits/ 64 <370000000>;
1134 opp-level = <RPM_SMD_LEVEL_SVS>;
1135 opp-peak-kBps = <2188000>;
1136 opp-supported-hw = <0xff>;
1138 opp-240000000 {
1139 opp-hz = /bits/ 64 <240000000>;
1140 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1141 opp-peak-kBps = <1648000>;
1142 opp-supported-hw = <0xff>;
1144 opp-160000000 {
1145 opp-hz = /bits/ 64 <160000000>;
1146 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1147 opp-peak-kBps = <1200000>;
1148 opp-supported-hw = <0xff>;
1154 compatible = "qcom,sdm630-smmu-v2",
1155 "qcom,adreno-smmu", "qcom,smmu-v2";
1165 power-domains = <&gpucc GPU_GX_GDSC>;
1166 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1167 <&gcc GCC_BIMC_GFX_CLK>,
1168 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1169 clock-names = "iface",
1172 #global-interrupts = <2>;
1173 #iommu-cells = <1>;
1191 gpucc: clock-controller@5065000 {
1192 compatible = "qcom,gpucc-sdm630";
1193 #clock-cells = <1>;
1194 #reset-cells = <1>;
1195 #power-domain-cells = <1>;
1199 <&gcc GCC_GPU_GPLL0_CLK>,
1200 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1201 clock-names = "xo",
1208 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1210 #iommu-cells = <1>;
1212 #global-interrupts = <2>;
1239 compatible = "qcom,rpm-stats";
1244 compatible = "qcom,spmi-pmic-arb";
1250 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1251 interrupt-names = "periph_irq";
1255 #address-cells = <2>;
1256 #size-cells = <0>;
1257 interrupt-controller;
1258 #interrupt-cells = <4>;
1262 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1265 #address-cells = <1>;
1266 #size-cells = <1>;
1269 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1270 <&gcc GCC_USB30_MASTER_CLK>,
1271 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1272 <&gcc GCC_USB30_SLEEP_CLK>,
1273 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1274 clock-names = "cfg_noc",
1280 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1281 <&gcc GCC_USB30_MASTER_CLK>;
1282 assigned-clock-rates = <19200000>, <120000000>;
1286 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1288 power-domains = <&gcc USB_30_GDSC>;
1289 qcom,select-utmi-as-pipe-clk;
1291 resets = <&gcc GCC_USB_30_BCR>;
1301 * SDM630 technically supports USB3 but I
1304 maximum-speed = "high-speed";
1306 phy-names = "usb2-phy";
1307 snps,hird-threshold = /bits/ 8 <0>;
1312 compatible = "qcom,sdm660-qusb2-phy";
1314 #phy-cells = <0>;
1316 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1317 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1318 clock-names = "cfg_ahb", "ref";
1320 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1321 nvmem-cells = <&qusb2_hstx_trim>;
1326 compatible = "qcom,sdm660-qusb2-phy";
1328 #phy-cells = <0>;
1330 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1331 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1332 clock-names = "cfg_ahb", "ref";
1334 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1335 nvmem-cells = <&qusb2_hstx_trim>;
1340 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1342 reg-names = "hc";
1346 interrupt-names = "hc_irq", "pwr_irq";
1348 bus-width = <4>;
1350 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1351 <&gcc GCC_SDCC2_APPS_CLK>,
1353 clock-names = "iface", "core", "xo";
1358 interconnect-names = "sdhc-ddr","cpu-sdhc";
1359 operating-points-v2 = <&sdhc2_opp_table>;
1361 pinctrl-names = "default", "sleep";
1362 pinctrl-0 = <&sdc2_state_on>;
1363 pinctrl-1 = <&sdc2_state_off>;
1364 power-domains = <&rpmpd SDM660_VDDCX>;
1368 sdhc2_opp_table: opp-table {
1369 compatible = "operating-points-v2";
1371 opp-50000000 {
1372 opp-hz = /bits/ 64 <50000000>;
1373 required-opps = <&rpmpd_opp_low_svs>;
1374 opp-peak-kBps = <200000 140000>;
1375 opp-avg-kBps = <130718 133320>;
1377 opp-100000000 {
1378 opp-hz = /bits/ 64 <100000000>;
1379 required-opps = <&rpmpd_opp_svs>;
1380 opp-peak-kBps = <250000 160000>;
1381 opp-avg-kBps = <196078 150000>;
1383 opp-200000000 {
1384 opp-hz = /bits/ 64 <200000000>;
1385 required-opps = <&rpmpd_opp_nom>;
1386 opp-peak-kBps = <4096000 4096000>;
1387 opp-avg-kBps = <1338562 1338562>;
1393 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1397 reg-names = "hc", "cqhci", "ice";
1401 interrupt-names = "hc_irq", "pwr_irq";
1403 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1404 <&gcc GCC_SDCC1_APPS_CLK>,
1406 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1407 clock-names = "iface", "core", "xo", "ice";
1411 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1412 operating-points-v2 = <&sdhc1_opp_table>;
1413 pinctrl-names = "default", "sleep";
1414 pinctrl-0 = <&sdc1_state_on>;
1415 pinctrl-1 = <&sdc1_state_off>;
1416 power-domains = <&rpmpd SDM660_VDDCX>;
1418 bus-width = <8>;
1419 non-removable;
1423 sdhc1_opp_table: opp-table {
1424 compatible = "operating-points-v2";
1426 opp-50000000 {
1427 opp-hz = /bits/ 64 <50000000>;
1428 required-opps = <&rpmpd_opp_low_svs>;
1429 opp-peak-kBps = <200000 140000>;
1430 opp-avg-kBps = <130718 133320>;
1432 opp-100000000 {
1433 opp-hz = /bits/ 64 <100000000>;
1434 required-opps = <&rpmpd_opp_svs>;
1435 opp-peak-kBps = <250000 160000>;
1436 opp-avg-kBps = <196078 150000>;
1438 opp-384000000 {
1439 opp-hz = /bits/ 64 <384000000>;
1440 required-opps = <&rpmpd_opp_nom>;
1441 opp-peak-kBps = <4096000 4096000>;
1442 opp-avg-kBps = <1338562 1338562>;
1448 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1451 #address-cells = <1>;
1452 #size-cells = <1>;
1455 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1456 <&gcc GCC_USB20_MASTER_CLK>,
1457 <&gcc GCC_USB20_SLEEP_CLK>,
1458 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1459 clock-names = "cfg_noc", "core",
1462 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1463 <&gcc GCC_USB20_MASTER_CLK>;
1464 assigned-clock-rates = <19200000>, <60000000>;
1467 interrupt-names = "hs_phy_irq";
1469 qcom,select-utmi-as-pipe-clk;
1471 resets = <&gcc GCC_USB_20_BCR>;
1480 /* This is the HS-only host */
1481 maximum-speed = "high-speed";
1483 phy-names = "usb2-phy";
1484 snps,hird-threshold = /bits/ 8 <0>;
1488 mmcc: clock-controller@c8c0000 {
1489 compatible = "qcom,mmcc-sdm630";
1491 #clock-cells = <1>;
1492 #reset-cells = <1>;
1493 #power-domain-cells = <1>;
1494 clock-names = "xo",
1506 <&gcc GCC_MMSS_GPLL0_CLK>,
1507 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1516 mdss: display-subsystem@c900000 {
1520 reg-names = "mdss_phys", "vbif_phys";
1522 power-domains = <&mmcc MDSS_GDSC>;
1528 clock-names = "iface",
1535 interrupt-controller;
1536 #interrupt-cells = <1>;
1538 #address-cells = <1>;
1539 #size-cells = <1>;
1543 mdp: display-controller@c901000 {
1544 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1546 reg-names = "mdp_phys";
1548 interrupt-parent = <&mdss>;
1551 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1553 assigned-clock-rates = <300000000>,
1559 clock-names = "iface",
1567 interconnect-names = "mdp0-mem",
1568 "mdp1-mem",
1569 "rotator-mem";
1571 operating-points-v2 = <&mdp_opp_table>;
1572 power-domains = <&rpmpd SDM660_VDDCX>;
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1581 remote-endpoint = <&mdss_dsi0_in>;
1586 mdp_opp_table: opp-table {
1587 compatible = "operating-points-v2";
1589 opp-150000000 {
1590 opp-hz = /bits/ 64 <150000000>;
1591 opp-peak-kBps = <320000 320000 76800>;
1592 required-opps = <&rpmpd_opp_low_svs>;
1594 opp-275000000 {
1595 opp-hz = /bits/ 64 <275000000>;
1596 opp-peak-kBps = <6400000 6400000 160000>;
1597 required-opps = <&rpmpd_opp_svs>;
1599 opp-300000000 {
1600 opp-hz = /bits/ 64 <300000000>;
1601 opp-peak-kBps = <6400000 6400000 190000>;
1602 required-opps = <&rpmpd_opp_svs_plus>;
1604 opp-330000000 {
1605 opp-hz = /bits/ 64 <330000000>;
1606 opp-peak-kBps = <6400000 6400000 240000>;
1607 required-opps = <&rpmpd_opp_nom>;
1609 opp-412500000 {
1610 opp-hz = /bits/ 64 <412500000>;
1611 opp-peak-kBps = <6400000 6400000 320000>;
1612 required-opps = <&rpmpd_opp_turbo>;
1618 compatible = "qcom,sdm660-dsi-ctrl",
1619 "qcom,mdss-dsi-ctrl";
1621 reg-names = "dsi_ctrl";
1623 operating-points-v2 = <&dsi_opp_table>;
1624 power-domains = <&rpmpd SDM660_VDDCX>;
1626 interrupt-parent = <&mdss>;
1629 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1631 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1643 clock-names = "mdp_core",
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1664 remote-endpoint = <&mdp5_intf1_out>;
1677 compatible = "qcom,dsi-phy-14nm-660";
1681 reg-names = "dsi_phy",
1685 #clock-cells = <1>;
1686 #phy-cells = <0>;
1689 clock-names = "iface", "ref";
1694 blsp1_dma: dma-controller@c144000 {
1695 compatible = "qcom,bam-v1.7.0";
1698 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1699 clock-names = "bam_clk";
1700 #dma-cells = <1>;
1702 qcom,controlled-remotely;
1703 num-channels = <18>;
1704 qcom,num-ees = <4>;
1708 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1711 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1712 <&gcc GCC_BLSP1_AHB_CLK>;
1713 clock-names = "core", "iface";
1715 dma-names = "tx", "rx";
1716 pinctrl-names = "default", "sleep";
1717 pinctrl-0 = <&blsp1_uart1_default>;
1718 pinctrl-1 = <&blsp1_uart1_sleep>;
1723 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1726 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1727 <&gcc GCC_BLSP1_AHB_CLK>;
1728 clock-names = "core", "iface";
1730 dma-names = "tx", "rx";
1731 pinctrl-names = "default";
1732 pinctrl-0 = <&blsp1_uart2_default>;
1737 compatible = "qcom,i2c-qup-v2.2.1";
1741 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1742 <&gcc GCC_BLSP1_AHB_CLK>;
1743 clock-names = "core", "iface";
1744 clock-frequency = <400000>;
1746 dma-names = "tx", "rx";
1748 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&i2c1_default>;
1750 pinctrl-1 = <&i2c1_sleep>;
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1757 compatible = "qcom,i2c-qup-v2.2.1";
1761 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1762 <&gcc GCC_BLSP1_AHB_CLK>;
1763 clock-names = "core", "iface";
1764 clock-frequency = <400000>;
1766 dma-names = "tx", "rx";
1768 pinctrl-names = "default", "sleep";
1769 pinctrl-0 = <&i2c2_default>;
1770 pinctrl-1 = <&i2c2_sleep>;
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1777 compatible = "qcom,i2c-qup-v2.2.1";
1781 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1782 <&gcc GCC_BLSP1_AHB_CLK>;
1783 clock-names = "core", "iface";
1784 clock-frequency = <400000>;
1786 dma-names = "tx", "rx";
1788 pinctrl-names = "default", "sleep";
1789 pinctrl-0 = <&i2c3_default>;
1790 pinctrl-1 = <&i2c3_sleep>;
1791 #address-cells = <1>;
1792 #size-cells = <0>;
1797 compatible = "qcom,i2c-qup-v2.2.1";
1801 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1802 <&gcc GCC_BLSP1_AHB_CLK>;
1803 clock-names = "core", "iface";
1804 clock-frequency = <400000>;
1806 dma-names = "tx", "rx";
1808 pinctrl-names = "default", "sleep";
1809 pinctrl-0 = <&i2c4_default>;
1810 pinctrl-1 = <&i2c4_sleep>;
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1816 blsp2_dma: dma-controller@c184000 {
1817 compatible = "qcom,bam-v1.7.0";
1820 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1821 clock-names = "bam_clk";
1822 #dma-cells = <1>;
1824 qcom,controlled-remotely;
1825 num-channels = <18>;
1826 qcom,num-ees = <4>;
1830 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1833 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1834 <&gcc GCC_BLSP2_AHB_CLK>;
1835 clock-names = "core", "iface";
1837 dma-names = "tx", "rx";
1838 pinctrl-names = "default", "sleep";
1839 pinctrl-0 = <&blsp2_uart1_default>;
1840 pinctrl-1 = <&blsp2_uart1_sleep>;
1845 compatible = "qcom,i2c-qup-v2.2.1";
1849 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1850 <&gcc GCC_BLSP2_AHB_CLK>;
1851 clock-names = "core", "iface";
1852 clock-frequency = <400000>;
1854 dma-names = "tx", "rx";
1856 pinctrl-names = "default", "sleep";
1857 pinctrl-0 = <&i2c5_default>;
1858 pinctrl-1 = <&i2c5_sleep>;
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1865 compatible = "qcom,i2c-qup-v2.2.1";
1869 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1870 <&gcc GCC_BLSP2_AHB_CLK>;
1871 clock-names = "core", "iface";
1872 clock-frequency = <400000>;
1874 dma-names = "tx", "rx";
1876 pinctrl-names = "default", "sleep";
1877 pinctrl-0 = <&i2c6_default>;
1878 pinctrl-1 = <&i2c6_sleep>;
1879 #address-cells = <1>;
1880 #size-cells = <0>;
1885 compatible = "qcom,i2c-qup-v2.2.1";
1889 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1890 <&gcc GCC_BLSP2_AHB_CLK>;
1891 clock-names = "core", "iface";
1892 clock-frequency = <400000>;
1894 dma-names = "tx", "rx";
1896 pinctrl-names = "default", "sleep";
1897 pinctrl-0 = <&i2c7_default>;
1898 pinctrl-1 = <&i2c7_sleep>;
1899 #address-cells = <1>;
1900 #size-cells = <0>;
1905 compatible = "qcom,i2c-qup-v2.2.1";
1909 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1910 <&gcc GCC_BLSP2_AHB_CLK>;
1911 clock-names = "core", "iface";
1912 clock-frequency = <400000>;
1914 dma-names = "tx", "rx";
1916 pinctrl-names = "default", "sleep";
1917 pinctrl-0 = <&i2c8_default>;
1918 pinctrl-1 = <&i2c8_sleep>;
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1925 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1928 #address-cells = <1>;
1929 #size-cells = <1>;
1933 pil-reloc@94c {
1934 compatible = "qcom,pil-reloc-info";
1940 compatible = "qcom,sdm660-camss";
1955 reg-names = "csi_clk_mux",
1979 interrupt-names = "csid0",
2031 clock-names = "ahb",
2074 interconnect-names = "vfe-mem";
2079 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2084 #address-cells = <1>;
2085 #size-cells = <0>;
2090 compatible = "qcom,msm8996-cci";
2091 #address-cells = <1>;
2092 #size-cells = <0>;
2096 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2098 assigned-clock-rates = <80800000>, <37500000>;
2103 clock-names = "camss_top_ahb",
2108 pinctrl-names = "default";
2109 pinctrl-0 = <&cci0_default &cci1_default>;
2110 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2113 cci_i2c0: i2c-bus@0 {
2115 clock-frequency = <400000>;
2116 #address-cells = <1>;
2117 #size-cells = <0>;
2120 cci_i2c1: i2c-bus@1 {
2122 clock-frequency = <400000>;
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2128 venus: video-codec@cc00000 {
2129 compatible = "qcom,sdm660-venus";
2135 clock-names = "core", "iface", "bus", "bus_throttle";
2138 interconnect-names = "cpu-cfg", "video-mem";
2160 memory-region = <&venus_region>;
2161 power-domains = <&mmcc VENUS_GDSC>;
2164 video-decoder {
2165 compatible = "venus-decoder";
2167 clock-names = "vcodec0_core";
2168 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2171 video-encoder {
2172 compatible = "venus-encoder";
2174 clock-names = "vcodec0_core";
2175 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2180 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2186 clock-names = "iface-mm", "iface-smmu",
2187 "bus-smmu";
2188 #global-interrupts = <2>;
2189 #iommu-cells = <1>;
2224 compatible = "qcom,sdm660-adsp-pas";
2227 interrupts-extended =
2233 interrupt-names = "wdog", "fatal", "ready",
2234 "handover", "stop-ack";
2237 clock-names = "xo";
2239 memory-region = <&adsp_region>;
2240 power-domains = <&rpmpd SDM660_VDDCX>;
2241 power-domain-names = "cx";
2243 qcom,smem-states = <&adsp_smp2p_out 0>;
2244 qcom,smem-state-names = "stop";
2246 glink-edge {
2251 qcom,remote-pid = <2>;
2254 compatible = "qcom,apr-v2";
2255 qcom,glink-channels = "apr_audio_svc";
2257 #address-cells = <1>;
2258 #size-cells = <0>;
2269 compatible = "qcom,q6afe-dais";
2270 #address-cells = <1>;
2271 #size-cells = <0>;
2272 #sound-dai-cells = <1>;
2280 compatible = "qcom,q6asm-dais";
2281 #address-cells = <1>;
2282 #size-cells = <0>;
2283 #sound-dai-cells = <1>;
2292 compatible = "qcom,q6adm-routing";
2293 #sound-dai-cells = <0>;
2301 compatible = "qcom,sdm660-gnoc";
2303 #interconnect-cells = <1>;
2307 compatible = "qcom,sdm660-apcs-hmss-global",
2308 "qcom,msm8994-apcs-kpss-global";
2311 #mbox-cells = <1>;
2315 #address-cells = <1>;
2316 #size-cells = <1>;
2318 compatible = "arm,armv7-timer-mem";
2320 clock-frequency = <19200000>;
2323 frame-number = <0>;
2331 frame-number = <1>;
2338 frame-number = <2>;
2345 frame-number = <3>;
2352 frame-number = <4>;
2359 frame-number = <5>;
2366 frame-number = <6>;
2373 intc: interrupt-controller@17a00000 {
2374 compatible = "arm,gic-v3";
2377 #interrupt-cells = <3>;
2378 #address-cells = <1>;
2379 #size-cells = <1>;
2381 interrupt-controller;
2382 #redistributor-regions = <1>;
2383 redistributor-stride = <0x0 0x20000>;
2391 thermal-zones {
2392 aoss-thermal {
2393 polling-delay-passive = <250>;
2394 polling-delay = <1000>;
2396 thermal-sensors = <&tsens 0>;
2399 aoss_alert0: trip-point0 {
2407 cpuss0-thermal {
2408 polling-delay-passive = <250>;
2409 polling-delay = <1000>;
2411 thermal-sensors = <&tsens 1>;
2414 cpuss0_alert0: trip-point0 {
2422 cpuss1-thermal {
2423 polling-delay-passive = <250>;
2424 polling-delay = <1000>;
2426 thermal-sensors = <&tsens 2>;
2429 cpuss1_alert0: trip-point0 {
2437 cpu0-thermal {
2438 polling-delay-passive = <250>;
2439 polling-delay = <1000>;
2441 thermal-sensors = <&tsens 3>;
2444 cpu0_alert0: trip-point0 {
2450 cpu0_crit: cpu-crit {
2458 cpu1-thermal {
2459 polling-delay-passive = <250>;
2460 polling-delay = <1000>;
2462 thermal-sensors = <&tsens 4>;
2465 cpu1_alert0: trip-point0 {
2471 cpu1_crit: cpu-crit {
2479 cpu2-thermal {
2480 polling-delay-passive = <250>;
2481 polling-delay = <1000>;
2483 thermal-sensors = <&tsens 5>;
2486 cpu2_alert0: trip-point0 {
2492 cpu2_crit: cpu-crit {
2500 cpu3-thermal {
2501 polling-delay-passive = <250>;
2502 polling-delay = <1000>;
2504 thermal-sensors = <&tsens 6>;
2507 cpu3_alert0: trip-point0 {
2513 cpu3_crit: cpu-crit {
2527 pwr-cluster-thermal {
2528 polling-delay-passive = <250>;
2529 polling-delay = <1000>;
2531 thermal-sensors = <&tsens 7>;
2534 pwr_cluster_alert0: trip-point0 {
2540 pwr_cluster_crit: cpu-crit {
2548 gpu-thermal {
2549 polling-delay-passive = <250>;
2550 polling-delay = <1000>;
2552 thermal-sensors = <&tsens 8>;
2555 gpu_alert0: trip-point0 {
2565 compatible = "arm,armv8-timer";