Lines Matching +full:1 +full:a98000
144 clocks = <&cpufreq_hw 1>;
150 qcom,freq-domain = <&cpufreq_hw 1>;
166 clocks = <&cpufreq_hw 1>;
172 qcom,freq-domain = <&cpufreq_hw 1>;
188 clocks = <&cpufreq_hw 1>;
194 qcom,freq-domain = <&cpufreq_hw 1>;
210 clocks = <&cpufreq_hw 1>;
216 qcom,freq-domain = <&cpufreq_hw 1>;
277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
719 #qcom,smem-state-cells = <1>;
743 #qcom,smem-state-cells = <1>;
767 #qcom,smem-state-cells = <1>;
817 #clock-cells = <1>;
818 #reset-cells = <1>;
819 #power-domain-cells = <1>;
882 #address-cells = <1>;
898 #address-cells = <1>;
914 #address-cells = <1>;
930 #address-cells = <1>;
960 #address-cells = <1>;
976 #address-cells = <1>;
992 #address-cells = <1>;
1008 #address-cells = <1>;
1024 #address-cells = <1>;
1040 #address-cells = <1>;
1059 #address-cells = <1>;
1072 #address-cells = <1>;
1088 #address-cells = <1>;
1104 #address-cells = <1>;
1120 #address-cells = <1>;
1136 #address-cells = <1>;
1167 #address-cells = <1>;
1183 #address-cells = <1>;
1199 #address-cells = <1>;
1215 #address-cells = <1>;
1231 #address-cells = <1>;
1247 #address-cells = <1>;
1277 #address-cells = <1>;
1293 #address-cells = <1>;
1312 #address-cells = <1>;
1325 #address-cells = <1>;
1341 #address-cells = <1>;
1357 #address-cells = <1>;
1373 #address-cells = <1>;
1389 #address-cells = <1>;
1405 #address-cells = <1>;
1421 #address-cells = <1>;
1452 #address-cells = <1>;
1468 #address-cells = <1>;
1484 #address-cells = <1>;
1500 #address-cells = <1>;
1516 #address-cells = <1>;
1532 #address-cells = <1>;
1548 #address-cells = <1>;
1564 #address-cells = <1>;
1580 #address-cells = <1>;
1596 #address-cells = <1>;
1612 #address-cells = <1>;
1628 #address-cells = <1>;
1641 i2c14: i2c@a98000 {
1644 #address-cells = <1>;
1657 spi14: spi@a98000 {
1660 #address-cells = <1>;
1676 #address-cells = <1>;
1692 #address-cells = <1>;
1713 pcie4: pcie@1c00000 {
1732 num-lanes = <1>;
1740 #interrupt-cells = <1>;
1742 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1784 pcie4_phy: phy@1c06000 {
1813 pcie3b: pcie@1c08000 {
1840 #interrupt-cells = <1>;
1842 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1882 pcie3b_phy: phy@1c0e000 {
1911 pcie3a: pcie@1c10000 {
1938 #interrupt-cells = <1>;
1940 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1980 pcie3a_phy: phy@1c14000 {
2002 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2012 pcie2b: pcie@1c18000 {
2039 #interrupt-cells = <1>;
2041 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2081 pcie2b_phy: phy@1c1e000 {
2110 pcie2a: pcie@1c20000 {
2137 #interrupt-cells = <1>;
2139 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2179 pcie2a_phy: phy@1c24000 {
2211 ufs_mem_hc: ufs@1d84000 {
2219 #reset-cells = <1>;
2256 ufs_mem_phy: phy@1d87000 {
2274 ufs_card_hc: ufs@1da4000 {
2282 #reset-cells = <1>;
2318 ufs_card_phy: phy@1da7000 {
2336 tcsr_mutex: hwlock@1f40000 {
2339 #hwlock-cells = <1>;
2342 tcsr: syscon@1fc0000 {
2357 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2476 #clock-cells = <1>;
2477 #reset-cells = <1>;
2478 #power-domain-cells = <1>;
2640 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2678 #address-cells = <1>;
2681 q6apm: service@1 {
2694 #sound-dai-cells = <1>;
2727 #sound-dai-cells = <1>;
2758 #sound-dai-cells = <1>;
2783 #sound-dai-cells = <1>;
2803 #sound-dai-cells = <1>;
2834 #sound-dai-cells = <1>;
2844 #clock-cells = <1>;
2845 #reset-cells = <1>;
2860 #sound-dai-cells = <1>;
2892 #sound-dai-cells = <1>;
2916 slew-rate = <1>;
2924 slew-rate = <1>;
2934 slew-rate = <1>;
2942 slew-rate = <1>;
3020 slew-rate = <1>;
3028 slew-rate = <1>;
3038 slew-rate = <1>;
3046 slew-rate = <1>;
3055 #clock-cells = <1>;
3056 #reset-cells = <1>;
3118 #clock-cells = <1>;
3119 #phy-cells = <1>;
3124 #address-cells = <1>;
3171 #clock-cells = <1>;
3172 #phy-cells = <1>;
3177 #address-cells = <1>;
3206 #clock-cells = <1>;
3224 #clock-cells = <1>;
3246 opp-1 {
3300 opp-1 {
3463 #clock-cells = <1>;
3464 #reset-cells = <1>;
3465 #power-domain-cells = <1>;
3488 #interrupt-cells = <1>;
3522 #address-cells = <1>;
3618 #address-cells = <1>;
3629 port@1 {
3630 reg = <1>;
3696 #address-cells = <1>;
3707 port@1 {
3708 reg = <1>;
3764 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3772 #address-cells = <1>;
3782 port@1 {
3783 reg = <1>;
3836 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3844 #address-cells = <1>;
3854 port@1 {
3855 reg = <1>;
3897 #clock-cells = <1>;
3915 #clock-cells = <1>;
3933 <&mdss0_dp2_phy 1>,
3935 <&mdss0_dp3_phy 1>,
3942 #clock-cells = <1>;
3943 #power-domain-cells = <1>;
3944 #reset-cells = <1>;
3954 <54 263 1>,
3960 <69 86 1>,
3963 <159 638 1>,
3965 <168 801 1>,
3968 <201 449 1>,
3969 <202 89 1>,
3970 <203 451 1>,
3971 <204 462 1>,
3972 <205 264 1>,
3973 <206 579 1>,
3974 <207 653 1>,
3975 <208 656 1>,
3976 <209 659 1>,
3977 <210 122 1>,
3978 <211 699 1>,
3979 <212 705 1>,
3980 <213 450 1>,
3981 <214 643 1>,
3986 <232 269 1>,
3987 <233 377 1>,
3988 <234 372 1>,
3989 <235 138 1>,
3990 <236 857 1>,
3991 <237 860 1>,
3992 <238 137 1>,
3993 <239 668 1>,
3994 <240 366 1>,
3995 <241 949 1>,
3997 <247 769 1>,
3998 <248 768 1>,
3999 <249 663 1>,
4001 <252 798 1>,
4002 <253 765 1>,
4003 <254 763 1>,
4004 <255 454 1>,
4005 <258 139 1>,
4022 #thermal-sensor-cells = <1>;
4033 #thermal-sensor-cells = <1>;
4060 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4225 #redistributor-regions = <1>;
4236 #msi-cells = <1>;
4250 #address-cells = <1>;
4251 #size-cells = <1>;
4263 frame-number = <1>;
4310 reg-names = "drv-0", "drv-1", "drv-2";
4317 <WAKE_TCS 3>, <CONTROL_TCS 1>;
4327 #clock-cells = <1>;
4334 #power-domain-cells = <1>;
4390 #interconnect-cells = <1>;
4402 #freq-domain-cells = <1>;
4403 #clock-cells = <1>;
4406 remoteproc_nsp0: remoteproc@1b300000 {
4412 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
4447 #address-cells = <1>;
4450 compute-cb@1 {
4452 reg = <1>;
4543 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
4597 #interrupt-cells = <1>;
4631 #address-cells = <1>;
4716 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4724 #address-cells = <1>;
4734 port@1 {
4735 reg = <1>;
4788 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4796 #address-cells = <1>;
4806 port@1 {
4807 reg = <1>;
4860 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4868 #address-cells = <1>;
4878 port@1 {
4879 reg = <1>;
4932 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4940 #address-cells = <1>;
4950 port@1 {
4951 reg = <1>;
4993 #clock-cells = <1>;
5011 #clock-cells = <1>;
5025 <&mdss1_dp0_phy 1>,
5027 <&mdss1_dp1_phy 1>,
5029 <&mdss1_dp2_phy 1>,
5031 <&mdss1_dp3_phy 1>,
5038 #clock-cells = <1>;
5039 #power-domain-cells = <1>;
5040 #reset-cells = <1>;
5084 thermal-sensors = <&tsens0 1>;