Lines Matching +full:0 +full:x0c600000
33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
78 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
99 reg = <0x0 0x200>;
100 clocks = <&cpufreq_hw 0>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
121 reg = <0x0 0x300>;
122 clocks = <&cpufreq_hw 0>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
143 reg = <0x0 0x400>;
165 reg = <0x0 0x500>;
187 reg = <0x0 0x600>;
209 reg = <0x0 0x700>;
267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
270 arm,psci-suspend-param = <0x40000004>;
277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
280 arm,psci-suspend-param = <0x40000004>;
289 CLUSTER_SLEEP_0: cluster-sleep-0 {
291 arm,psci-suspend-param = <0x4100c344>;
302 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
381 reg = <0x0 0x80000000 0x0 0x0>;
588 #power-domain-cells = <0>;
594 #power-domain-cells = <0>;
600 #power-domain-cells = <0>;
606 #power-domain-cells = <0>;
612 #power-domain-cells = <0>;
618 #power-domain-cells = <0>;
624 #power-domain-cells = <0>;
630 #power-domain-cells = <0>;
636 #power-domain-cells = <0>;
647 reg = <0 0x80000000 0 0x860000>;
653 reg = <0 0x80860000 0 0x20000>;
658 reg = <0 0x80880000 0 0x80000>;
664 reg = <0 0x80900000 0 0x200000>;
670 reg = <0 0x80b00000 0 0x100000>;
675 reg = <0 0x83b00000 0 0x1700000>;
680 reg = <0 0x85b00000 0 0xc00000>;
685 reg = <0 0x86c00000 0 0x2000000>;
690 reg = <0 0x8a100000 0 0x1e00000>;
695 reg = <0 0x8c600000 0 0x1e00000>;
700 reg = <0 0xaeb00000 0 0x16600000>;
714 qcom,local-pid = <0>;
738 qcom,local-pid = <0>;
762 qcom,local-pid = <0>;
777 soc: soc@0 {
781 ranges = <0 0 0 0 0x10 0>;
782 dma-ranges = <0 0 0 0 0x10 0>;
786 reg = <0x0 0x00020000 0x0 0x10000>,
787 <0x0 0x00036000 0x0 0x100>;
803 iommus = <&apps_smmu 0x4c0 0xf>;
816 reg = <0x0 0x00100000 0x0 0x1f0000>;
822 <0>,
823 <0>,
824 <0>,
825 <0>,
826 <0>,
827 <0>,
829 <0>,
830 <0>,
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <0>,
837 <0>,
838 <0>,
839 <0>,
840 <0>,
841 <0>,
842 <0>,
843 <0>,
844 <0>,
845 <0>,
851 <0>,
852 <0>;
858 reg = <0 0x00408000 0 0x1000>;
867 reg = <0 0x008c0000 0 0x2000>;
871 iommus = <&apps_smmu 0xa3 0>;
881 reg = <0 0x00880000 0 0x4000>;
883 #size-cells = <0>;
888 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
889 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
890 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
897 reg = <0 0x00880000 0 0x4000>;
899 #size-cells = <0>;
904 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
906 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
913 reg = <0 0x00884000 0 0x4000>;
915 #size-cells = <0>;
920 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
922 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
929 reg = <0 0x00884000 0 0x4000>;
931 #size-cells = <0>;
936 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
938 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
945 reg = <0 0x00884000 0 0x4000>;
951 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
959 reg = <0 0x00888000 0 0x4000>;
961 #size-cells = <0>;
966 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
967 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
968 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
975 reg = <0 0x00888000 0 0x4000>;
977 #size-cells = <0>;
982 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
983 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
984 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
991 reg = <0 0x0088c000 0 0x4000>;
993 #size-cells = <0>;
998 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
999 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1000 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1007 reg = <0 0x0088c000 0 0x4000>;
1009 #size-cells = <0>;
1014 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1016 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1023 reg = <0 0x00890000 0 0x4000>;
1025 #size-cells = <0>;
1030 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1031 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1032 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1039 reg = <0 0x00890000 0 0x4000>;
1041 #size-cells = <0>;
1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1048 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1055 reg = <0 0x00894000 0 0x4000>;
1060 #size-cells = <0>;
1062 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1064 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1071 reg = <0 0x00894000 0 0x4000>;
1073 #size-cells = <0>;
1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1080 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1087 reg = <0 0x00898000 0 0x4000>;
1089 #size-cells = <0>;
1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1096 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1103 reg = <0 0x00898000 0 0x4000>;
1105 #size-cells = <0>;
1110 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1111 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1112 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1119 reg = <0 0x0089c000 0 0x4000>;
1121 #size-cells = <0>;
1126 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1127 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1128 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1135 reg = <0 0x0089c000 0 0x4000>;
1137 #size-cells = <0>;
1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1143 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1144 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1152 reg = <0 0x009c0000 0 0x6000>;
1156 iommus = <&apps_smmu 0x563 0>;
1166 reg = <0 0x00980000 0 0x4000>;
1168 #size-cells = <0>;
1173 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1175 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1182 reg = <0 0x00980000 0 0x4000>;
1184 #size-cells = <0>;
1189 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1190 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1191 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1198 reg = <0 0x00984000 0 0x4000>;
1200 #size-cells = <0>;
1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1207 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1214 reg = <0 0x00984000 0 0x4000>;
1216 #size-cells = <0>;
1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1223 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 reg = <0 0x00988000 0 0x4000>;
1232 #size-cells = <0>;
1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1239 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1246 reg = <0 0x00988000 0 0x4000>;
1248 #size-cells = <0>;
1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1262 reg = <0 0x00988000 0 0x4000>;
1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1276 reg = <0 0x0098c000 0 0x4000>;
1278 #size-cells = <0>;
1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1284 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1285 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1292 reg = <0 0x0098c000 0 0x4000>;
1294 #size-cells = <0>;
1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1301 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1308 reg = <0 0x00990000 0 0x4000>;
1313 #size-cells = <0>;
1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1317 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1324 reg = <0 0x00990000 0 0x4000>;
1326 #size-cells = <0>;
1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1333 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1340 reg = <0 0x00994000 0 0x4000>;
1342 #size-cells = <0>;
1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1349 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1356 reg = <0 0x00994000 0 0x4000>;
1358 #size-cells = <0>;
1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1372 reg = <0 0x00998000 0 0x4000>;
1374 #size-cells = <0>;
1379 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1380 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1381 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1388 reg = <0 0x00998000 0 0x4000>;
1390 #size-cells = <0>;
1395 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1396 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1397 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1404 reg = <0 0x0099c000 0 0x4000>;
1406 #size-cells = <0>;
1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1413 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1420 reg = <0 0x0099c000 0 0x4000>;
1422 #size-cells = <0>;
1427 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1428 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1429 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1437 reg = <0 0x00ac0000 0 0x6000>;
1441 iommus = <&apps_smmu 0x83 0>;
1451 reg = <0 0x00a80000 0 0x4000>;
1453 #size-cells = <0>;
1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1459 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1460 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1467 reg = <0 0x00a80000 0 0x4000>;
1469 #size-cells = <0>;
1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1475 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1476 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1483 reg = <0 0x00a84000 0 0x4000>;
1485 #size-cells = <0>;
1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1491 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1492 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1499 reg = <0 0x00a84000 0 0x4000>;
1501 #size-cells = <0>;
1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1508 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1515 reg = <0 0x00a88000 0 0x4000>;
1517 #size-cells = <0>;
1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1524 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1531 reg = <0 0x00a88000 0 0x4000>;
1533 #size-cells = <0>;
1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1539 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1540 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1547 reg = <0 0x00a8c000 0 0x4000>;
1549 #size-cells = <0>;
1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1555 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1556 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1563 reg = <0 0x00a8c000 0 0x4000>;
1565 #size-cells = <0>;
1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1572 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1579 reg = <0 0x00a90000 0 0x4000>;
1581 #size-cells = <0>;
1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1587 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1588 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1595 reg = <0 0x00a90000 0 0x4000>;
1597 #size-cells = <0>;
1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1603 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1604 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1611 reg = <0 0x00a94000 0 0x4000>;
1613 #size-cells = <0>;
1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1619 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1620 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1627 reg = <0 0x00a94000 0 0x4000>;
1629 #size-cells = <0>;
1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1635 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1636 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1643 reg = <0 0x00a98000 0 0x4000>;
1645 #size-cells = <0>;
1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1651 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1652 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1659 reg = <0 0x00a98000 0 0x4000>;
1661 #size-cells = <0>;
1666 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1667 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1668 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1675 reg = <0 0x00a9c000 0 0x4000>;
1677 #size-cells = <0>;
1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1683 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1684 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1691 reg = <0 0x00a9c000 0 0x4000>;
1693 #size-cells = <0>;
1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1699 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1700 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1708 reg = <0 0x010d3000 0 0x1000>;
1716 reg = <0x0 0x01c00000 0x0 0x3000>,
1717 <0x0 0x30000000 0x0 0xf1d>,
1718 <0x0 0x30000f20 0x0 0xa8>,
1719 <0x0 0x30001000 0x0 0x1000>,
1720 <0x0 0x30100000 0x0 0x100000>,
1721 <0x0 0x01c03000 0x0 0x1000>;
1725 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1726 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1727 bus-range = <0x00 0xff>;
1741 interrupt-map-mask = <0 0 0 0x7>;
1742 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1743 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1744 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1745 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1770 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1786 reg = <0x0 0x01c06000 0x0 0x2000>;
1805 #clock-cells = <0>;
1808 #phy-cells = <0>;
1816 reg = <0x0 0x01c08000 0x0 0x3000>,
1817 <0x0 0x32000000 0x0 0xf1d>,
1818 <0x0 0x32000f20 0x0 0xa8>,
1819 <0x0 0x32001000 0x0 0x1000>,
1820 <0x0 0x32100000 0x0 0x100000>,
1821 <0x0 0x01c0b000 0x0 0x1000>;
1825 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1826 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1827 bus-range = <0x00 0xff>;
1841 interrupt-map-mask = <0 0 0 0x7>;
1842 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1843 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1844 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1845 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1867 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1868 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1884 reg = <0x0 0x01c0e000 0x0 0x2000>;
1903 #clock-cells = <0>;
1906 #phy-cells = <0>;
1914 reg = <0x0 0x01c10000 0x0 0x3000>,
1915 <0x0 0x34000000 0x0 0xf1d>,
1916 <0x0 0x34000f20 0x0 0xa8>,
1917 <0x0 0x34001000 0x0 0x1000>,
1918 <0x0 0x34100000 0x0 0x100000>,
1919 <0x0 0x01c13000 0x0 0x1000>;
1923 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1924 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1925 bus-range = <0x00 0xff>;
1939 interrupt-map-mask = <0 0 0 0x7>;
1940 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1941 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1942 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1943 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1965 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1982 reg = <0x0 0x01c14000 0x0 0x2000>,
1983 <0x0 0x01c16000 0x0 0x2000>;
2002 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2004 #clock-cells = <0>;
2007 #phy-cells = <0>;
2015 reg = <0x0 0x01c18000 0x0 0x3000>,
2016 <0x0 0x38000000 0x0 0xf1d>,
2017 <0x0 0x38000f20 0x0 0xa8>,
2018 <0x0 0x38001000 0x0 0x1000>,
2019 <0x0 0x38100000 0x0 0x100000>,
2020 <0x0 0x01c1b000 0x0 0x1000>;
2024 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2025 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2026 bus-range = <0x00 0xff>;
2040 interrupt-map-mask = <0 0 0 0x7>;
2041 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2042 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2043 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2044 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2066 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2083 reg = <0x0 0x01c1e000 0x0 0x2000>;
2102 #clock-cells = <0>;
2105 #phy-cells = <0>;
2113 reg = <0x0 0x01c20000 0x0 0x3000>,
2114 <0x0 0x3c000000 0x0 0xf1d>,
2115 <0x0 0x3c000f20 0x0 0xa8>,
2116 <0x0 0x3c001000 0x0 0x1000>,
2117 <0x0 0x3c100000 0x0 0x100000>,
2118 <0x0 0x01c23000 0x0 0x1000>;
2122 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2123 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2124 bus-range = <0x00 0xff>;
2138 interrupt-map-mask = <0 0 0 0x7>;
2139 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2140 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2141 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2142 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2164 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2181 reg = <0x0 0x01c24000 0x0 0x2000>,
2182 <0x0 0x01c26000 0x0 0x2000>;
2201 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2203 #clock-cells = <0>;
2206 #phy-cells = <0>;
2214 reg = <0 0x01d84000 0 0x3000>;
2226 iommus = <&apps_smmu 0xe0 0x0>;
2246 <0 0>,
2247 <0 0>,
2249 <0 0>,
2250 <0 0>,
2251 <0 0>,
2252 <0 0>;
2258 reg = <0 0x01d87000 0 0x1000>;
2266 resets = <&ufs_mem_hc 0>;
2269 #phy-cells = <0>;
2277 reg = <0 0x01da4000 0 0x3000>;
2288 iommus = <&apps_smmu 0x4a0 0x0>;
2308 <0 0>,
2309 <0 0>,
2311 <0 0>,
2312 <0 0>,
2313 <0 0>,
2314 <0 0>;
2320 reg = <0 0x01da7000 0 0x1000>;
2328 resets = <&ufs_card_hc 0>;
2331 #phy-cells = <0>;
2338 reg = <0x0 0x01f40000 0x0 0x20000>;
2344 reg = <0x0 0x01fc0000 0x0 0x30000>;
2350 reg = <0 0x03d00000 0 0x40000>,
2351 <0 0x03d9e000 0 0x1000>,
2352 <0 0x03d61000 0 0x800>;
2357 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2361 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2422 reg = <0 0x03d6a000 0 0x34000>,
2423 <0 0x03de0000 0 0x10000>,
2424 <0 0x0b290000 0 0x10000>;
2447 iommus = <&gpu_smmu 5 0xc00>;
2467 reg = <0 0x03d90000 0 0x9000>;
2484 reg = <0 0x03da0000 0 0x20000>;
2524 reg = <0 0x088e5000 0 0x400>;
2529 #phy-cells = <0>;
2537 reg = <0 0x088e7000 0 0x400>;
2542 #phy-cells = <0>;
2550 reg = <0 0x088e8000 0 0x400>;
2555 #phy-cells = <0>;
2563 reg = <0 0x088e9000 0 0x400>;
2568 #phy-cells = <0>;
2576 reg = <0 0x088ea000 0 0x400>;
2581 #phy-cells = <0>;
2588 reg = <0 0x088ef000 0 0x2000>;
2602 #clock-cells = <0>;
2605 #phy-cells = <0>;
2612 reg = <0 0x088f1000 0 0x2000>;
2626 #clock-cells = <0>;
2629 #phy-cells = <0>;
2636 reg = <0 0x03000000 0 0x100>;
2639 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2658 qcom,smem-states = <&smp2p_adsp_out 0>;
2679 #size-cells = <0>;
2684 #sound-dai-cells = <0>;
2689 iommus = <&apps_smmu 0x0c01 0x0>;
2714 reg = <0 0x03200000 0 0x1000>;
2726 #clock-cells = <0>;
2730 pinctrl-0 = <&rx_swr_default>;
2737 reg = <0 0x03210000 0 0x2000>;
2745 qcom,din-ports = <0>;
2748 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2749 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2750 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2751 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2752 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2753 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2754 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2755 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2756 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2760 #size-cells = <0>;
2767 reg = <0 0x03220000 0 0x1000>;
2769 pinctrl-0 = <&tx_swr_default>;
2782 #clock-cells = <0>;
2790 reg = <0 0x03240000 0 0x1000>;
2801 #clock-cells = <0>;
2806 pinctrl-0 = <&wsa_swr_default>;
2812 reg = <0 0x03250000 0 0x2000>;
2824 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2825 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2826 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2827 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2828 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2829 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2830 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2831 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2832 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2836 #size-cells = <0>;
2843 reg = <0 0x032a9000 0 0x1000>;
2850 reg = <0 0x03330000 0 0x2000>;
2862 #size-cells = <0>;
2865 qcom,dout-ports = <0>;
2866 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2867 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2868 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2869 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2870 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2871 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2872 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2873 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2874 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2881 reg = <0 0x03370000 0 0x1000>;
2890 #clock-cells = <0>;
2899 reg = <0 0x33c0000 0x0 0x20000>,
2900 <0 0x3550000 0x0 0x10000>;
2903 gpio-ranges = <&lpass_tlmm 0 0 19>;
3054 reg = <0 0x033e0000 0 0x12000>;
3061 reg = <0 0x08804000 0 0x1000>;
3072 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3073 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3075 iommus = <&apps_smmu 0x4e0 0x0>;
3090 opp-avg-kBps = <100000 0>;
3097 opp-avg-kBps = <200000 0>;
3104 reg = <0 0x088eb000 0 0x4000>;
3125 #size-cells = <0>;
3127 port@0 {
3128 reg = <0>;
3144 reg = <0 0x08902000 0 0x400>;
3145 #phy-cells = <0>;
3157 reg = <0 0x08903000 0 0x4000>;
3178 #size-cells = <0>;
3180 port@0 {
3181 reg = <0>;
3196 reg = <0 0x08909a00 0 0x19c>,
3197 <0 0x08909200 0 0xec>,
3198 <0 0x08909600 0 0xec>,
3199 <0 0x08909000 0 0x1c8>;
3207 #phy-cells = <0>;
3214 reg = <0 0x0890ca00 0 0x19c>,
3215 <0 0x0890c200 0 0xec>,
3216 <0 0x0890c600 0 0xec>,
3217 <0 0x0890c000 0 0x1c8>;
3225 #phy-cells = <0>;
3232 reg = <0 0x09091000 0 0x1000>;
3243 opp-0 {
3287 reg = <0 0x090b6400 0 0x600>;
3297 opp-0 {
3323 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3324 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3325 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3326 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3327 <0 0x09600000 0 0x58000>;
3336 reg = <0 0x0a6f8800 0 0x400>;
3371 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3372 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3381 reg = <0 0x0a600000 0 0xcd00>;
3383 iommus = <&apps_smmu 0x820 0x0>;
3396 reg = <0 0x0a8f8800 0 0x400>;
3431 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3441 reg = <0 0x0a800000 0 0xcd00>;
3443 iommus = <&apps_smmu 0x860 0x0>;
3456 reg = <0 0x0ad00000 0 0x20000>;
3470 reg = <0 0x0ae00000 0 0x1000>;
3480 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
3481 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
3483 iommus = <&apps_smmu 0x1000 0x402>;
3497 reg = <0 0x0ae01000 0 0x8f000>,
3498 <0 0x0aeb0000 0 0x2008>;
3514 interrupts = <0>;
3523 #size-cells = <0>;
3525 port@0 {
3526 reg = <0>;
3585 reg = <0 0xae90000 0 0x200>,
3586 <0 0xae90200 0 0x200>,
3587 <0 0xae90400 0 0x600>,
3588 <0 0xae91000 0 0x400>,
3589 <0 0xae91400 0 0x400>;
3610 #sound-dai-cells = <0>;
3619 #size-cells = <0>;
3621 port@0 {
3622 reg = <0>;
3664 reg = <0 0xae98000 0 0x200>,
3665 <0 0xae98200 0 0x200>,
3666 <0 0xae98400 0 0x600>,
3667 <0 0xae99000 0 0x400>,
3668 <0 0xae99400 0 0x400>;
3688 #sound-dai-cells = <0>;
3697 #size-cells = <0>;
3699 port@0 {
3700 reg = <0>;
3742 reg = <0 0xae9a000 0 0x200>,
3743 <0 0xae9a200 0 0x200>,
3744 <0 0xae9a400 0 0x600>,
3745 <0 0xae9b000 0 0x400>,
3746 <0 0xae9b400 0 0x400>;
3764 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3767 #sound-dai-cells = <0>;
3773 #size-cells = <0>;
3775 port@0 {
3776 reg = <0>;
3814 reg = <0 0xaea0000 0 0x200>,
3815 <0 0xaea0200 0 0x200>,
3816 <0 0xaea0400 0 0x600>,
3817 <0 0xaea1000 0 0x400>,
3818 <0 0xaea1400 0 0x400>;
3836 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3839 #sound-dai-cells = <0>;
3845 #size-cells = <0>;
3847 port@0 {
3848 reg = <0>;
3887 reg = <0 0x0aec2a00 0 0x19c>,
3888 <0 0x0aec2200 0 0xec>,
3889 <0 0x0aec2600 0 0xec>,
3890 <0 0x0aec2000 0 0x1c8>;
3898 #phy-cells = <0>;
3905 reg = <0 0x0aec5a00 0 0x19c>,
3906 <0 0x0aec5200 0 0xec>,
3907 <0 0x0aec5600 0 0xec>,
3908 <0 0x0aec5000 0 0x1c8>;
3916 #phy-cells = <0>;
3923 reg = <0 0x0af00000 0 0x20000>;
3932 <&mdss0_dp2_phy 0>,
3934 <&mdss0_dp3_phy 0>,
3936 <0>,
3937 <0>,
3938 <0>,
3939 <0>;
3951 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3952 qcom,pdc-ranges = <0 480 40>,
4016 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4017 <0 0x0c222000 0 0x8>; /* SROT */
4027 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4028 <0 0x0c223000 0 0x8>; /* SROT */
4038 reg = <0 0x0c300000 0 0x400>;
4042 #clock-cells = <0>;
4047 reg = <0 0x0c3f0000 0 0x400>;
4053 reg = <0 0x0c440000 0 0x1100>,
4054 <0 0x0c600000 0 0x2000000>,
4055 <0 0x0e600000 0 0x100000>,
4056 <0 0x0e700000 0 0xa0000>,
4057 <0 0x0c40a000 0 0x26000>;
4061 qcom,ee = <0>;
4062 qcom,channel = <0>;
4064 #size-cells = <0>;
4071 reg = <0 0x0f100000 0 0x300000>;
4077 gpio-ranges = <&tlmm 0 0 230>;
4083 reg = <0 0x15000000 0 0x100000>;
4222 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4223 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4226 redistributor-stride = <0 0x20000>;
4234 reg = <0 0x17a40000 0 0x20000>;
4242 reg = <0 0x17c10000 0 0x1000>;
4244 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4249 reg = <0x0 0x17c20000 0x0 0x1000>;
4252 ranges = <0x0 0x0 0x0 0x20000000>;
4255 frame-number = <0>;
4258 reg = <0x17c21000 0x1000>,
4259 <0x17c22000 0x1000>;
4265 reg = <0x17c23000 0x1000>;
4272 reg = <0x17c25000 0x1000>;
4279 reg = <0x17c26000 0x1000>;
4286 reg = <0x17c29000 0x1000>;
4293 reg = <0x17c2b000 0x1000>;
4300 reg = <0x17c2d000 0x1000>;
4307 reg = <0x0 0x18200000 0x0 0x10000>,
4308 <0x0 0x18210000 0x0 0x10000>,
4309 <0x0 0x18220000 0x0 0x10000>;
4310 reg-names = "drv-0", "drv-1", "drv-2";
4314 qcom,tcs-offset = <0xd00>;
4385 reg = <0 0x18590000 0 0x1000>;
4395 reg = <0 0x18591000 0 0x1000>,
4396 <0 0x18592000 0 0x1000>;
4408 reg = <0 0x1b300000 0 0x100>;
4411 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4426 qcom,smem-states = <&smp2p_nsp0_out 0>;
4429 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4448 #size-cells = <0>;
4453 iommus = <&apps_smmu 0x3181 0x0420>;
4459 iommus = <&apps_smmu 0x3182 0x0420>;
4465 iommus = <&apps_smmu 0x3183 0x0420>;
4471 iommus = <&apps_smmu 0x3184 0x0420>;
4477 iommus = <&apps_smmu 0x3185 0x0420>;
4483 iommus = <&apps_smmu 0x3186 0x0420>;
4489 iommus = <&apps_smmu 0x3187 0x0420>;
4495 iommus = <&apps_smmu 0x3188 0x0420>;
4501 iommus = <&apps_smmu 0x318b 0x0420>;
4507 iommus = <&apps_smmu 0x318b 0x0420>;
4513 iommus = <&apps_smmu 0x318c 0x0420>;
4519 iommus = <&apps_smmu 0x318d 0x0420>;
4525 iommus = <&apps_smmu 0x318e 0x0420>;
4531 iommus = <&apps_smmu 0x318f 0x0420>;
4539 reg = <0 0x21300000 0 0x100>;
4542 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
4557 qcom,smem-states = <&smp2p_nsp1_out 0>;
4560 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
4578 reg = <0 0x22000000 0 0x1000>;
4587 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
4588 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
4592 iommus = <&apps_smmu 0x1800 0x402>;
4606 reg = <0 0x22001000 0 0x8f000>,
4607 <0 0x220b0000 0 0x2008>;
4623 interrupts = <0>;
4632 #size-cells = <0>;
4634 port@0 {
4635 reg = <0>;
4694 reg = <0 0x22090000 0 0x200>,
4695 <0 0x22090200 0 0x200>,
4696 <0 0x22090400 0 0x600>,
4697 <0 0x22091000 0 0x400>,
4698 <0 0x22091400 0 0x400>;
4716 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4719 #sound-dai-cells = <0>;
4725 #size-cells = <0>;
4727 port@0 {
4728 reg = <0>;
4766 reg = <0 0x22098000 0 0x200>,
4767 <0 0x22098200 0 0x200>,
4768 <0 0x22098400 0 0x600>,
4769 <0 0x22099000 0 0x400>,
4770 <0 0x22099400 0 0x400>;
4788 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4791 #sound-dai-cells = <0>;
4797 #size-cells = <0>;
4799 port@0 {
4800 reg = <0>;
4838 reg = <0 0x2209a000 0 0x200>,
4839 <0 0x2209a200 0 0x200>,
4840 <0 0x2209a400 0 0x600>,
4841 <0 0x2209b000 0 0x400>,
4842 <0 0x2209b400 0 0x400>;
4860 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4863 #sound-dai-cells = <0>;
4869 #size-cells = <0>;
4871 port@0 {
4872 reg = <0>;
4910 reg = <0 0x220a0000 0 0x200>,
4911 <0 0x220a0200 0 0x200>,
4912 <0 0x220a0400 0 0x600>,
4913 <0 0x220a1000 0 0x400>,
4914 <0 0x220a1400 0 0x400>;
4932 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4935 #sound-dai-cells = <0>;
4941 #size-cells = <0>;
4943 port@0 {
4944 reg = <0>;
4983 reg = <0 0x220c2a00 0 0x19c>,
4984 <0 0x220c2200 0 0xec>,
4985 <0 0x220c2600 0 0xec>,
4986 <0 0x220c2000 0 0x1c8>;
4994 #phy-cells = <0>;
5001 reg = <0 0x220c5a00 0 0x19c>,
5002 <0 0x220c5200 0 0xec>,
5003 <0 0x220c5600 0 0xec>,
5004 <0 0x220c5000 0 0x1c8>;
5012 #phy-cells = <0>;
5019 reg = <0 0x22100000 0 0x20000>;
5023 <0>,
5024 <&mdss1_dp0_phy 0>,
5026 <&mdss1_dp1_phy 0>,
5028 <&mdss1_dp2_phy 0>,
5030 <&mdss1_dp3_phy 0>,
5032 <0>,
5033 <0>,
5034 <0>,
5035 <0>;
5047 reg = <0x0 0x23000000 0x0 0x10000>,
5048 <0x0 0x23016000 0x0 0x100>;
5064 iommus = <&apps_smmu 0x40 0xf>;