Lines Matching +full:sm8250 +full:- +full:mdss
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8180x.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
26 xo_board_clk: xo-board {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <38400000>;
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <32764>;
36 clock-output-names = "sleep_clk";
41 #address-cells = <2>;
42 #size-cells = <0>;
48 enable-method = "psci";
49 capacity-dmips-mhz = <602>;
50 next-level-cache = <&L2_0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
52 operating-points-v2 = <&cpu0_opp_table>;
55 power-domains = <&CPU_PD0>;
56 power-domain-names = "psci";
57 #cooling-cells = <2>;
60 L2_0: l2-cache {
62 cache-level = <2>;
63 cache-unified;
64 next-level-cache = <&L3_0>;
65 L3_0: l3-cache {
67 cache-level = <3>;
68 cache-unified;
77 enable-method = "psci";
78 capacity-dmips-mhz = <602>;
79 next-level-cache = <&L2_100>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
81 operating-points-v2 = <&cpu0_opp_table>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 #cooling-cells = <2>;
89 L2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&L3_0>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <602>;
104 next-level-cache = <&L2_200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 operating-points-v2 = <&cpu0_opp_table>;
109 power-domains = <&CPU_PD2>;
110 power-domain-names = "psci";
111 #cooling-cells = <2>;
114 L2_200: l2-cache {
116 cache-level = <2>;
117 cache-unified;
118 next-level-cache = <&L3_0>;
126 enable-method = "psci";
127 capacity-dmips-mhz = <602>;
128 next-level-cache = <&L2_300>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
130 operating-points-v2 = <&cpu0_opp_table>;
133 power-domains = <&CPU_PD3>;
134 power-domain-names = "psci";
135 #cooling-cells = <2>;
138 L2_300: l2-cache {
140 cache-unified;
141 cache-level = <2>;
142 next-level-cache = <&L3_0>;
150 enable-method = "psci";
151 capacity-dmips-mhz = <1024>;
152 next-level-cache = <&L2_400>;
153 qcom,freq-domain = <&cpufreq_hw 1>;
154 operating-points-v2 = <&cpu4_opp_table>;
157 power-domains = <&CPU_PD4>;
158 power-domain-names = "psci";
159 #cooling-cells = <2>;
162 L2_400: l2-cache {
164 cache-unified;
165 cache-level = <2>;
166 next-level-cache = <&L3_0>;
174 enable-method = "psci";
175 capacity-dmips-mhz = <1024>;
176 next-level-cache = <&L2_500>;
177 qcom,freq-domain = <&cpufreq_hw 1>;
178 operating-points-v2 = <&cpu4_opp_table>;
181 power-domains = <&CPU_PD5>;
182 power-domain-names = "psci";
183 #cooling-cells = <2>;
186 L2_500: l2-cache {
188 cache-unified;
189 cache-level = <2>;
190 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 next-level-cache = <&L2_600>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
205 power-domains = <&CPU_PD6>;
206 power-domain-names = "psci";
207 #cooling-cells = <2>;
210 L2_600: l2-cache {
212 cache-unified;
213 cache-level = <2>;
214 next-level-cache = <&L3_0>;
222 enable-method = "psci";
223 capacity-dmips-mhz = <1024>;
224 next-level-cache = <&L2_700>;
225 qcom,freq-domain = <&cpufreq_hw 1>;
226 operating-points-v2 = <&cpu4_opp_table>;
229 power-domains = <&CPU_PD7>;
230 power-domain-names = "psci";
231 #cooling-cells = <2>;
234 L2_700: l2-cache {
236 cache-unified;
237 cache-level = <2>;
238 next-level-cache = <&L3_0>;
242 cpu-map {
278 idle-states {
279 entry-method = "psci";
281 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
282 compatible = "arm,idle-state";
283 arm,psci-suspend-param = <0x40000004>;
284 entry-latency-us = <355>;
285 exit-latency-us = <909>;
286 min-residency-us = <3934>;
287 local-timer-stop;
290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
291 compatible = "arm,idle-state";
292 arm,psci-suspend-param = <0x40000004>;
293 entry-latency-us = <241>;
294 exit-latency-us = <1461>;
295 min-residency-us = <4488>;
296 local-timer-stop;
300 domain-idle-states {
301 CLUSTER_SLEEP_0: cluster-sleep-0 {
302 compatible = "domain-idle-state";
303 arm,psci-suspend-param = <0x4100a344>;
304 entry-latency-us = <3263>;
305 exit-latency-us = <6562>;
306 min-residency-us = <9987>;
311 cpu0_opp_table: opp-table-cpu0 {
312 compatible = "operating-points-v2";
313 opp-shared;
315 opp-300000000 {
316 opp-hz = /bits/ 64 <300000000>;
317 opp-peak-kBps = <800000 9600000>;
320 opp-422400000 {
321 opp-hz = /bits/ 64 <422400000>;
322 opp-peak-kBps = <800000 9600000>;
325 opp-537600000 {
326 opp-hz = /bits/ 64 <537600000>;
327 opp-peak-kBps = <800000 12902400>;
330 opp-652800000 {
331 opp-hz = /bits/ 64 <652800000>;
332 opp-peak-kBps = <800000 12902400>;
335 opp-768000000 {
336 opp-hz = /bits/ 64 <768000000>;
337 opp-peak-kBps = <800000 15974400>;
340 opp-883200000 {
341 opp-hz = /bits/ 64 <883200000>;
342 opp-peak-kBps = <1804000 19660800>;
345 opp-998400000 {
346 opp-hz = /bits/ 64 <998400000>;
347 opp-peak-kBps = <1804000 19660800>;
350 opp-1113600000 {
351 opp-hz = /bits/ 64 <1113600000>;
352 opp-peak-kBps = <1804000 22732800>;
355 opp-1228800000 {
356 opp-hz = /bits/ 64 <1228800000>;
357 opp-peak-kBps = <1804000 22732800>;
360 opp-1363200000 {
361 opp-hz = /bits/ 64 <1363200000>;
362 opp-peak-kBps = <2188000 25804800>;
365 opp-1478400000 {
366 opp-hz = /bits/ 64 <1478400000>;
367 opp-peak-kBps = <2188000 31948800>;
370 opp-1574400000 {
371 opp-hz = /bits/ 64 <1574400000>;
372 opp-peak-kBps = <3072000 31948800>;
375 opp-1670400000 {
376 opp-hz = /bits/ 64 <1670400000>;
377 opp-peak-kBps = <3072000 31948800>;
380 opp-1766400000 {
381 opp-hz = /bits/ 64 <1766400000>;
382 opp-peak-kBps = <3072000 31948800>;
386 cpu4_opp_table: opp-table-cpu4 {
387 compatible = "operating-points-v2";
388 opp-shared;
390 opp-825600000 {
391 opp-hz = /bits/ 64 <825600000>;
392 opp-peak-kBps = <1804000 15974400>;
395 opp-940800000 {
396 opp-hz = /bits/ 64 <940800000>;
397 opp-peak-kBps = <2188000 19660800>;
400 opp-1056000000 {
401 opp-hz = /bits/ 64 <1056000000>;
402 opp-peak-kBps = <2188000 22732800>;
405 opp-1171200000 {
406 opp-hz = /bits/ 64 <1171200000>;
407 opp-peak-kBps = <3072000 25804800>;
410 opp-1286400000 {
411 opp-hz = /bits/ 64 <1286400000>;
412 opp-peak-kBps = <3072000 31948800>;
415 opp-1420800000 {
416 opp-hz = /bits/ 64 <1420800000>;
417 opp-peak-kBps = <4068000 31948800>;
420 opp-1536000000 {
421 opp-hz = /bits/ 64 <1536000000>;
422 opp-peak-kBps = <4068000 31948800>;
425 opp-1651200000 {
426 opp-hz = /bits/ 64 <1651200000>;
427 opp-peak-kBps = <4068000 40550400>;
430 opp-1766400000 {
431 opp-hz = /bits/ 64 <1766400000>;
432 opp-peak-kBps = <4068000 40550400>;
435 opp-1881600000 {
436 opp-hz = /bits/ 64 <1881600000>;
437 opp-peak-kBps = <4068000 43008000>;
440 opp-1996800000 {
441 opp-hz = /bits/ 64 <1996800000>;
442 opp-peak-kBps = <6220000 43008000>;
445 opp-2131200000 {
446 opp-hz = /bits/ 64 <2131200000>;
447 opp-peak-kBps = <6220000 49152000>;
450 opp-2246400000 {
451 opp-hz = /bits/ 64 <2246400000>;
452 opp-peak-kBps = <7216000 49152000>;
455 opp-2361600000 {
456 opp-hz = /bits/ 64 <2361600000>;
457 opp-peak-kBps = <8368000 49152000>;
460 opp-2457600000 {
461 opp-hz = /bits/ 64 <2457600000>;
462 opp-peak-kBps = <8368000 51609600>;
465 opp-2553600000 {
466 opp-hz = /bits/ 64 <2553600000>;
467 opp-peak-kBps = <8368000 51609600>;
470 opp-2649600000 {
471 opp-hz = /bits/ 64 <2649600000>;
472 opp-peak-kBps = <8368000 51609600>;
475 opp-2745600000 {
476 opp-hz = /bits/ 64 <2745600000>;
477 opp-peak-kBps = <8368000 51609600>;
480 opp-2841600000 {
481 opp-hz = /bits/ 64 <2841600000>;
482 opp-peak-kBps = <8368000 51609600>;
485 opp-2918400000 {
486 opp-hz = /bits/ 64 <2918400000>;
487 opp-peak-kBps = <8368000 51609600>;
490 opp-2995200000 {
491 opp-hz = /bits/ 64 <2995200000>;
492 opp-peak-kBps = <8368000 51609600>;
498 compatible = "qcom,scm-sc8180x", "qcom,scm";
502 camnoc_virt: interconnect-camnoc-virt {
503 compatible = "qcom,sc8180x-camnoc-virt";
504 #interconnect-cells = <2>;
505 qcom,bcm-voters = <&apps_bcm_voter>;
508 mc_virt: interconnect-mc-virt {
509 compatible = "qcom,sc8180x-mc-virt";
510 #interconnect-cells = <2>;
511 qcom,bcm-voters = <&apps_bcm_voter>;
514 qup_virt: interconnect-qup-virt {
515 compatible = "qcom,sc8180x-qup-virt";
516 #interconnect-cells = <2>;
517 qcom,bcm-voters = <&apps_bcm_voter>;
527 compatible = "arm,armv8-pmuv3";
532 compatible = "arm,psci-1.0";
535 CPU_PD0: power-domain-cpu0 {
536 #power-domain-cells = <0>;
537 power-domains = <&CLUSTER_PD>;
538 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
541 CPU_PD1: power-domain-cpu1 {
542 #power-domain-cells = <0>;
543 power-domains = <&CLUSTER_PD>;
544 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
547 CPU_PD2: power-domain-cpu2 {
548 #power-domain-cells = <0>;
549 power-domains = <&CLUSTER_PD>;
550 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
553 CPU_PD3: power-domain-cpu3 {
554 #power-domain-cells = <0>;
555 power-domains = <&CLUSTER_PD>;
556 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
559 CPU_PD4: power-domain-cpu4 {
560 #power-domain-cells = <0>;
561 power-domains = <&CLUSTER_PD>;
562 domain-idle-states = <&BIG_CPU_SLEEP_0>;
565 CPU_PD5: power-domain-cpu5 {
566 #power-domain-cells = <0>;
567 power-domains = <&CLUSTER_PD>;
568 domain-idle-states = <&BIG_CPU_SLEEP_0>;
571 CPU_PD6: power-domain-cpu6 {
572 #power-domain-cells = <0>;
573 power-domains = <&CLUSTER_PD>;
574 domain-idle-states = <&BIG_CPU_SLEEP_0>;
577 CPU_PD7: power-domain-cpu7 {
578 #power-domain-cells = <0>;
579 power-domains = <&CLUSTER_PD>;
580 domain-idle-states = <&BIG_CPU_SLEEP_0>;
583 CLUSTER_PD: power-domain-cpu-cluster0 {
584 #power-domain-cells = <0>;
585 domain-idle-states = <&CLUSTER_SLEEP_0>;
589 reserved-memory {
590 #address-cells = <2>;
591 #size-cells = <2>;
596 no-map;
601 no-map;
606 no-map;
609 aop_cmd_db: cmd-db@85f20000 {
610 compatible = "qcom,cmd-db";
612 no-map;
617 no-map;
623 no-map;
629 no-map;
634 no-map;
639 no-map;
644 no-map;
649 no-map;
653 smp2p-cdsp {
661 qcom,local-pid = <0>;
662 qcom,remote-pid = <5>;
664 cdsp_smp2p_out: master-kernel {
665 qcom,entry-name = "master-kernel";
666 #qcom,smem-state-cells = <1>;
669 cdsp_smp2p_in: slave-kernel {
670 qcom,entry-name = "slave-kernel";
672 interrupt-controller;
673 #interrupt-cells = <2>;
677 smp2p-lpass {
685 qcom,local-pid = <0>;
686 qcom,remote-pid = <2>;
688 adsp_smp2p_out: master-kernel {
689 qcom,entry-name = "master-kernel";
690 #qcom,smem-state-cells = <1>;
693 adsp_smp2p_in: slave-kernel {
694 qcom,entry-name = "slave-kernel";
696 interrupt-controller;
697 #interrupt-cells = <2>;
701 smp2p-mpss {
709 qcom,local-pid = <0>;
710 qcom,remote-pid = <1>;
712 modem_smp2p_out: master-kernel {
713 qcom,entry-name = "master-kernel";
714 #qcom,smem-state-cells = <1>;
717 modem_smp2p_in: slave-kernel {
718 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
724 modem_smp2p_ipa_out: ipa-ap-to-modem {
725 qcom,entry-name = "ipa";
726 #qcom,smem-state-cells = <1>;
729 modem_smp2p_ipa_in: ipa-modem-to-ap {
730 qcom,entry-name = "ipa";
731 interrupt-controller;
732 #interrupt-cells = <2>;
735 modem_smp2p_wlan_in: wlan-wpss-to-ap {
736 qcom,entry-name = "wlan";
737 interrupt-controller;
738 #interrupt-cells = <2>;
742 smp2p-slpi {
750 qcom,local-pid = <0>;
751 qcom,remote-pid = <3>;
753 slpi_smp2p_out: master-kernel {
754 qcom,entry-name = "master-kernel";
755 #qcom,smem-state-cells = <1>;
758 slpi_smp2p_in: slave-kernel {
759 qcom,entry-name = "slave-kernel";
761 interrupt-controller;
762 #interrupt-cells = <2>;
767 compatible = "simple-bus";
768 #address-cells = <2>;
769 #size-cells = <2>;
771 dma-ranges = <0 0 0 0 0x10 0>;
773 gcc: clock-controller@100000 {
774 compatible = "qcom,gcc-sc8180x";
776 #clock-cells = <1>;
777 #reset-cells = <1>;
778 #power-domain-cells = <1>;
782 clock-names = "bi_tcxo",
788 compatible = "qcom,geni-se-qup";
792 clock-names = "m-ahb", "s-ahb";
793 #address-cells = <2>;
794 #size-cells = <2>;
800 compatible = "qcom,geni-i2c";
803 clock-names = "se";
808 interconnect-names = "qup-core", "qup-config", "qup-memory";
809 #address-cells = <1>;
810 #size-cells = <0>;
815 compatible = "qcom,geni-spi";
818 clock-names = "se";
822 interconnect-names = "qup-core", "qup-config";
823 #address-cells = <1>;
824 #size-cells = <0>;
829 compatible = "qcom,geni-uart";
832 clock-names = "se";
836 interconnect-names = "qup-core", "qup-config";
841 compatible = "qcom,geni-i2c";
844 clock-names = "se";
849 interconnect-names = "qup-core", "qup-config", "qup-memory";
850 #address-cells = <1>;
851 #size-cells = <0>;
856 compatible = "qcom,geni-spi";
859 clock-names = "se";
863 interconnect-names = "qup-core", "qup-config";
864 #address-cells = <1>;
865 #size-cells = <0>;
870 compatible = "qcom,geni-uart";
873 clock-names = "se";
877 interconnect-names = "qup-core", "qup-config";
882 compatible = "qcom,geni-i2c";
885 clock-names = "se";
890 interconnect-names = "qup-core", "qup-config", "qup-memory";
891 #address-cells = <1>;
892 #size-cells = <0>;
897 compatible = "qcom,geni-spi";
900 clock-names = "se";
904 interconnect-names = "qup-core", "qup-config";
905 #address-cells = <1>;
906 #size-cells = <0>;
911 compatible = "qcom,geni-uart";
914 clock-names = "se";
918 interconnect-names = "qup-core", "qup-config";
923 compatible = "qcom,geni-i2c";
926 clock-names = "se";
931 interconnect-names = "qup-core", "qup-config", "qup-memory";
932 #address-cells = <1>;
933 #size-cells = <0>;
938 compatible = "qcom,geni-spi";
941 clock-names = "se";
945 interconnect-names = "qup-core", "qup-config";
946 #address-cells = <1>;
947 #size-cells = <0>;
952 compatible = "qcom,geni-uart";
955 clock-names = "se";
959 interconnect-names = "qup-core", "qup-config";
964 compatible = "qcom,geni-i2c";
967 clock-names = "se";
972 interconnect-names = "qup-core", "qup-config", "qup-memory";
973 #address-cells = <1>;
974 #size-cells = <0>;
979 compatible = "qcom,geni-spi";
982 clock-names = "se";
986 interconnect-names = "qup-core", "qup-config";
987 #address-cells = <1>;
988 #size-cells = <0>;
993 compatible = "qcom,geni-uart";
996 clock-names = "se";
1000 interconnect-names = "qup-core", "qup-config";
1005 compatible = "qcom,geni-i2c";
1008 clock-names = "se";
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "qcom,geni-spi";
1023 clock-names = "se";
1027 interconnect-names = "qup-core", "qup-config";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1034 compatible = "qcom,geni-uart";
1037 clock-names = "se";
1041 interconnect-names = "qup-core", "qup-config";
1046 compatible = "qcom,geni-i2c";
1049 clock-names = "se";
1054 interconnect-names = "qup-core", "qup-config", "qup-memory";
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1061 compatible = "qcom,geni-spi";
1064 clock-names = "se";
1068 interconnect-names = "qup-core", "qup-config";
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1075 compatible = "qcom,geni-uart";
1078 clock-names = "se";
1082 interconnect-names = "qup-core", "qup-config";
1087 compatible = "qcom,geni-i2c";
1090 clock-names = "se";
1095 interconnect-names = "qup-core", "qup-config", "qup-memory";
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1102 compatible = "qcom,geni-spi";
1105 clock-names = "se";
1109 interconnect-names = "qup-core", "qup-config";
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1116 compatible = "qcom,geni-uart";
1119 clock-names = "se";
1123 interconnect-names = "qup-core", "qup-config";
1129 compatible = "qcom,geni-se-qup";
1133 clock-names = "m-ahb", "s-ahb";
1134 #address-cells = <2>;
1135 #size-cells = <2>;
1141 compatible = "qcom,geni-i2c";
1144 clock-names = "se";
1149 interconnect-names = "qup-core", "qup-config", "qup-memory";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1156 compatible = "qcom,geni-spi";
1159 clock-names = "se";
1163 interconnect-names = "qup-core", "qup-config";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1170 compatible = "qcom,geni-uart";
1173 clock-names = "se";
1177 interconnect-names = "qup-core", "qup-config";
1182 compatible = "qcom,geni-i2c";
1185 clock-names = "se";
1190 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1197 compatible = "qcom,geni-spi";
1200 clock-names = "se";
1204 interconnect-names = "qup-core", "qup-config";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1211 compatible = "qcom,geni-debug-uart";
1214 clock-names = "se";
1218 interconnect-names = "qup-core", "qup-config";
1223 compatible = "qcom,geni-i2c";
1226 clock-names = "se";
1231 interconnect-names = "qup-core", "qup-config", "qup-memory";
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1238 compatible = "qcom,geni-spi";
1241 clock-names = "se";
1245 interconnect-names = "qup-core", "qup-config";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1252 compatible = "qcom,geni-uart";
1255 clock-names = "se";
1259 interconnect-names = "qup-core", "qup-config";
1264 compatible = "qcom,geni-i2c";
1267 clock-names = "se";
1272 interconnect-names = "qup-core", "qup-config", "qup-memory";
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1279 compatible = "qcom,geni-spi";
1282 clock-names = "se";
1286 interconnect-names = "qup-core", "qup-config";
1287 #address-cells = <1>;
1288 #size-cells = <0>;
1293 compatible = "qcom,geni-uart";
1296 clock-names = "se";
1300 interconnect-names = "qup-core", "qup-config";
1305 compatible = "qcom,geni-i2c";
1308 clock-names = "se";
1313 interconnect-names = "qup-core", "qup-config", "qup-memory";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1320 compatible = "qcom,geni-spi";
1323 clock-names = "se";
1327 interconnect-names = "qup-core", "qup-config";
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "qcom,geni-uart";
1337 clock-names = "se";
1341 interconnect-names = "qup-core", "qup-config";
1346 compatible = "qcom,geni-i2c";
1349 clock-names = "se";
1354 interconnect-names = "qup-core", "qup-config", "qup-memory";
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1361 compatible = "qcom,geni-spi";
1364 clock-names = "se";
1368 interconnect-names = "qup-core", "qup-config";
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1375 compatible = "qcom,geni-uart";
1378 clock-names = "se";
1382 interconnect-names = "qup-core", "qup-config";
1388 compatible = "qcom,geni-se-qup";
1392 clock-names = "m-ahb", "s-ahb";
1393 #address-cells = <2>;
1394 #size-cells = <2>;
1400 compatible = "qcom,geni-i2c";
1403 clock-names = "se";
1408 interconnect-names = "qup-core", "qup-config", "qup-memory";
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1415 compatible = "qcom,geni-spi";
1418 clock-names = "se";
1422 interconnect-names = "qup-core", "qup-config";
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "qcom,geni-uart";
1432 clock-names = "se";
1436 interconnect-names = "qup-core", "qup-config";
1441 compatible = "qcom,geni-i2c";
1444 clock-names = "se";
1449 interconnect-names = "qup-core", "qup-config", "qup-memory";
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1456 compatible = "qcom,geni-spi";
1459 clock-names = "se";
1463 interconnect-names = "qup-core", "qup-config";
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1470 compatible = "qcom,geni-uart";
1473 clock-names = "se";
1477 interconnect-names = "qup-core", "qup-config";
1482 compatible = "qcom,geni-i2c";
1485 clock-names = "se";
1490 interconnect-names = "qup-core", "qup-config", "qup-memory";
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1497 compatible = "qcom,geni-spi";
1500 clock-names = "se";
1504 interconnect-names = "qup-core", "qup-config";
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1511 compatible = "qcom,geni-uart";
1514 clock-names = "se";
1518 interconnect-names = "qup-core", "qup-config";
1523 compatible = "qcom,geni-i2c";
1526 clock-names = "se";
1531 interconnect-names = "qup-core", "qup-config", "qup-memory";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1538 compatible = "qcom,geni-spi";
1541 clock-names = "se";
1545 interconnect-names = "qup-core", "qup-config";
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1552 compatible = "qcom,geni-uart";
1555 clock-names = "se";
1559 interconnect-names = "qup-core", "qup-config";
1564 compatible = "qcom,geni-i2c";
1567 clock-names = "se";
1572 interconnect-names = "qup-core", "qup-config", "qup-memory";
1573 #address-cells = <1>;
1574 #size-cells = <0>;
1579 compatible = "qcom,geni-spi";
1582 clock-names = "se";
1586 interconnect-names = "qup-core", "qup-config";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1593 compatible = "qcom,geni-uart";
1596 clock-names = "se";
1600 interconnect-names = "qup-core", "qup-config";
1605 compatible = "qcom,geni-i2c";
1608 clock-names = "se";
1613 interconnect-names = "qup-core", "qup-config", "qup-memory";
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1620 compatible = "qcom,geni-spi";
1623 clock-names = "se";
1627 interconnect-names = "qup-core", "qup-config";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1634 compatible = "qcom,geni-uart";
1637 clock-names = "se";
1641 interconnect-names = "qup-core", "qup-config";
1647 compatible = "qcom,sc8180x-config-noc";
1649 #interconnect-cells = <2>;
1650 qcom,bcm-voters = <&apps_bcm_voter>;
1654 compatible = "qcom,sc8180x-system-noc";
1656 #interconnect-cells = <2>;
1657 qcom,bcm-voters = <&apps_bcm_voter>;
1661 compatible = "qcom,sc8180x-aggre1-noc";
1663 #interconnect-cells = <2>;
1664 qcom,bcm-voters = <&apps_bcm_voter>;
1668 compatible = "qcom,sc8180x-aggre2-noc";
1670 #interconnect-cells = <2>;
1671 qcom,bcm-voters = <&apps_bcm_voter>;
1675 compatible = "qcom,sc8180x-compute-noc";
1677 #interconnect-cells = <2>;
1678 qcom,bcm-voters = <&apps_bcm_voter>;
1682 compatible = "qcom,sc8180x-mmss-noc";
1684 #interconnect-cells = <2>;
1685 qcom,bcm-voters = <&apps_bcm_voter>;
1689 compatible = "qcom,pcie-sc8180x";
1695 reg-names = "parf",
1701 linux,pci-domain = <0>;
1702 bus-range = <0x00 0xff>;
1703 num-lanes = <2>;
1705 #address-cells = <3>;
1706 #size-cells = <2>;
1712 interrupt-names = "msi";
1713 #interrupt-cells = <1>;
1714 interrupt-map-mask = <0 0 0 0x7>;
1715 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1728 clock-names = "pipe",
1737 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1738 assigned-clock-rates = <19200000>;
1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1744 reset-names = "pci";
1746 power-domains = <&gcc PCIE_0_GDSC>;
1750 interconnect-names = "pcie-mem", "cpu-pcie";
1753 phy-names = "pciephy";
1754 dma-coherent;
1760 compatible = "qcom,sc8180x-qmp-pcie-phy";
1767 clock-names = "aux",
1772 #clock-cells = <0>;
1773 clock-output-names = "pcie_0_pipe_clk";
1774 #phy-cells = <0>;
1777 reset-names = "phy";
1779 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1780 assigned-clock-rates = <100000000>;
1786 compatible = "qcom,pcie-sc8180x";
1792 reg-names = "parf",
1798 linux,pci-domain = <3>;
1799 bus-range = <0x00 0xff>;
1800 num-lanes = <2>;
1802 #address-cells = <3>;
1803 #size-cells = <2>;
1809 interrupt-names = "msi";
1810 #interrupt-cells = <1>;
1811 interrupt-map-mask = <0 0 0 0x7>;
1812 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1825 clock-names = "pipe",
1834 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1835 assigned-clock-rates = <19200000>;
1837 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1841 reset-names = "pci";
1843 power-domains = <&gcc PCIE_3_GDSC>;
1847 interconnect-names = "pcie-mem", "cpu-pcie";
1850 phy-names = "pciephy";
1851 dma-coherent;
1857 compatible = "qcom,sc8180x-qmp-pcie-phy";
1864 clock-names = "aux",
1869 #clock-cells = <0>;
1870 clock-output-names = "pcie_3_pipe_clk";
1872 #phy-cells = <0>;
1875 reset-names = "phy";
1877 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1878 assigned-clock-rates = <100000000>;
1884 compatible = "qcom,pcie-sc8180x";
1890 reg-names = "parf",
1896 linux,pci-domain = <1>;
1897 bus-range = <0x00 0xff>;
1898 num-lanes = <2>;
1900 #address-cells = <3>;
1901 #size-cells = <2>;
1907 interrupt-names = "msi";
1908 #interrupt-cells = <1>;
1909 interrupt-map-mask = <0 0 0 0x7>;
1910 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1923 clock-names = "pipe",
1932 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1933 assigned-clock-rates = <19200000>;
1935 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1939 reset-names = "pci";
1941 power-domains = <&gcc PCIE_1_GDSC>;
1945 interconnect-names = "pcie-mem", "cpu-pcie";
1948 phy-names = "pciephy";
1949 dma-coherent;
1955 compatible = "qcom,sc8180x-qmp-pcie-phy";
1962 clock-names = "aux",
1967 #clock-cells = <0>;
1968 clock-output-names = "pcie_1_pipe_clk";
1970 #phy-cells = <0>;
1973 reset-names = "phy";
1975 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1976 assigned-clock-rates = <100000000>;
1982 compatible = "qcom,pcie-sc8180x";
1988 reg-names = "parf",
1994 linux,pci-domain = <2>;
1995 bus-range = <0x00 0xff>;
1996 num-lanes = <4>;
1998 #address-cells = <3>;
1999 #size-cells = <2>;
2005 interrupt-names = "msi";
2006 #interrupt-cells = <1>;
2007 interrupt-map-mask = <0 0 0 0x7>;
2008 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2021 clock-names = "pipe",
2030 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2031 assigned-clock-rates = <19200000>;
2033 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2037 reset-names = "pci";
2039 power-domains = <&gcc PCIE_2_GDSC>;
2043 interconnect-names = "pcie-mem", "cpu-pcie";
2046 phy-names = "pciephy";
2047 dma-coherent;
2053 compatible = "qcom,sc8180x-qmp-pcie-phy";
2060 clock-names = "aux",
2065 #clock-cells = <0>;
2066 clock-output-names = "pcie_2_pipe_clk";
2068 #phy-cells = <0>;
2071 reset-names = "phy";
2073 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2074 assigned-clock-rates = <100000000>;
2080 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2081 "jedec,ufs-2.0";
2085 phy-names = "ufsphy";
2086 lanes-per-direction = <2>;
2087 #reset-cells = <1>;
2089 reset-names = "rst";
2101 clock-names = "core_clk",
2109 freq-table-hz = <37500000 300000000>,
2118 power-domains = <&gcc UFS_PHY_GDSC>;
2124 interconnect-names = "ufs-ddr", "cpu-ufs";
2129 ufs_mem_phy: phy-wrapper@1d87000 {
2130 compatible = "qcom,sc8180x-qmp-ufs-phy";
2135 clock-names = "ref",
2139 reset-names = "ufsphy";
2141 #phy-cells = <0>;
2147 compatible = "qcom,sc8180x-ipa-virt";
2149 #interconnect-cells = <2>;
2150 qcom,bcm-voters = <&apps_bcm_voter>;
2154 compatible = "qcom,tcsr-mutex";
2156 #hwlock-cells = <1>;
2160 compatible = "qcom,adreno-680.1", "qcom,adreno";
2161 #stream-id-cells = <16>;
2164 reg-names = "kgsl_3d0_reg_memory";
2170 operating-points-v2 = <&gpu_opp_table>;
2173 interconnect-names = "gfx-mem";
2178 gpu_opp_table: opp-table {
2179 compatible = "operating-points-v2";
2181 opp-514000000 {
2182 opp-hz = /bits/ 64 <514000000>;
2183 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2186 opp-500000000 {
2187 opp-hz = /bits/ 64 <500000000>;
2188 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2191 opp-461000000 {
2192 opp-hz = /bits/ 64 <461000000>;
2193 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2196 opp-405000000 {
2197 opp-hz = /bits/ 64 <405000000>;
2198 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2201 opp-315000000 {
2202 opp-hz = /bits/ 64 <315000000>;
2203 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2206 opp-256000000 {
2207 opp-hz = /bits/ 64 <256000000>;
2208 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2211 opp-177000000 {
2212 opp-hz = /bits/ 64 <177000000>;
2213 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2219 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2224 reg-names = "gmu",
2230 interrupt-names = "hfi", "gmu";
2237 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2239 power-domains = <&gpucc GPU_CX_GDSC>,
2241 power-domain-names = "cx", "gx";
2245 operating-points-v2 = <&gmu_opp_table>;
2247 gmu_opp_table: opp-table {
2248 compatible = "operating-points-v2";
2250 opp-200000000 {
2251 opp-hz = /bits/ 64 <200000000>;
2252 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2255 opp-500000000 {
2256 opp-hz = /bits/ 64 <500000000>;
2257 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2262 gpucc: clock-controller@2c90000 {
2263 compatible = "qcom,sc8180x-gpucc";
2268 clock-names = "bi_tcxo",
2271 #clock-cells = <1>;
2272 #reset-cells = <1>;
2273 #power-domain-cells = <1>;
2277 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2278 "qcom,smmu-500", "arm,mmu-500";
2280 #iommu-cells = <2>;
2281 #global-interrupts = <1>;
2294 clock-names = "ahb", "bus", "iface";
2296 power-domains = <&gpucc GPU_CX_GDSC>;
2300 compatible = "qcom,sc8180x-tlmm";
2304 reg-names = "west", "east", "south";
2306 gpio-controller;
2307 #gpio-cells = <2>;
2308 interrupt-controller;
2309 #interrupt-cells = <2>;
2310 gpio-ranges = <&tlmm 0 0 191>;
2311 wakeup-parent = <&pdc>;
2315 compatible = "qcom,sc8180x-mpss-pas";
2318 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2324 interrupt-names = "wdog", "fatal", "ready", "handover",
2325 "stop-ack", "shutdown-ack";
2328 clock-names = "xo";
2330 power-domains = <&rpmhpd SC8180X_CX>,
2332 power-domain-names = "cx", "mss";
2336 qcom,smem-states = <&modem_smp2p_out 0>;
2337 qcom,smem-state-names = "stop";
2339 glink-edge {
2342 qcom,remote-pid = <1>;
2348 compatible = "qcom,sc8180x-cdsp-pas";
2351 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2356 interrupt-names = "wdog", "fatal", "ready",
2357 "handover", "stop-ack";
2360 clock-names = "xo";
2362 power-domains = <&rpmhpd SC8180X_CX>;
2363 power-domain-names = "cx";
2367 qcom,smem-states = <&cdsp_smp2p_out 0>;
2368 qcom,smem-state-names = "stop";
2372 glink-edge {
2375 qcom,remote-pid = <5>;
2381 compatible = "qcom,sc8180x-usb-hs-phy",
2382 "qcom,usb-snps-hs-7nm-phy";
2385 clock-names = "ref";
2388 #phy-cells = <0>;
2394 compatible = "qcom,sc8180x-usb-hs-phy",
2395 "qcom,usb-snps-hs-7nm-phy";
2398 clock-names = "ref";
2401 #phy-cells = <0>;
2407 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2411 reg-names = "reg-base", "dp_com";
2416 clock-names = "aux",
2422 reset-names = "phy", "common";
2424 #clock-cells = <1>;
2425 #address-cells = <2>;
2426 #size-cells = <2>;
2432 #address-cells = <1>;
2433 #size-cells = <0>;
2448 usb_prim_ssphy: usb3-phy@88e9200 {
2455 #phy-cells = <0>;
2457 clock-names = "pipe0";
2458 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2461 usb_prim_dpphy: dp-phy@88ea200 {
2467 #clock-cells = <1>;
2468 #phy-cells = <0>;
2473 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2477 reg-names = "reg-base", "dp_com";
2482 clock-names = "aux",
2488 reset-names = "phy", "common";
2490 #clock-cells = <1>;
2491 #address-cells = <2>;
2492 #size-cells = <2>;
2498 #address-cells = <1>;
2499 #size-cells = <0>;
2514 usb_sec_ssphy: usb3-phy@88e9200 {
2521 #phy-cells = <0>;
2523 clock-names = "pipe0";
2524 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2527 usb_sec_dpphy: dp-phy@88ef200 {
2533 #clock-cells = <1>;
2534 #phy-cells = <0>;
2535 clock-output-names = "qmp_dptx1_phy_pll_link_clk",
2540 system-cache-controller@9200000 {
2541 compatible = "qcom,sc8180x-llcc";
2545 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2551 compatible = "qcom,sc8180x-gem-noc";
2553 #interconnect-cells = <2>;
2554 qcom,bcm-voters = <&apps_bcm_voter>;
2558 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2560 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2564 interrupt-names = "hs_phy_irq",
2575 clock-names = "cfg_noc",
2582 power-domains = <&gcc USB30_PRIM_GDSC>;
2586 interconnect-names = "usb-ddr", "apps-usb";
2588 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2590 assigned-clock-rates = <19200000>, <200000000>;
2592 #address-cells = <2>;
2593 #size-cells = <2>;
2595 dma-ranges;
2607 phy-names = "usb2-phy", "usb3-phy";
2617 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2626 clock-names = "cfg_noc",
2633 power-domains = <&gcc USB30_SEC_GDSC>;
2634 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2638 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2641 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2643 assigned-clock-rates = <19200000>, <200000000>;
2647 interconnect-names = "usb-ddr", "apps-usb";
2649 #address-cells = <2>;
2650 #size-cells = <2>;
2652 dma-ranges;
2664 phy-names = "usb2-phy", "usb3-phy";
2673 mdss: mdss@ae00000 {
2674 compatible = "qcom,sc8180x-mdss";
2676 reg-names = "mdss";
2678 power-domains = <&dispcc MDSS_GDSC>;
2684 clock-names = "iface",
2692 interrupt-controller;
2693 #interrupt-cells = <1>;
2697 interconnect-names = "mdp0-mem", "mdp1-mem";
2701 #address-cells = <2>;
2702 #size-cells = <2>;
2708 compatible = "qcom,sc8180x-dpu";
2711 reg-names = "mdp", "vbif";
2719 clock-names = "iface",
2726 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2728 assigned-clock-rates = <460000000>,
2731 operating-points-v2 = <&mdp_opp_table>;
2732 power-domains = <&rpmhpd SC8180X_MMCX>;
2734 interrupt-parent = <&mdss>;
2738 #address-cells = <1>;
2739 #size-cells = <0>;
2744 remote-endpoint = <&dp0_in>;
2751 remote-endpoint = <&mdss_dsi0_in>;
2758 remote-endpoint = <&mdss_dsi1_in>;
2765 remote-endpoint = <&dp1_in>;
2772 remote-endpoint = <&edp_in>;
2777 mdp_opp_table: opp-table {
2778 compatible = "operating-points-v2";
2780 opp-200000000 {
2781 opp-hz = /bits/ 64 <200000000>;
2782 required-opps = <&rpmhpd_opp_low_svs>;
2785 opp-300000000 {
2786 opp-hz = /bits/ 64 <300000000>;
2787 required-opps = <&rpmhpd_opp_svs>;
2790 opp-345000000 {
2791 opp-hz = /bits/ 64 <345000000>;
2792 required-opps = <&rpmhpd_opp_svs_l1>;
2795 opp-460000000 {
2796 opp-hz = /bits/ 64 <460000000>;
2797 required-opps = <&rpmhpd_opp_nom>;
2803 compatible = "qcom,mdss-dsi-ctrl";
2805 reg-names = "dsi_ctrl";
2807 interrupt-parent = <&mdss>;
2816 clock-names = "byte",
2823 operating-points-v2 = <&dsi_opp_table>;
2824 power-domains = <&rpmhpd SC8180X_MMCX>;
2827 phy-names = "dsi";
2832 #address-cells = <1>;
2833 #size-cells = <0>;
2838 remote-endpoint = <&dpu_intf1_out>;
2849 dsi_opp_table: opp-table {
2850 compatible = "operating-points-v2";
2852 opp-187500000 {
2853 opp-hz = /bits/ 64 <187500000>;
2854 required-opps = <&rpmhpd_opp_low_svs>;
2857 opp-300000000 {
2858 opp-hz = /bits/ 64 <300000000>;
2859 required-opps = <&rpmhpd_opp_svs>;
2862 opp-358000000 {
2863 opp-hz = /bits/ 64 <358000000>;
2864 required-opps = <&rpmhpd_opp_svs_l1>;
2869 mdss_dsi0_phy: dsi-phy@ae94400 {
2870 compatible = "qcom,dsi-phy-7nm";
2874 reg-names = "dsi_phy",
2878 #clock-cells = <1>;
2879 #phy-cells = <0>;
2883 clock-names = "iface", "ref";
2889 compatible = "qcom,mdss-dsi-ctrl";
2891 reg-names = "dsi_ctrl";
2893 interrupt-parent = <&mdss>;
2902 clock-names = "byte",
2909 operating-points-v2 = <&dsi_opp_table>;
2910 power-domains = <&rpmhpd SC8180X_MMCX>;
2913 phy-names = "dsi";
2918 #address-cells = <1>;
2919 #size-cells = <0>;
2924 remote-endpoint = <&dpu_intf2_out>;
2936 mdss_dsi1_phy: dsi-phy@ae96400 {
2937 compatible = "qcom,dsi-phy-7nm";
2941 reg-names = "dsi_phy",
2945 #clock-cells = <1>;
2946 #phy-cells = <0>;
2950 clock-names = "iface", "ref";
2955 mdss_dp0: displayport-controller@ae90000 {
2956 compatible = "qcom,sc8180x-dp";
2961 interrupt-parent = <&mdss>;
2968 clock-names = "core_iface",
2974 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2976 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
2979 phy-names = "dp";
2981 #sound-dai-cells = <0>;
2983 operating-points-v2 = <&dp0_opp_table>;
2984 power-domains = <&rpmhpd SC8180X_MMCX>;
2989 #address-cells = <1>;
2990 #size-cells = <0>;
2995 remote-endpoint = <&dpu_intf0_out>;
3006 dp0_opp_table: opp-table {
3007 compatible = "operating-points-v2";
3009 opp-160000000 {
3010 opp-hz = /bits/ 64 <160000000>;
3011 required-opps = <&rpmhpd_opp_low_svs>;
3014 opp-270000000 {
3015 opp-hz = /bits/ 64 <270000000>;
3016 required-opps = <&rpmhpd_opp_svs>;
3019 opp-540000000 {
3020 opp-hz = /bits/ 64 <540000000>;
3021 required-opps = <&rpmhpd_opp_svs_l1>;
3024 opp-810000000 {
3025 opp-hz = /bits/ 64 <810000000>;
3026 required-opps = <&rpmhpd_opp_nom>;
3031 mdss_dp1: displayport-controller@ae98000 {
3032 compatible = "qcom,sc8180x-dp";
3037 interrupt-parent = <&mdss>;
3044 clock-names = "core_iface",
3050 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3052 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3055 phy-names = "dp";
3057 #sound-dai-cells = <0>;
3059 operating-points-v2 = <&dp0_opp_table>;
3060 power-domains = <&rpmhpd SC8180X_MMCX>;
3065 #address-cells = <1>;
3066 #size-cells = <0>;
3071 remote-endpoint = <&dpu_intf4_out>;
3082 dp1_opp_table: opp-table {
3083 compatible = "operating-points-v2";
3085 opp-160000000 {
3086 opp-hz = /bits/ 64 <160000000>;
3087 required-opps = <&rpmhpd_opp_low_svs>;
3090 opp-270000000 {
3091 opp-hz = /bits/ 64 <270000000>;
3092 required-opps = <&rpmhpd_opp_svs>;
3095 opp-540000000 {
3096 opp-hz = /bits/ 64 <540000000>;
3097 required-opps = <&rpmhpd_opp_svs_l1>;
3100 opp-810000000 {
3101 opp-hz = /bits/ 64 <810000000>;
3102 required-opps = <&rpmhpd_opp_nom>;
3107 mdss_edp: displayport-controller@ae9a000 {
3108 compatible = "qcom,sc8180x-edp";
3113 interrupt-parent = <&mdss>;
3120 clock-names = "core_iface",
3126 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3128 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3131 phy-names = "dp";
3133 operating-points-v2 = <&edp_opp_table>;
3134 power-domains = <&rpmhpd SC8180X_MMCX>;
3139 #address-cells = <1>;
3140 #size-cells = <0>;
3145 remote-endpoint = <&dpu_intf5_out>;
3150 edp_opp_table: opp-table {
3151 compatible = "operating-points-v2";
3153 opp-160000000 {
3154 opp-hz = /bits/ 64 <160000000>;
3155 required-opps = <&rpmhpd_opp_low_svs>;
3158 opp-270000000 {
3159 opp-hz = /bits/ 64 <270000000>;
3160 required-opps = <&rpmhpd_opp_svs>;
3163 opp-540000000 {
3164 opp-hz = /bits/ 64 <540000000>;
3165 required-opps = <&rpmhpd_opp_svs_l1>;
3168 opp-810000000 {
3169 opp-hz = /bits/ 64 <810000000>;
3170 required-opps = <&rpmhpd_opp_nom>;
3177 compatible = "qcom,sc8180x-edp-phy";
3185 clock-names = "aux", "cfg_ahb";
3187 power-domains = <&dispcc MDSS_GDSC>;
3189 #clock-cells = <1>;
3190 #phy-cells = <0>;
3193 dispcc: clock-controller@af00000 {
3194 compatible = "qcom,sc8180x-dispcc";
3204 clock-names = "bi_tcxo",
3212 power-domains = <&rpmhpd SC8180X_MMCX>;
3213 #clock-cells = <1>;
3214 #reset-cells = <1>;
3215 #power-domain-cells = <1>;
3218 pdc: interrupt-controller@b220000 {
3219 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3221 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3222 #interrupt-cells = <2>;
3223 interrupt-parent = <&intc>;
3224 interrupt-controller;
3227 tsens0: thermal-sensor@c263000 {
3228 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3234 interrupt-names = "uplow", "critical";
3235 #thermal-sensor-cells = <1>;
3238 tsens1: thermal-sensor@c265000 {
3239 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3245 interrupt-names = "uplow", "critical";
3246 #thermal-sensor-cells = <1>;
3249 aoss_qmp: power-controller@c300000 {
3250 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3255 #clock-cells = <0>;
3256 #power-domain-cells = <1>;
3260 compatible = "qcom,spmi-pmic-arb";
3266 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3267 interrupt-names = "periph_irq";
3271 #address-cells = <2>;
3272 #size-cells = <0>;
3273 interrupt-controller;
3274 #interrupt-cells = <4>;
3278 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3280 #iommu-cells = <2>;
3281 #global-interrupts = <1>;
3393 compatible = "qcom,sc8180x-adsp-pas";
3396 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3401 interrupt-names = "wdog", "fatal", "ready",
3402 "handover", "stop-ack";
3405 clock-names = "xo";
3407 power-domains = <&rpmhpd SC8180X_CX>;
3408 power-domain-names = "cx";
3412 qcom,smem-states = <&adsp_smp2p_out 0>;
3413 qcom,smem-state-names = "stop";
3417 remoteproc_adsp_glink: glink-edge {
3420 qcom,remote-pid = <2>;
3425 intc: interrupt-controller@17a00000 {
3426 compatible = "arm,gic-v3";
3427 interrupt-controller;
3428 #interrupt-cells = <3>;
3432 #redistributor-regions = <1>;
3433 redistributor-stride = <0 0x20000>;
3437 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3439 #mbox-cells = <1>;
3443 compatible = "arm,armv7-timer-mem";
3446 #address-cells = <1>;
3447 #size-cells = <1>;
3453 frame-number = <0>;
3460 frame-number = <1>;
3467 frame-number = <2>;
3474 frame-number = <3>;
3481 frame-number = <4>;
3488 frame-number = <5>;
3495 frame-number = <6>;
3502 compatible = "qcom,rpmh-rsc";
3506 reg-names = "drv-0", "drv-1", "drv-2";
3510 qcom,tcs-offset = <0xd00>;
3511 qcom,drv-id = <2>;
3512 qcom,tcs-config = <ACTIVE_TCS 2>,
3517 power-domains = <&CLUSTER_PD>;
3519 apps_bcm_voter: bcm-voter {
3520 compatible = "qcom,bcm-voter";
3523 rpmhcc: clock-controller {
3524 compatible = "qcom,sc8180x-rpmh-clk";
3525 #clock-cells = <1>;
3526 clock-names = "xo";
3530 rpmhpd: power-controller {
3531 compatible = "qcom,sc8180x-rpmhpd";
3532 #power-domain-cells = <1>;
3533 operating-points-v2 = <&rpmhpd_opp_table>;
3535 rpmhpd_opp_table: opp-table {
3536 compatible = "operating-points-v2";
3539 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3543 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3547 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3551 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3555 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3559 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3563 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3567 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3571 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3575 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3582 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3586 clock-names = "xo", "alternate";
3588 #interconnect-cells = <1>;
3592 compatible = "qcom,sc8180x-lmh";
3596 qcom,lmh-temp-arm-millicelsius = <65000>;
3597 qcom,lmh-temp-low-millicelsius = <94500>;
3598 qcom,lmh-temp-high-millicelsius = <95000>;
3599 interrupt-controller;
3600 #interrupt-cells = <1>;
3604 compatible = "qcom,sc8180x-lmh";
3608 qcom,lmh-temp-arm-millicelsius = <65000>;
3609 qcom,lmh-temp-low-millicelsius = <94500>;
3610 qcom,lmh-temp-high-millicelsius = <95000>;
3611 interrupt-controller;
3612 #interrupt-cells = <1>;
3616 compatible = "qcom,cpufreq-hw";
3618 reg-names = "freq-domain0", "freq-domain1";
3621 clock-names = "xo", "alternate";
3623 #freq-domain-cells = <1>;
3624 #clock-cells = <1>;
3628 compatible = "qcom,wcn3990-wifi";
3630 reg-names = "membase";
3631 clock-names = "cxo_ref_clk_pin";
3646 qcom,msa-fixed-perm;
3651 thermal-zones {
3652 cpu0-thermal {
3653 polling-delay-passive = <250>;
3654 polling-delay = <1000>;
3656 thermal-sensors = <&tsens0 1>;
3659 cpu-crit {
3667 cpu1-thermal {
3668 polling-delay-passive = <250>;
3669 polling-delay = <1000>;
3671 thermal-sensors = <&tsens0 2>;
3674 cpu-crit {
3682 cpu2-thermal {
3683 polling-delay-passive = <250>;
3684 polling-delay = <1000>;
3686 thermal-sensors = <&tsens0 3>;
3689 cpu-crit {
3697 cpu3-thermal {
3698 polling-delay-passive = <250>;
3699 polling-delay = <1000>;
3701 thermal-sensors = <&tsens0 4>;
3704 cpu-crit {
3712 cpu4-top-thermal {
3713 polling-delay-passive = <250>;
3714 polling-delay = <1000>;
3716 thermal-sensors = <&tsens0 7>;
3719 cpu-crit {
3727 cpu5-top-thermal {
3728 polling-delay-passive = <250>;
3729 polling-delay = <1000>;
3731 thermal-sensors = <&tsens0 8>;
3734 cpu-crit {
3742 cpu6-top-thermal {
3743 polling-delay-passive = <250>;
3744 polling-delay = <1000>;
3746 thermal-sensors = <&tsens0 9>;
3749 cpu-crit {
3757 cpu7-top-thermal {
3758 polling-delay-passive = <250>;
3759 polling-delay = <1000>;
3761 thermal-sensors = <&tsens0 10>;
3764 cpu-crit {
3772 cpu4-bottom-thermal {
3773 polling-delay-passive = <250>;
3774 polling-delay = <1000>;
3776 thermal-sensors = <&tsens0 11>;
3779 cpu-crit {
3787 cpu5-bottom-thermal {
3788 polling-delay-passive = <250>;
3789 polling-delay = <1000>;
3791 thermal-sensors = <&tsens0 12>;
3794 cpu-crit {
3802 cpu6-bottom-thermal {
3803 polling-delay-passive = <250>;
3804 polling-delay = <1000>;
3806 thermal-sensors = <&tsens0 13>;
3809 cpu-crit {
3817 cpu7-bottom-thermal {
3818 polling-delay-passive = <250>;
3819 polling-delay = <1000>;
3821 thermal-sensors = <&tsens0 14>;
3824 cpu-crit {
3832 aoss0-thermal {
3833 polling-delay-passive = <250>;
3834 polling-delay = <1000>;
3836 thermal-sensors = <&tsens0 0>;
3839 trip-point0 {
3847 cluster0-thermal {
3848 polling-delay-passive = <250>;
3849 polling-delay = <1000>;
3851 thermal-sensors = <&tsens0 5>;
3854 cluster-crit {
3862 cluster1-thermal {
3863 polling-delay-passive = <250>;
3864 polling-delay = <1000>;
3866 thermal-sensors = <&tsens0 6>;
3869 cluster-crit {
3877 gpu-top-thermal {
3878 polling-delay-passive = <250>;
3879 polling-delay = <1000>;
3881 thermal-sensors = <&tsens0 15>;
3884 trip-point0 {
3892 aoss1-thermal {
3893 polling-delay-passive = <250>;
3894 polling-delay = <1000>;
3896 thermal-sensors = <&tsens1 0>;
3899 trip-point0 {
3907 wlan-thermal {
3908 polling-delay-passive = <250>;
3909 polling-delay = <1000>;
3911 thermal-sensors = <&tsens1 1>;
3914 trip-point0 {
3922 video-thermal {
3923 polling-delay-passive = <250>;
3924 polling-delay = <1000>;
3926 thermal-sensors = <&tsens1 2>;
3929 trip-point0 {
3937 mem-thermal {
3938 polling-delay-passive = <250>;
3939 polling-delay = <1000>;
3941 thermal-sensors = <&tsens1 3>;
3944 trip-point0 {
3952 q6-hvx-thermal {
3953 polling-delay-passive = <250>;
3954 polling-delay = <1000>;
3956 thermal-sensors = <&tsens1 4>;
3959 trip-point0 {
3967 camera-thermal {
3968 polling-delay-passive = <250>;
3969 polling-delay = <1000>;
3971 thermal-sensors = <&tsens1 5>;
3974 trip-point0 {
3982 compute-thermal {
3983 polling-delay-passive = <250>;
3984 polling-delay = <1000>;
3986 thermal-sensors = <&tsens1 6>;
3989 trip-point0 {
3997 mdm-dsp-thermal {
3998 polling-delay-passive = <250>;
3999 polling-delay = <1000>;
4001 thermal-sensors = <&tsens1 7>;
4004 trip-point0 {
4012 npu-thermal {
4013 polling-delay-passive = <250>;
4014 polling-delay = <1000>;
4016 thermal-sensors = <&tsens1 8>;
4019 trip-point0 {
4027 gpu-bottom-thermal {
4028 polling-delay-passive = <250>;
4029 polling-delay = <1000>;
4031 thermal-sensors = <&tsens1 11>;
4034 trip-point0 {
4044 compatible = "arm,armv8-timer";