Lines Matching +full:0 +full:x088ef000
28 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
58 clocks = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
87 clocks = <&cpufreq_hw 0>;
101 reg = <0x0 0x200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
112 clocks = <&cpufreq_hw 0>;
125 reg = <0x0 0x300>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
136 clocks = <&cpufreq_hw 0>;
149 reg = <0x0 0x400>;
173 reg = <0x0 0x500>;
197 reg = <0x0 0x600>;
221 reg = <0x0 0x700>;
281 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 arm,psci-suspend-param = <0x40000004>;
290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 arm,psci-suspend-param = <0x40000004>;
301 CLUSTER_SLEEP_0: cluster-sleep-0 {
303 arm,psci-suspend-param = <0x4100a344>;
523 reg = <0x0 0x80000000 0x0 0x0>;
536 #power-domain-cells = <0>;
542 #power-domain-cells = <0>;
548 #power-domain-cells = <0>;
554 #power-domain-cells = <0>;
560 #power-domain-cells = <0>;
566 #power-domain-cells = <0>;
572 #power-domain-cells = <0>;
578 #power-domain-cells = <0>;
584 #power-domain-cells = <0>;
595 reg = <0x0 0x85700000 0x0 0x600000>;
600 reg = <0x0 0x85d00000 0x0 0x140000>;
605 reg = <0x0 0x85f00000 0x0 0x20000>;
611 reg = <0x0 0x85f20000 0x0 0x20000>;
616 reg = <0x0 0x85f40000 0x0 0x10000>;
622 reg = <0x0 0x86000000 0x0 0x200000>;
628 reg = <0x0 0x86200000 0x0 0x3900000>;
633 reg = <0x0 0x89b00000 0x0 0x1c00000>;
638 reg = <0x0 0x9d400000 0x0 0x1000000>;
643 reg = <0x0 0x9e400000 0x0 0x1400000>;
648 reg = <0x0 0x9f800000 0x0 0x800000>;
661 qcom,local-pid = <0>;
685 qcom,local-pid = <0>;
709 qcom,local-pid = <0>;
750 qcom,local-pid = <0>;
766 soc: soc@0 {
770 ranges = <0 0 0 0 0x10 0>;
771 dma-ranges = <0 0 0 0 0x10 0>;
775 reg = <0x0 0x00100000 0x0 0x1f0000>;
789 reg = <0 0x008c0000 0 0x6000>;
796 iommus = <&apps_smmu 0x4c3 0>;
801 reg = <0 0x00880000 0 0x4000>;
805 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
806 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
807 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
810 #size-cells = <0>;
816 reg = <0 0x00880000 0 0x4000>;
820 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
821 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
824 #size-cells = <0>;
830 reg = <0 0x00880000 0 0x4000>;
834 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
835 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
842 reg = <0 0x00884000 0 0x4000>;
846 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
848 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
851 #size-cells = <0>;
857 reg = <0 0x00884000 0 0x4000>;
861 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
862 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
865 #size-cells = <0>;
871 reg = <0 0x00884000 0 0x4000>;
875 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
876 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
883 reg = <0 0x00888000 0 0x4000>;
887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
888 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
889 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
892 #size-cells = <0>;
898 reg = <0 0x00888000 0 0x4000>;
902 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
903 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
906 #size-cells = <0>;
912 reg = <0 0x00888000 0 0x4000>;
916 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
917 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
924 reg = <0 0x0088c000 0 0x4000>;
928 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
929 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
930 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
933 #size-cells = <0>;
939 reg = <0 0x0088c000 0 0x4000>;
943 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
944 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
947 #size-cells = <0>;
953 reg = <0 0x0088c000 0 0x4000>;
957 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
965 reg = <0 0x00890000 0 0x4000>;
969 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
970 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
971 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
974 #size-cells = <0>;
980 reg = <0 0x00890000 0 0x4000>;
984 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
985 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
988 #size-cells = <0>;
994 reg = <0 0x00890000 0 0x4000>;
998 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
999 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1006 reg = <0 0x00894000 0 0x4000>;
1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1012 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1015 #size-cells = <0>;
1021 reg = <0 0x00894000 0 0x4000>;
1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1029 #size-cells = <0>;
1035 reg = <0 0x00894000 0 0x4000>;
1039 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1040 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1047 reg = <0 0x00898000 0 0x4000>;
1051 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1052 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1053 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1056 #size-cells = <0>;
1062 reg = <0 0x00898000 0 0x4000>;
1066 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1070 #size-cells = <0>;
1076 reg = <0 0x00898000 0 0x4000>;
1080 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1088 reg = <0 0x0089c000 0 0x4000>;
1092 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1093 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1094 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1097 #size-cells = <0>;
1103 reg = <0 0x0089c000 0 0x4000>;
1107 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1108 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1111 #size-cells = <0>;
1117 reg = <0 0x0089c000 0 0x4000>;
1121 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1122 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1130 reg = <0x0 0x00ac0000 0x0 0x6000>;
1137 iommus = <&apps_smmu 0x603 0>;
1142 reg = <0 0x00a80000 0 0x4000>;
1146 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1148 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1151 #size-cells = <0>;
1157 reg = <0 0x00a80000 0 0x4000>;
1161 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1162 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1165 #size-cells = <0>;
1171 reg = <0 0x00a80000 0 0x4000>;
1175 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1176 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1183 reg = <0 0x00a84000 0 0x4000>;
1187 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1188 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1189 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1192 #size-cells = <0>;
1198 reg = <0 0x00a84000 0 0x4000>;
1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1203 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1206 #size-cells = <0>;
1212 reg = <0 0x00a84000 0 0x4000>;
1216 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1217 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1224 reg = <0 0x00a88000 0 0x4000>;
1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1229 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1230 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1233 #size-cells = <0>;
1239 reg = <0 0x00a88000 0 0x4000>;
1243 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1244 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1247 #size-cells = <0>;
1253 reg = <0 0x00a88000 0 0x4000>;
1257 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1258 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1265 reg = <0 0x00a8c000 0 0x4000>;
1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1271 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1274 #size-cells = <0>;
1280 reg = <0 0x00a8c000 0 0x4000>;
1284 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1285 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1288 #size-cells = <0>;
1294 reg = <0 0x00a8c000 0 0x4000>;
1298 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1299 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1306 reg = <0 0x00a90000 0 0x4000>;
1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1311 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1312 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1315 #size-cells = <0>;
1321 reg = <0 0x00a90000 0 0x4000>;
1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1326 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1329 #size-cells = <0>;
1335 reg = <0 0x00a90000 0 0x4000>;
1339 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1340 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1347 reg = <0 0x00a94000 0 0x4000>;
1351 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1352 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1353 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1356 #size-cells = <0>;
1362 reg = <0 0x00a94000 0 0x4000>;
1366 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1367 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1370 #size-cells = <0>;
1376 reg = <0 0x00a94000 0 0x4000>;
1380 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1389 reg = <0x0 0x00cc0000 0x0 0x6000>;
1396 iommus = <&apps_smmu 0x7a3 0>;
1401 reg = <0 0x00c80000 0 0x4000>;
1405 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1406 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1407 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1410 #size-cells = <0>;
1416 reg = <0 0x00c80000 0 0x4000>;
1420 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1424 #size-cells = <0>;
1430 reg = <0 0x00c80000 0 0x4000>;
1434 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1435 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1442 reg = <0 0x00c84000 0 0x4000>;
1446 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1447 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1448 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1451 #size-cells = <0>;
1457 reg = <0 0x00c84000 0 0x4000>;
1461 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1462 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1465 #size-cells = <0>;
1471 reg = <0 0x00c84000 0 0x4000>;
1475 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1476 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1483 reg = <0 0x00c88000 0 0x4000>;
1487 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1489 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1492 #size-cells = <0>;
1498 reg = <0 0x00c88000 0 0x4000>;
1502 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1503 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1506 #size-cells = <0>;
1512 reg = <0 0x00c88000 0 0x4000>;
1516 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1517 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1524 reg = <0 0x00c8c000 0 0x4000>;
1528 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1529 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1530 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1533 #size-cells = <0>;
1539 reg = <0 0x00c8c000 0 0x4000>;
1543 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1544 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1547 #size-cells = <0>;
1553 reg = <0 0x00c8c000 0 0x4000>;
1557 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1558 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1565 reg = <0 0x00c90000 0 0x4000>;
1569 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1570 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1571 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1574 #size-cells = <0>;
1580 reg = <0 0x00c90000 0 0x4000>;
1584 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1585 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1588 #size-cells = <0>;
1594 reg = <0 0x00c90000 0 0x4000>;
1598 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1599 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1606 reg = <0 0x00c94000 0 0x4000>;
1610 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1611 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1612 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1615 #size-cells = <0>;
1621 reg = <0 0x00c94000 0 0x4000>;
1625 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1626 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1629 #size-cells = <0>;
1635 reg = <0 0x00c94000 0 0x4000>;
1639 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1648 reg = <0 0x01500000 0 0x7400>;
1655 reg = <0 0x01620000 0 0x19400>;
1662 reg = <0 0x016e0000 0 0xd080>;
1669 reg = <0 0x01700000 0 0x20000>;
1676 reg = <0 0x01720000 0 0x7000>;
1683 reg = <0 0x01740000 0 0x1c100>;
1690 reg = <0 0x01c00000 0 0x3000>,
1691 <0 0x60000000 0 0xf1d>,
1692 <0 0x60000f20 0 0xa8>,
1693 <0 0x60001000 0 0x1000>,
1694 <0 0x60100000 0 0x100000>;
1701 linux,pci-domain = <0>;
1702 bus-range = <0x00 0xff>;
1708 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1709 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1714 interrupt-map-mask = <0 0 0 0x7>;
1715 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1716 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1717 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1718 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1741 <0x100 &apps_smmu 0x1d81 0x1>;
1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1761 reg = <0 0x01c06000 0 0x1000>;
1772 #clock-cells = <0>;
1774 #phy-cells = <0>;
1787 reg = <0 0x01c08000 0 0x3000>,
1788 <0 0x40000000 0 0xf1d>,
1789 <0 0x40000f20 0 0xa8>,
1790 <0 0x40001000 0 0x1000>,
1791 <0 0x40100000 0 0x100000>;
1799 bus-range = <0x00 0xff>;
1805 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1806 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1811 interrupt-map-mask = <0 0 0 0x7>;
1812 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1813 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1814 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1815 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1837 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1838 <0x100 &apps_smmu 0x1e01 0x1>;
1845 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1858 reg = <0 0x01c0c000 0 0x1000>;
1869 #clock-cells = <0>;
1872 #phy-cells = <0>;
1885 reg = <0 0x01c10000 0 0x3000>,
1886 <0 0x68000000 0 0xf1d>,
1887 <0 0x68000f20 0 0xa8>,
1888 <0 0x68001000 0 0x1000>,
1889 <0 0x68100000 0 0x100000>;
1897 bus-range = <0x00 0xff>;
1903 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1904 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1909 interrupt-map-mask = <0 0 0 0x7>;
1910 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1911 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1912 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1913 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1935 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1936 <0x100 &apps_smmu 0x1c81 0x1>;
1943 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1944 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1956 reg = <0 0x01c16000 0 0x1000>;
1967 #clock-cells = <0>;
1970 #phy-cells = <0>;
1983 reg = <0 0x01c18000 0 0x3000>,
1984 <0 0x70000000 0 0xf1d>,
1985 <0 0x70000f20 0 0xa8>,
1986 <0 0x70001000 0 0x1000>,
1987 <0 0x70100000 0 0x100000>;
1995 bus-range = <0x00 0xff>;
2001 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2002 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2007 interrupt-map-mask = <0 0 0 0x7>;
2008 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2009 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2010 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2011 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2033 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2034 <0x100 &apps_smmu 0x1d01 0x1>;
2041 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2042 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2054 reg = <0 0x01c1c000 0 0x1000>;
2065 #clock-cells = <0>;
2068 #phy-cells = <0>;
2082 reg = <0 0x01d84000 0 0x2500>;
2091 iommus = <&apps_smmu 0x300 0>;
2110 <0 0>,
2111 <0 0>,
2113 <0 0>,
2114 <0 0>,
2115 <0 0>,
2116 <0 0>;
2131 reg = <0 0x01d87000 0 0x1000>;
2138 resets = <&ufs_mem_hc 0>;
2141 #phy-cells = <0>;
2148 reg = <0 0x01e00000 0 0x1000>;
2155 reg = <0x0 0x01f40000 0x0 0x40000>;
2163 reg = <0 0x02c00000 0 0x40000>;
2168 iommus = <&adreno_smmu 0 0xc01>;
2172 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2221 reg = <0 0x02c6a000 0 0x30000>,
2222 <0 0x0b290000 0 0x10000>,
2223 <0 0x0b490000 0 0x10000>;
2243 iommus = <&adreno_smmu 5 0xc00>;
2264 reg = <0 0x02c90000 0 0x9000>;
2279 reg = <0 0x02ca0000 0 0x10000>;
2301 reg = <0 0x03100000 0 0x300000>,
2302 <0 0x03500000 0 0x700000>,
2303 <0 0x03d00000 0 0x300000>;
2310 gpio-ranges = <&tlmm 0 0 191>;
2316 reg = <0x0 0x04080000 0x0 0x4040>;
2319 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2336 qcom,smem-states = <&modem_smp2p_out 0>;
2349 reg = <0x0 0x08300000 0x0 0x4040>;
2352 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2367 qcom,smem-states = <&cdsp_smp2p_out 0>;
2383 reg = <0 0x088e2000 0 0x400>;
2388 #phy-cells = <0>;
2396 reg = <0 0x088e3000 0 0x400>;
2401 #phy-cells = <0>;
2408 reg = <0 0x088e9000 0 0x18c>,
2409 <0 0x088e8000 0 0x38>,
2410 <0 0x088ea000 0 0x40>;
2433 #size-cells = <0>;
2435 port@0 {
2436 reg = <0>;
2449 reg = <0 0x088e9200 0 0x200>,
2450 <0 0x088e9400 0 0x200>,
2451 <0 0x088e9c00 0 0x218>,
2452 <0 0x088e9600 0 0x200>,
2453 <0 0x088e9800 0 0x200>,
2454 <0 0x088e9a00 0 0x100>;
2455 #phy-cells = <0>;
2462 reg = <0 0x088ea200 0 0x200>,
2463 <0 0x088ea400 0 0x200>,
2464 <0 0x088eaa00 0 0x200>,
2465 <0 0x088ea600 0 0x200>,
2466 <0 0x088ea800 0 0x200>;
2468 #phy-cells = <0>;
2474 reg = <0 0x088ee000 0 0x18c>,
2475 <0 0x088ed000 0 0x10>,
2476 <0 0x088ef000 0 0x40>;
2499 #size-cells = <0>;
2501 port@0 {
2502 reg = <0>;
2515 reg = <0 0x088ee200 0 0x200>,
2516 <0 0x088ee400 0 0x200>,
2517 <0 0x088eec00 0 0x218>,
2518 <0 0x088ee600 0 0x200>,
2519 <0 0x088ee800 0 0x200>,
2520 <0 0x088eea00 0 0x100>;
2521 #phy-cells = <0>;
2528 reg = <0 0x088ef200 0 0x200>,
2529 <0 0x088ef400 0 0x200>,
2530 <0 0x088efa00 0 0x200>,
2531 <0 0x088ef600 0 0x200>,
2532 <0 0x088ef800 0 0x200>;
2534 #phy-cells = <0>;
2542 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
2543 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
2544 <0 0x09600000 0 0x50000>;
2552 reg = <0 0x09680000 0 0x58200>;
2559 reg = <0 0x0a6f8800 0 0x400>;
2584 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2585 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2601 reg = <0 0x0a600000 0 0xcd00>;
2603 iommus = <&apps_smmu 0x140 0>;
2618 reg = <0 0x0a8f8800 0 0x400>;
2645 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2646 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2658 reg = <0 0x0a800000 0 0xcd00>;
2660 iommus = <&apps_smmu 0x160 0>;
2675 reg = <0 0x0ae00000 0 0x1000>;
2695 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
2696 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
2699 iommus = <&apps_smmu 0x800 0x420>;
2709 reg = <0 0x0ae01000 0 0x8f000>,
2710 <0 0x0aeb0000 0 0x2008>;
2735 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2739 #size-cells = <0>;
2741 port@0 {
2742 reg = <0>;
2804 reg = <0 0x0ae94000 0 0x400>;
2833 #size-cells = <0>;
2835 port@0 {
2836 reg = <0>;
2871 reg = <0 0x0ae94400 0 0x200>,
2872 <0 0x0ae94600 0 0x280>,
2873 <0 0x0ae94900 0 0x260>;
2879 #phy-cells = <0>;
2890 reg = <0 0x0ae96000 0 0x400>;
2919 #size-cells = <0>;
2921 port@0 {
2922 reg = <0>;
2938 reg = <0 0x0ae96400 0 0x200>,
2939 <0 0x0ae96600 0 0x280>,
2940 <0 0x0ae96900 0 0x260>;
2946 #phy-cells = <0>;
2957 reg = <0 0xae90000 0 0x200>,
2958 <0 0xae90200 0 0x200>,
2959 <0 0xae90400 0 0x600>,
2960 <0 0xae90a00 0 0x400>;
2976 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
2981 #sound-dai-cells = <0>;
2990 #size-cells = <0>;
2992 port@0 {
2993 reg = <0>;
3033 reg = <0 0xae98000 0 0x200>,
3034 <0 0xae98200 0 0x200>,
3035 <0 0xae98400 0 0x600>,
3036 <0 0xae98a00 0 0x400>;
3052 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3057 #sound-dai-cells = <0>;
3066 #size-cells = <0>;
3068 port@0 {
3069 reg = <0>;
3109 reg = <0 0xae9a000 0 0x200>,
3110 <0 0xae9a200 0 0x200>,
3111 <0 0xae9a400 0 0x600>,
3112 <0 0xae9aa00 0 0x400>;
3128 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3140 #size-cells = <0>;
3142 port@0 {
3143 reg = <0>;
3178 reg = <0 0x0aec2a00 0 0x1c0>,
3179 <0 0x0aec2200 0 0xa0>,
3180 <0 0x0aec2600 0 0xa0>,
3181 <0 0x0aec2000 0 0x19c>;
3190 #phy-cells = <0>;
3195 reg = <0 0x0af00000 0 0x20000>;
3198 <&usb_prim_dpphy 0>,
3200 <&usb_sec_dpphy 0>,
3202 <&edp_phy 0>,
3220 reg = <0 0x0b220000 0 0x30000>;
3221 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3229 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3230 <0 0x0c222000 0 0x1ff>; /* SROT */
3240 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3241 <0 0x0c223000 0 0x1ff>; /* SROT */
3251 reg = <0x0 0x0c300000 0x0 0x100000>;
3253 mboxes = <&apss_shared 0>;
3255 #clock-cells = <0>;
3261 reg = <0x0 0x0c440000 0x0 0x0001100>,
3262 <0x0 0x0c600000 0x0 0x2000000>,
3263 <0x0 0x0e600000 0x0 0x0100000>,
3264 <0x0 0x0e700000 0x0 0x00a0000>,
3265 <0x0 0x0c40a000 0x0 0x0026000>;
3269 qcom,ee = <0>;
3270 qcom,channel = <0>;
3272 #size-cells = <0>;
3279 reg = <0 0x15000000 0 0x100000>;
3394 reg = <0x0 0x17300000 0x0 0x4040>;
3397 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3412 qcom,smem-states = <&adsp_smp2p_out 0>;
3429 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3430 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3433 redistributor-stride = <0 0x20000>;
3438 reg = <0x0 0x17c00000 0x0 0x1000>;
3444 reg = <0x0 0x17c20000 0x0 0x1000>;
3448 ranges = <0 0 0 0x20000000>;
3451 reg = <0x17c21000 0x1000>,
3452 <0x17c22000 0x1000>;
3453 frame-number = <0>;
3459 reg = <0x17c23000 0x1000>;
3466 reg = <0x17c25000 0x1000>;
3473 reg = <0x17c26000 0x1000>;
3480 reg = <0x17c29000 0x1000>;
3487 reg = <0x17c2b000 0x1000>;
3494 reg = <0x17c2d000 0x1000>;
3503 reg = <0x0 0x18200000 0x0 0x10000>,
3504 <0x0 0x18210000 0x0 0x10000>,
3505 <0x0 0x18220000 0x0 0x10000>;
3506 reg-names = "drv-0", "drv-1", "drv-2";
3510 qcom,tcs-offset = <0xd00>;
3515 <CONTROL_TCS 0>;
3583 reg = <0 0x18321000 0 0x1400>;
3593 reg = <0 0x18350800 0 0x400>;
3605 reg = <0 0x18358800 0 0x400>;
3617 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3629 reg = <0 0x18800000 0 0x800000>;
3645 iommus = <&apps_smmu 0x0640 0x1>;
3836 thermal-sensors = <&tsens0 0>;
3896 thermal-sensors = <&tsens1 0>;
4048 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;