Lines Matching +full:opp +full:- +full:202000000
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sc7280.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/mailbox/qcom-ipcc.h>
23 #include <dt-bindings/phy/phy-qcom-qmp.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
28 #include <dt-bindings/sound/qcom,lpass.h>
29 #include <dt-bindings/thermal/thermal.h>
32 interrupt-parent = <&intc>;
34 #address-cells = <2>;
35 #size-cells = <2>;
77 xo_board: xo-board {
78 compatible = "fixed-clock";
79 clock-frequency = <76800000>;
80 #clock-cells = <0>;
83 sleep_clk: sleep-clk {
84 compatible = "fixed-clock";
85 clock-frequency = <32000>;
86 #clock-cells = <0>;
90 reserved-memory {
91 #address-cells = <2>;
92 #size-cells = <2>;
95 wlan_ce_mem: wlan-ce@4cd000 {
96 no-map;
102 no-map;
107 no-map;
112 no-map;
115 aop_cmd_db_mem: aop-cmd-db@80860000 {
117 compatible = "qcom,cmd-db";
118 no-map;
121 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
123 no-map;
126 sec_apps_mem: sec-apps@808ff000 {
128 no-map;
133 no-map;
137 no-map;
141 wlan_fw_mem: wlan-fw@80c00000 {
143 no-map;
148 no-map;
153 no-map;
158 no-map;
161 ipa_fw_mem: ipa-fw@8b700000 {
163 no-map;
168 no-map;
173 no-map;
178 no-map;
182 compatible = "qcom,rmtfs-mem";
184 no-map;
186 qcom,client-id = <1>;
192 #address-cells = <2>;
193 #size-cells = <0>;
200 enable-method = "psci";
201 power-domains = <&CPU_PD0>;
202 power-domain-names = "psci";
203 next-level-cache = <&L2_0>;
204 operating-points-v2 = <&cpu0_opp_table>;
207 qcom,freq-domain = <&cpufreq_hw 0>;
208 #cooling-cells = <2>;
209 L2_0: l2-cache {
211 cache-level = <2>;
212 cache-unified;
213 next-level-cache = <&L3_0>;
214 L3_0: l3-cache {
216 cache-level = <3>;
217 cache-unified;
227 enable-method = "psci";
228 power-domains = <&CPU_PD1>;
229 power-domain-names = "psci";
230 next-level-cache = <&L2_100>;
231 operating-points-v2 = <&cpu0_opp_table>;
234 qcom,freq-domain = <&cpufreq_hw 0>;
235 #cooling-cells = <2>;
236 L2_100: l2-cache {
238 cache-level = <2>;
239 cache-unified;
240 next-level-cache = <&L3_0>;
249 enable-method = "psci";
250 power-domains = <&CPU_PD2>;
251 power-domain-names = "psci";
252 next-level-cache = <&L2_200>;
253 operating-points-v2 = <&cpu0_opp_table>;
256 qcom,freq-domain = <&cpufreq_hw 0>;
257 #cooling-cells = <2>;
258 L2_200: l2-cache {
260 cache-level = <2>;
261 cache-unified;
262 next-level-cache = <&L3_0>;
271 enable-method = "psci";
272 power-domains = <&CPU_PD3>;
273 power-domain-names = "psci";
274 next-level-cache = <&L2_300>;
275 operating-points-v2 = <&cpu0_opp_table>;
278 qcom,freq-domain = <&cpufreq_hw 0>;
279 #cooling-cells = <2>;
280 L2_300: l2-cache {
282 cache-level = <2>;
283 cache-unified;
284 next-level-cache = <&L3_0>;
293 enable-method = "psci";
294 power-domains = <&CPU_PD4>;
295 power-domain-names = "psci";
296 next-level-cache = <&L2_400>;
297 operating-points-v2 = <&cpu4_opp_table>;
300 qcom,freq-domain = <&cpufreq_hw 1>;
301 #cooling-cells = <2>;
302 L2_400: l2-cache {
304 cache-level = <2>;
305 cache-unified;
306 next-level-cache = <&L3_0>;
315 enable-method = "psci";
316 power-domains = <&CPU_PD5>;
317 power-domain-names = "psci";
318 next-level-cache = <&L2_500>;
319 operating-points-v2 = <&cpu4_opp_table>;
322 qcom,freq-domain = <&cpufreq_hw 1>;
323 #cooling-cells = <2>;
324 L2_500: l2-cache {
326 cache-level = <2>;
327 cache-unified;
328 next-level-cache = <&L3_0>;
337 enable-method = "psci";
338 power-domains = <&CPU_PD6>;
339 power-domain-names = "psci";
340 next-level-cache = <&L2_600>;
341 operating-points-v2 = <&cpu4_opp_table>;
344 qcom,freq-domain = <&cpufreq_hw 1>;
345 #cooling-cells = <2>;
346 L2_600: l2-cache {
348 cache-level = <2>;
349 cache-unified;
350 next-level-cache = <&L3_0>;
359 enable-method = "psci";
360 power-domains = <&CPU_PD7>;
361 power-domain-names = "psci";
362 next-level-cache = <&L2_700>;
363 operating-points-v2 = <&cpu7_opp_table>;
366 qcom,freq-domain = <&cpufreq_hw 2>;
367 #cooling-cells = <2>;
368 L2_700: l2-cache {
370 cache-level = <2>;
371 cache-unified;
372 next-level-cache = <&L3_0>;
376 cpu-map {
412 idle-states {
413 entry-method = "psci";
415 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
416 compatible = "arm,idle-state";
417 idle-state-name = "little-power-down";
418 arm,psci-suspend-param = <0x40000003>;
419 entry-latency-us = <549>;
420 exit-latency-us = <901>;
421 min-residency-us = <1774>;
422 local-timer-stop;
425 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
426 compatible = "arm,idle-state";
427 idle-state-name = "little-rail-power-down";
428 arm,psci-suspend-param = <0x40000004>;
429 entry-latency-us = <702>;
430 exit-latency-us = <915>;
431 min-residency-us = <4001>;
432 local-timer-stop;
435 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
436 compatible = "arm,idle-state";
437 idle-state-name = "big-power-down";
438 arm,psci-suspend-param = <0x40000003>;
439 entry-latency-us = <523>;
440 exit-latency-us = <1244>;
441 min-residency-us = <2207>;
442 local-timer-stop;
445 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
446 compatible = "arm,idle-state";
447 idle-state-name = "big-rail-power-down";
448 arm,psci-suspend-param = <0x40000004>;
449 entry-latency-us = <526>;
450 exit-latency-us = <1854>;
451 min-residency-us = <5555>;
452 local-timer-stop;
456 domain-idle-states {
457 CLUSTER_SLEEP_0: cluster-sleep-0 {
458 compatible = "domain-idle-state";
459 idle-state-name = "cluster-power-down";
460 arm,psci-suspend-param = <0x40003444>;
461 entry-latency-us = <3263>;
462 exit-latency-us = <6562>;
463 min-residency-us = <9926>;
464 local-timer-stop;
469 cpu0_opp_table: opp-table-cpu0 {
470 compatible = "operating-points-v2";
471 opp-shared;
473 cpu0_opp_300mhz: opp-300000000 {
474 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <800000 9600000>;
478 cpu0_opp_691mhz: opp-691200000 {
479 opp-hz = /bits/ 64 <691200000>;
480 opp-peak-kBps = <800000 17817600>;
483 cpu0_opp_806mhz: opp-806400000 {
484 opp-hz = /bits/ 64 <806400000>;
485 opp-peak-kBps = <800000 20889600>;
488 cpu0_opp_941mhz: opp-940800000 {
489 opp-hz = /bits/ 64 <940800000>;
490 opp-peak-kBps = <1804000 24576000>;
493 cpu0_opp_1152mhz: opp-1152000000 {
494 opp-hz = /bits/ 64 <1152000000>;
495 opp-peak-kBps = <2188000 27033600>;
498 cpu0_opp_1325mhz: opp-1324800000 {
499 opp-hz = /bits/ 64 <1324800000>;
500 opp-peak-kBps = <2188000 33792000>;
503 cpu0_opp_1517mhz: opp-1516800000 {
504 opp-hz = /bits/ 64 <1516800000>;
505 opp-peak-kBps = <3072000 38092800>;
508 cpu0_opp_1651mhz: opp-1651200000 {
509 opp-hz = /bits/ 64 <1651200000>;
510 opp-peak-kBps = <3072000 41779200>;
513 cpu0_opp_1805mhz: opp-1804800000 {
514 opp-hz = /bits/ 64 <1804800000>;
515 opp-peak-kBps = <4068000 48537600>;
518 cpu0_opp_1958mhz: opp-1958400000 {
519 opp-hz = /bits/ 64 <1958400000>;
520 opp-peak-kBps = <4068000 48537600>;
523 cpu0_opp_2016mhz: opp-2016000000 {
524 opp-hz = /bits/ 64 <2016000000>;
525 opp-peak-kBps = <6220000 48537600>;
529 cpu4_opp_table: opp-table-cpu4 {
530 compatible = "operating-points-v2";
531 opp-shared;
533 cpu4_opp_691mhz: opp-691200000 {
534 opp-hz = /bits/ 64 <691200000>;
535 opp-peak-kBps = <1804000 9600000>;
538 cpu4_opp_941mhz: opp-940800000 {
539 opp-hz = /bits/ 64 <940800000>;
540 opp-peak-kBps = <2188000 17817600>;
543 cpu4_opp_1229mhz: opp-1228800000 {
544 opp-hz = /bits/ 64 <1228800000>;
545 opp-peak-kBps = <4068000 24576000>;
548 cpu4_opp_1344mhz: opp-1344000000 {
549 opp-hz = /bits/ 64 <1344000000>;
550 opp-peak-kBps = <4068000 24576000>;
553 cpu4_opp_1517mhz: opp-1516800000 {
554 opp-hz = /bits/ 64 <1516800000>;
555 opp-peak-kBps = <4068000 24576000>;
558 cpu4_opp_1651mhz: opp-1651200000 {
559 opp-hz = /bits/ 64 <1651200000>;
560 opp-peak-kBps = <6220000 38092800>;
563 cpu4_opp_1901mhz: opp-1900800000 {
564 opp-hz = /bits/ 64 <1900800000>;
565 opp-peak-kBps = <6220000 44851200>;
568 cpu4_opp_2054mhz: opp-2054400000 {
569 opp-hz = /bits/ 64 <2054400000>;
570 opp-peak-kBps = <6220000 44851200>;
573 cpu4_opp_2112mhz: opp-2112000000 {
574 opp-hz = /bits/ 64 <2112000000>;
575 opp-peak-kBps = <6220000 44851200>;
578 cpu4_opp_2131mhz: opp-2131200000 {
579 opp-hz = /bits/ 64 <2131200000>;
580 opp-peak-kBps = <6220000 44851200>;
583 cpu4_opp_2208mhz: opp-2208000000 {
584 opp-hz = /bits/ 64 <2208000000>;
585 opp-peak-kBps = <6220000 44851200>;
588 cpu4_opp_2400mhz: opp-2400000000 {
589 opp-hz = /bits/ 64 <2400000000>;
590 opp-peak-kBps = <8532000 48537600>;
593 cpu4_opp_2611mhz: opp-2611200000 {
594 opp-hz = /bits/ 64 <2611200000>;
595 opp-peak-kBps = <8532000 48537600>;
599 cpu7_opp_table: opp-table-cpu7 {
600 compatible = "operating-points-v2";
601 opp-shared;
603 cpu7_opp_806mhz: opp-806400000 {
604 opp-hz = /bits/ 64 <806400000>;
605 opp-peak-kBps = <1804000 9600000>;
608 cpu7_opp_1056mhz: opp-1056000000 {
609 opp-hz = /bits/ 64 <1056000000>;
610 opp-peak-kBps = <2188000 17817600>;
613 cpu7_opp_1325mhz: opp-1324800000 {
614 opp-hz = /bits/ 64 <1324800000>;
615 opp-peak-kBps = <4068000 24576000>;
618 cpu7_opp_1517mhz: opp-1516800000 {
619 opp-hz = /bits/ 64 <1516800000>;
620 opp-peak-kBps = <4068000 24576000>;
623 cpu7_opp_1766mhz: opp-1766400000 {
624 opp-hz = /bits/ 64 <1766400000>;
625 opp-peak-kBps = <6220000 38092800>;
628 cpu7_opp_1862mhz: opp-1862400000 {
629 opp-hz = /bits/ 64 <1862400000>;
630 opp-peak-kBps = <6220000 38092800>;
633 cpu7_opp_2035mhz: opp-2035200000 {
634 opp-hz = /bits/ 64 <2035200000>;
635 opp-peak-kBps = <6220000 38092800>;
638 cpu7_opp_2112mhz: opp-2112000000 {
639 opp-hz = /bits/ 64 <2112000000>;
640 opp-peak-kBps = <6220000 44851200>;
643 cpu7_opp_2208mhz: opp-2208000000 {
644 opp-hz = /bits/ 64 <2208000000>;
645 opp-peak-kBps = <6220000 44851200>;
648 cpu7_opp_2381mhz: opp-2380800000 {
649 opp-hz = /bits/ 64 <2380800000>;
650 opp-peak-kBps = <6832000 44851200>;
653 cpu7_opp_2400mhz: opp-2400000000 {
654 opp-hz = /bits/ 64 <2400000000>;
655 opp-peak-kBps = <8532000 48537600>;
658 cpu7_opp_2515mhz: opp-2515200000 {
659 opp-hz = /bits/ 64 <2515200000>;
660 opp-peak-kBps = <8532000 48537600>;
663 cpu7_opp_2707mhz: opp-2707200000 {
664 opp-hz = /bits/ 64 <2707200000>;
665 opp-peak-kBps = <8532000 48537600>;
668 cpu7_opp_3014mhz: opp-3014400000 {
669 opp-hz = /bits/ 64 <3014400000>;
670 opp-peak-kBps = <8532000 48537600>;
682 compatible = "qcom,scm-sc7280", "qcom,scm";
687 compatible = "qcom,sc7280-clk-virt";
688 #interconnect-cells = <2>;
689 qcom,bcm-voters = <&apps_bcm_voter>;
694 memory-region = <&smem_mem>;
698 smp2p-adsp {
701 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
707 qcom,local-pid = <0>;
708 qcom,remote-pid = <2>;
710 adsp_smp2p_out: master-kernel {
711 qcom,entry-name = "master-kernel";
712 #qcom,smem-state-cells = <1>;
715 adsp_smp2p_in: slave-kernel {
716 qcom,entry-name = "slave-kernel";
717 interrupt-controller;
718 #interrupt-cells = <2>;
722 smp2p-cdsp {
725 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
731 qcom,local-pid = <0>;
732 qcom,remote-pid = <5>;
734 cdsp_smp2p_out: master-kernel {
735 qcom,entry-name = "master-kernel";
736 #qcom,smem-state-cells = <1>;
739 cdsp_smp2p_in: slave-kernel {
740 qcom,entry-name = "slave-kernel";
741 interrupt-controller;
742 #interrupt-cells = <2>;
746 smp2p-mpss {
749 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
755 qcom,local-pid = <0>;
756 qcom,remote-pid = <1>;
758 modem_smp2p_out: master-kernel {
759 qcom,entry-name = "master-kernel";
760 #qcom,smem-state-cells = <1>;
763 modem_smp2p_in: slave-kernel {
764 qcom,entry-name = "slave-kernel";
765 interrupt-controller;
766 #interrupt-cells = <2>;
769 ipa_smp2p_out: ipa-ap-to-modem {
770 qcom,entry-name = "ipa";
771 #qcom,smem-state-cells = <1>;
774 ipa_smp2p_in: ipa-modem-to-ap {
775 qcom,entry-name = "ipa";
776 interrupt-controller;
777 #interrupt-cells = <2>;
781 smp2p-wpss {
784 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
790 qcom,local-pid = <0>;
791 qcom,remote-pid = <13>;
793 wpss_smp2p_out: master-kernel {
794 qcom,entry-name = "master-kernel";
795 #qcom,smem-state-cells = <1>;
798 wpss_smp2p_in: slave-kernel {
799 qcom,entry-name = "slave-kernel";
800 interrupt-controller;
801 #interrupt-cells = <2>;
804 wlan_smp2p_out: wlan-ap-to-wpss {
805 qcom,entry-name = "wlan";
806 #qcom,smem-state-cells = <1>;
809 wlan_smp2p_in: wlan-wpss-to-ap {
810 qcom,entry-name = "wlan";
811 interrupt-controller;
812 #interrupt-cells = <2>;
817 compatible = "arm,armv8-pmuv3";
822 compatible = "arm,psci-1.0";
825 CPU_PD0: power-domain-cpu0 {
826 #power-domain-cells = <0>;
827 power-domains = <&CLUSTER_PD>;
828 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
831 CPU_PD1: power-domain-cpu1 {
832 #power-domain-cells = <0>;
833 power-domains = <&CLUSTER_PD>;
834 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
837 CPU_PD2: power-domain-cpu2 {
838 #power-domain-cells = <0>;
839 power-domains = <&CLUSTER_PD>;
840 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
843 CPU_PD3: power-domain-cpu3 {
844 #power-domain-cells = <0>;
845 power-domains = <&CLUSTER_PD>;
846 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
849 CPU_PD4: power-domain-cpu4 {
850 #power-domain-cells = <0>;
851 power-domains = <&CLUSTER_PD>;
852 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
855 CPU_PD5: power-domain-cpu5 {
856 #power-domain-cells = <0>;
857 power-domains = <&CLUSTER_PD>;
858 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
861 CPU_PD6: power-domain-cpu6 {
862 #power-domain-cells = <0>;
863 power-domains = <&CLUSTER_PD>;
864 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
867 CPU_PD7: power-domain-cpu7 {
868 #power-domain-cells = <0>;
869 power-domains = <&CLUSTER_PD>;
870 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
873 CLUSTER_PD: power-domain-cluster {
874 #power-domain-cells = <0>;
875 domain-idle-states = <&CLUSTER_SLEEP_0>;
879 qspi_opp_table: opp-table-qspi {
880 compatible = "operating-points-v2";
882 opp-75000000 {
883 opp-hz = /bits/ 64 <75000000>;
884 required-opps = <&rpmhpd_opp_low_svs>;
887 opp-150000000 {
888 opp-hz = /bits/ 64 <150000000>;
889 required-opps = <&rpmhpd_opp_svs>;
892 opp-200000000 {
893 opp-hz = /bits/ 64 <200000000>;
894 required-opps = <&rpmhpd_opp_svs_l1>;
897 opp-300000000 {
898 opp-hz = /bits/ 64 <300000000>;
899 required-opps = <&rpmhpd_opp_nom>;
903 qup_opp_table: opp-table-qup {
904 compatible = "operating-points-v2";
906 opp-75000000 {
907 opp-hz = /bits/ 64 <75000000>;
908 required-opps = <&rpmhpd_opp_low_svs>;
911 opp-100000000 {
912 opp-hz = /bits/ 64 <100000000>;
913 required-opps = <&rpmhpd_opp_svs>;
916 opp-128000000 {
917 opp-hz = /bits/ 64 <128000000>;
918 required-opps = <&rpmhpd_opp_nom>;
923 #address-cells = <2>;
924 #size-cells = <2>;
926 dma-ranges = <0 0 0 0 0x10 0>;
927 compatible = "simple-bus";
929 gcc: clock-controller@100000 {
930 compatible = "qcom,gcc-sc7280";
937 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
942 #clock-cells = <1>;
943 #reset-cells = <1>;
944 #power-domain-cells = <1>;
945 power-domains = <&rpmhpd SC7280_CX>;
949 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
952 interrupt-controller;
953 #interrupt-cells = <3>;
954 #mbox-cells = <2>;
958 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
964 clock-names = "core";
965 power-domains = <&rpmhpd SC7280_MX>;
966 #address-cells = <1>;
967 #size-cells = <1>;
976 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
977 pinctrl-names = "default", "sleep";
978 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
979 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
984 reg-names = "hc", "cqhci";
989 interrupt-names = "hc_irq", "pwr_irq";
994 clock-names = "iface", "core", "xo";
997 interconnect-names = "sdhc-ddr","cpu-sdhc";
998 power-domains = <&rpmhpd SC7280_CX>;
999 operating-points-v2 = <&sdhc1_opp_table>;
1001 bus-width = <8>;
1002 supports-cqe;
1003 dma-coherent;
1005 qcom,dll-config = <0x0007642c>;
1006 qcom,ddr-config = <0x80040868>;
1008 mmc-ddr-1_8v;
1009 mmc-hs200-1_8v;
1010 mmc-hs400-1_8v;
1011 mmc-hs400-enhanced-strobe;
1015 sdhc1_opp_table: opp-table {
1016 compatible = "operating-points-v2";
1018 opp-100000000 {
1019 opp-hz = /bits/ 64 <100000000>;
1020 required-opps = <&rpmhpd_opp_low_svs>;
1021 opp-peak-kBps = <1800000 400000>;
1022 opp-avg-kBps = <100000 0>;
1025 opp-384000000 {
1026 opp-hz = /bits/ 64 <384000000>;
1027 required-opps = <&rpmhpd_opp_nom>;
1028 opp-peak-kBps = <5400000 1600000>;
1029 opp-avg-kBps = <390000 0>;
1034 gpi_dma0: dma-controller@900000 {
1035 #dma-cells = <3>;
1036 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1050 dma-channels = <12>;
1051 dma-channel-mask = <0x7f>;
1057 compatible = "qcom,geni-se-qup";
1061 clock-names = "m-ahb", "s-ahb";
1062 #address-cells = <2>;
1063 #size-cells = <2>;
1069 compatible = "qcom,geni-i2c";
1072 clock-names = "se";
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_i2c0_data_clk>;
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1081 interconnect-names = "qup-core", "qup-config",
1082 "qup-memory";
1083 power-domains = <&rpmhpd SC7280_CX>;
1084 required-opps = <&rpmhpd_opp_low_svs>;
1087 dma-names = "tx", "rx";
1092 compatible = "qcom,geni-spi";
1095 clock-names = "se";
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 power-domains = <&rpmhpd SC7280_CX>;
1102 operating-points-v2 = <&qup_opp_table>;
1105 interconnect-names = "qup-core", "qup-config";
1108 dma-names = "tx", "rx";
1113 compatible = "qcom,geni-uart";
1116 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1120 power-domains = <&rpmhpd SC7280_CX>;
1121 operating-points-v2 = <&qup_opp_table>;
1124 interconnect-names = "qup-core", "qup-config";
1129 compatible = "qcom,geni-i2c";
1132 clock-names = "se";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_i2c1_data_clk>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1141 interconnect-names = "qup-core", "qup-config",
1142 "qup-memory";
1143 power-domains = <&rpmhpd SC7280_CX>;
1144 required-opps = <&rpmhpd_opp_low_svs>;
1147 dma-names = "tx", "rx";
1152 compatible = "qcom,geni-spi";
1155 clock-names = "se";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 power-domains = <&rpmhpd SC7280_CX>;
1162 operating-points-v2 = <&qup_opp_table>;
1165 interconnect-names = "qup-core", "qup-config";
1168 dma-names = "tx", "rx";
1173 compatible = "qcom,geni-uart";
1176 clock-names = "se";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1180 power-domains = <&rpmhpd SC7280_CX>;
1181 operating-points-v2 = <&qup_opp_table>;
1184 interconnect-names = "qup-core", "qup-config";
1189 compatible = "qcom,geni-i2c";
1192 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_i2c2_data_clk>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1201 interconnect-names = "qup-core", "qup-config",
1202 "qup-memory";
1203 power-domains = <&rpmhpd SC7280_CX>;
1204 required-opps = <&rpmhpd_opp_low_svs>;
1207 dma-names = "tx", "rx";
1212 compatible = "qcom,geni-spi";
1215 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 power-domains = <&rpmhpd SC7280_CX>;
1222 operating-points-v2 = <&qup_opp_table>;
1225 interconnect-names = "qup-core", "qup-config";
1228 dma-names = "tx", "rx";
1233 compatible = "qcom,geni-uart";
1236 clock-names = "se";
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1240 power-domains = <&rpmhpd SC7280_CX>;
1241 operating-points-v2 = <&qup_opp_table>;
1244 interconnect-names = "qup-core", "qup-config";
1249 compatible = "qcom,geni-i2c";
1252 clock-names = "se";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_i2c3_data_clk>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1261 interconnect-names = "qup-core", "qup-config",
1262 "qup-memory";
1263 power-domains = <&rpmhpd SC7280_CX>;
1264 required-opps = <&rpmhpd_opp_low_svs>;
1267 dma-names = "tx", "rx";
1272 compatible = "qcom,geni-spi";
1275 clock-names = "se";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1281 power-domains = <&rpmhpd SC7280_CX>;
1282 operating-points-v2 = <&qup_opp_table>;
1285 interconnect-names = "qup-core", "qup-config";
1288 dma-names = "tx", "rx";
1293 compatible = "qcom,geni-uart";
1296 clock-names = "se";
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1300 power-domains = <&rpmhpd SC7280_CX>;
1301 operating-points-v2 = <&qup_opp_table>;
1304 interconnect-names = "qup-core", "qup-config";
1309 compatible = "qcom,geni-i2c";
1312 clock-names = "se";
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&qup_i2c4_data_clk>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1321 interconnect-names = "qup-core", "qup-config",
1322 "qup-memory";
1323 power-domains = <&rpmhpd SC7280_CX>;
1324 required-opps = <&rpmhpd_opp_low_svs>;
1327 dma-names = "tx", "rx";
1332 compatible = "qcom,geni-spi";
1335 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1341 power-domains = <&rpmhpd SC7280_CX>;
1342 operating-points-v2 = <&qup_opp_table>;
1345 interconnect-names = "qup-core", "qup-config";
1348 dma-names = "tx", "rx";
1353 compatible = "qcom,geni-uart";
1356 clock-names = "se";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1360 power-domains = <&rpmhpd SC7280_CX>;
1361 operating-points-v2 = <&qup_opp_table>;
1364 interconnect-names = "qup-core", "qup-config";
1369 compatible = "qcom,geni-i2c";
1372 clock-names = "se";
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&qup_i2c5_data_clk>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1381 interconnect-names = "qup-core", "qup-config",
1382 "qup-memory";
1383 power-domains = <&rpmhpd SC7280_CX>;
1384 required-opps = <&rpmhpd_opp_low_svs>;
1387 dma-names = "tx", "rx";
1392 compatible = "qcom,geni-spi";
1395 clock-names = "se";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 power-domains = <&rpmhpd SC7280_CX>;
1402 operating-points-v2 = <&qup_opp_table>;
1405 interconnect-names = "qup-core", "qup-config";
1408 dma-names = "tx", "rx";
1413 compatible = "qcom,geni-uart";
1416 clock-names = "se";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1420 power-domains = <&rpmhpd SC7280_CX>;
1421 operating-points-v2 = <&qup_opp_table>;
1424 interconnect-names = "qup-core", "qup-config";
1429 compatible = "qcom,geni-i2c";
1432 clock-names = "se";
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&qup_i2c6_data_clk>;
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1441 interconnect-names = "qup-core", "qup-config",
1442 "qup-memory";
1443 power-domains = <&rpmhpd SC7280_CX>;
1444 required-opps = <&rpmhpd_opp_low_svs>;
1447 dma-names = "tx", "rx";
1452 compatible = "qcom,geni-spi";
1455 clock-names = "se";
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1459 #address-cells = <1>;
1460 #size-cells = <0>;
1461 power-domains = <&rpmhpd SC7280_CX>;
1462 operating-points-v2 = <&qup_opp_table>;
1465 interconnect-names = "qup-core", "qup-config";
1468 dma-names = "tx", "rx";
1473 compatible = "qcom,geni-uart";
1476 clock-names = "se";
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1480 power-domains = <&rpmhpd SC7280_CX>;
1481 operating-points-v2 = <&qup_opp_table>;
1484 interconnect-names = "qup-core", "qup-config";
1489 compatible = "qcom,geni-i2c";
1492 clock-names = "se";
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&qup_i2c7_data_clk>;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1501 interconnect-names = "qup-core", "qup-config",
1502 "qup-memory";
1503 power-domains = <&rpmhpd SC7280_CX>;
1504 required-opps = <&rpmhpd_opp_low_svs>;
1507 dma-names = "tx", "rx";
1512 compatible = "qcom,geni-spi";
1515 clock-names = "se";
1516 pinctrl-names = "default";
1517 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1521 power-domains = <&rpmhpd SC7280_CX>;
1522 operating-points-v2 = <&qup_opp_table>;
1525 interconnect-names = "qup-core", "qup-config";
1528 dma-names = "tx", "rx";
1533 compatible = "qcom,geni-uart";
1536 clock-names = "se";
1537 pinctrl-names = "default";
1538 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1540 power-domains = <&rpmhpd SC7280_CX>;
1541 operating-points-v2 = <&qup_opp_table>;
1544 interconnect-names = "qup-core", "qup-config";
1549 gpi_dma1: dma-controller@a00000 {
1550 #dma-cells = <3>;
1551 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1565 dma-channels = <12>;
1566 dma-channel-mask = <0x1e>;
1572 compatible = "qcom,geni-se-qup";
1576 clock-names = "m-ahb", "s-ahb";
1577 #address-cells = <2>;
1578 #size-cells = <2>;
1584 compatible = "qcom,geni-i2c";
1587 clock-names = "se";
1588 pinctrl-names = "default";
1589 pinctrl-0 = <&qup_i2c8_data_clk>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1596 interconnect-names = "qup-core", "qup-config",
1597 "qup-memory";
1598 power-domains = <&rpmhpd SC7280_CX>;
1599 required-opps = <&rpmhpd_opp_low_svs>;
1602 dma-names = "tx", "rx";
1607 compatible = "qcom,geni-spi";
1610 clock-names = "se";
1611 pinctrl-names = "default";
1612 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1616 power-domains = <&rpmhpd SC7280_CX>;
1617 operating-points-v2 = <&qup_opp_table>;
1620 interconnect-names = "qup-core", "qup-config";
1623 dma-names = "tx", "rx";
1628 compatible = "qcom,geni-uart";
1631 clock-names = "se";
1632 pinctrl-names = "default";
1633 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1635 power-domains = <&rpmhpd SC7280_CX>;
1636 operating-points-v2 = <&qup_opp_table>;
1639 interconnect-names = "qup-core", "qup-config";
1644 compatible = "qcom,geni-i2c";
1647 clock-names = "se";
1648 pinctrl-names = "default";
1649 pinctrl-0 = <&qup_i2c9_data_clk>;
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1656 interconnect-names = "qup-core", "qup-config",
1657 "qup-memory";
1658 power-domains = <&rpmhpd SC7280_CX>;
1659 required-opps = <&rpmhpd_opp_low_svs>;
1662 dma-names = "tx", "rx";
1667 compatible = "qcom,geni-spi";
1670 clock-names = "se";
1671 pinctrl-names = "default";
1672 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1676 power-domains = <&rpmhpd SC7280_CX>;
1677 operating-points-v2 = <&qup_opp_table>;
1680 interconnect-names = "qup-core", "qup-config";
1683 dma-names = "tx", "rx";
1688 compatible = "qcom,geni-uart";
1691 clock-names = "se";
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1695 power-domains = <&rpmhpd SC7280_CX>;
1696 operating-points-v2 = <&qup_opp_table>;
1699 interconnect-names = "qup-core", "qup-config";
1704 compatible = "qcom,geni-i2c";
1707 clock-names = "se";
1708 pinctrl-names = "default";
1709 pinctrl-0 = <&qup_i2c10_data_clk>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1716 interconnect-names = "qup-core", "qup-config",
1717 "qup-memory";
1718 power-domains = <&rpmhpd SC7280_CX>;
1719 required-opps = <&rpmhpd_opp_low_svs>;
1722 dma-names = "tx", "rx";
1727 compatible = "qcom,geni-spi";
1730 clock-names = "se";
1731 pinctrl-names = "default";
1732 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1736 power-domains = <&rpmhpd SC7280_CX>;
1737 operating-points-v2 = <&qup_opp_table>;
1740 interconnect-names = "qup-core", "qup-config";
1743 dma-names = "tx", "rx";
1748 compatible = "qcom,geni-uart";
1751 clock-names = "se";
1752 pinctrl-names = "default";
1753 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1755 power-domains = <&rpmhpd SC7280_CX>;
1756 operating-points-v2 = <&qup_opp_table>;
1759 interconnect-names = "qup-core", "qup-config";
1764 compatible = "qcom,geni-i2c";
1767 clock-names = "se";
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&qup_i2c11_data_clk>;
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1776 interconnect-names = "qup-core", "qup-config",
1777 "qup-memory";
1778 power-domains = <&rpmhpd SC7280_CX>;
1779 required-opps = <&rpmhpd_opp_low_svs>;
1782 dma-names = "tx", "rx";
1787 compatible = "qcom,geni-spi";
1790 clock-names = "se";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1796 power-domains = <&rpmhpd SC7280_CX>;
1797 operating-points-v2 = <&qup_opp_table>;
1800 interconnect-names = "qup-core", "qup-config";
1803 dma-names = "tx", "rx";
1808 compatible = "qcom,geni-uart";
1811 clock-names = "se";
1812 pinctrl-names = "default";
1813 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1815 power-domains = <&rpmhpd SC7280_CX>;
1816 operating-points-v2 = <&qup_opp_table>;
1819 interconnect-names = "qup-core", "qup-config";
1824 compatible = "qcom,geni-i2c";
1827 clock-names = "se";
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&qup_i2c12_data_clk>;
1831 #address-cells = <1>;
1832 #size-cells = <0>;
1836 interconnect-names = "qup-core", "qup-config",
1837 "qup-memory";
1838 power-domains = <&rpmhpd SC7280_CX>;
1839 required-opps = <&rpmhpd_opp_low_svs>;
1842 dma-names = "tx", "rx";
1847 compatible = "qcom,geni-spi";
1850 clock-names = "se";
1851 pinctrl-names = "default";
1852 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1854 #address-cells = <1>;
1855 #size-cells = <0>;
1856 power-domains = <&rpmhpd SC7280_CX>;
1857 operating-points-v2 = <&qup_opp_table>;
1860 interconnect-names = "qup-core", "qup-config";
1863 dma-names = "tx", "rx";
1868 compatible = "qcom,geni-uart";
1871 clock-names = "se";
1872 pinctrl-names = "default";
1873 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1875 power-domains = <&rpmhpd SC7280_CX>;
1876 operating-points-v2 = <&qup_opp_table>;
1879 interconnect-names = "qup-core", "qup-config";
1884 compatible = "qcom,geni-i2c";
1887 clock-names = "se";
1888 pinctrl-names = "default";
1889 pinctrl-0 = <&qup_i2c13_data_clk>;
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1896 interconnect-names = "qup-core", "qup-config",
1897 "qup-memory";
1898 power-domains = <&rpmhpd SC7280_CX>;
1899 required-opps = <&rpmhpd_opp_low_svs>;
1902 dma-names = "tx", "rx";
1907 compatible = "qcom,geni-spi";
1910 clock-names = "se";
1911 pinctrl-names = "default";
1912 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1914 #address-cells = <1>;
1915 #size-cells = <0>;
1916 power-domains = <&rpmhpd SC7280_CX>;
1917 operating-points-v2 = <&qup_opp_table>;
1920 interconnect-names = "qup-core", "qup-config";
1923 dma-names = "tx", "rx";
1928 compatible = "qcom,geni-uart";
1931 clock-names = "se";
1932 pinctrl-names = "default";
1933 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1935 power-domains = <&rpmhpd SC7280_CX>;
1936 operating-points-v2 = <&qup_opp_table>;
1939 interconnect-names = "qup-core", "qup-config";
1944 compatible = "qcom,geni-i2c";
1947 clock-names = "se";
1948 pinctrl-names = "default";
1949 pinctrl-0 = <&qup_i2c14_data_clk>;
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1956 interconnect-names = "qup-core", "qup-config",
1957 "qup-memory";
1958 power-domains = <&rpmhpd SC7280_CX>;
1959 required-opps = <&rpmhpd_opp_low_svs>;
1962 dma-names = "tx", "rx";
1967 compatible = "qcom,geni-spi";
1970 clock-names = "se";
1971 pinctrl-names = "default";
1972 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1974 #address-cells = <1>;
1975 #size-cells = <0>;
1976 power-domains = <&rpmhpd SC7280_CX>;
1977 operating-points-v2 = <&qup_opp_table>;
1980 interconnect-names = "qup-core", "qup-config";
1983 dma-names = "tx", "rx";
1988 compatible = "qcom,geni-uart";
1991 clock-names = "se";
1992 pinctrl-names = "default";
1993 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1995 power-domains = <&rpmhpd SC7280_CX>;
1996 operating-points-v2 = <&qup_opp_table>;
1999 interconnect-names = "qup-core", "qup-config";
2004 compatible = "qcom,geni-i2c";
2007 clock-names = "se";
2008 pinctrl-names = "default";
2009 pinctrl-0 = <&qup_i2c15_data_clk>;
2011 #address-cells = <1>;
2012 #size-cells = <0>;
2016 interconnect-names = "qup-core", "qup-config",
2017 "qup-memory";
2018 power-domains = <&rpmhpd SC7280_CX>;
2019 required-opps = <&rpmhpd_opp_low_svs>;
2022 dma-names = "tx", "rx";
2027 compatible = "qcom,geni-spi";
2030 clock-names = "se";
2031 pinctrl-names = "default";
2032 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2034 #address-cells = <1>;
2035 #size-cells = <0>;
2036 power-domains = <&rpmhpd SC7280_CX>;
2037 operating-points-v2 = <&qup_opp_table>;
2040 interconnect-names = "qup-core", "qup-config";
2043 dma-names = "tx", "rx";
2048 compatible = "qcom,geni-uart";
2051 clock-names = "se";
2052 pinctrl-names = "default";
2053 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2055 power-domains = <&rpmhpd SC7280_CX>;
2056 operating-points-v2 = <&qup_opp_table>;
2059 interconnect-names = "qup-core", "qup-config";
2065 compatible = "qcom,sc7280-trng", "qcom,trng";
2071 compatible = "qcom,sc7280-cnoc2";
2072 #interconnect-cells = <2>;
2073 qcom,bcm-voters = <&apps_bcm_voter>;
2078 compatible = "qcom,sc7280-cnoc3";
2079 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&apps_bcm_voter>;
2085 compatible = "qcom,sc7280-mc-virt";
2086 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&apps_bcm_voter>;
2092 compatible = "qcom,sc7280-system-noc";
2093 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&apps_bcm_voter>;
2098 compatible = "qcom,sc7280-aggre1-noc";
2100 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&apps_bcm_voter>;
2106 compatible = "qcom,sc7280-aggre2-noc";
2107 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&apps_bcm_voter>;
2113 compatible = "qcom,sc7280-mmss-noc";
2114 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&apps_bcm_voter>;
2119 compatible = "qcom,wcn6750-wifi";
2155 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2157 qcom,smem-states = <&wlan_smp2p_out 0>;
2158 qcom,smem-state-names = "wlan-smp2p-out";
2162 compatible = "qcom,pcie-sc7280";
2169 reg-names = "parf", "dbi", "elbi", "atu", "config";
2171 linux,pci-domain = <1>;
2172 bus-range = <0x00 0xff>;
2173 num-lanes = <2>;
2175 #address-cells = <3>;
2176 #size-cells = <2>;
2182 interrupt-names = "msi";
2183 #interrupt-cells = <1>;
2184 interrupt-map-mask = <0 0 0 0x7>;
2185 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2204 clock-names = "pipe",
2218 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2219 assigned-clock-rates = <19200000>;
2222 reset-names = "pci";
2224 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2227 phy-names = "pciephy";
2229 pinctrl-names = "default";
2230 pinctrl-0 = <&pcie1_clkreq_n>;
2232 dma-coherent;
2234 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2241 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2248 clock-names = "aux",
2254 clock-output-names = "pcie_1_pipe_clk";
2255 #clock-cells = <0>;
2257 #phy-cells = <0>;
2260 reset-names = "phy";
2262 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2263 assigned-clock-rates = <100000000>;
2269 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2270 "jedec,ufs-2.0";
2274 phy-names = "ufsphy";
2275 lanes-per-direction = <2>;
2276 #reset-cells = <1>;
2278 reset-names = "rst";
2280 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2281 required-opps = <&rpmhpd_opp_nom>;
2284 dma-coherent;
2290 interconnect-names = "ufs-ddr", "cpu-ufs";
2300 clock-names = "core_clk",
2308 freq-table-hz =
2321 compatible = "qcom,sc7280-qmp-ufs-phy";
2326 clock-names = "ref", "ref_aux", "qref";
2328 power-domains = <&rpmhpd SC7280_MX>;
2331 reset-names = "ufsphy";
2333 #clock-cells = <1>;
2334 #phy-cells = <0>;
2339 cryptobam: dma-controller@1dc4000 {
2340 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2343 #dma-cells = <1>;
2347 qcom,controlled-remotely;
2351 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2354 dma-names = "rx", "tx";
2358 interconnect-names = "memory";
2362 compatible = "qcom,sc7280-ipa";
2369 reg-names = "ipa-reg",
2370 "ipa-shared",
2373 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2377 interrupt-names = "ipa",
2379 "ipa-clock-query",
2380 "ipa-setup-ready";
2383 clock-names = "core";
2387 interconnect-names = "memory",
2392 qcom,smem-states = <&ipa_smp2p_out 0>,
2394 qcom,smem-state-names = "ipa-clock-enabled-valid",
2395 "ipa-clock-enabled";
2401 compatible = "qcom,tcsr-mutex";
2403 #hwlock-cells = <1>;
2407 compatible = "qcom,sc7280-tcsr", "syscon";
2412 compatible = "qcom,sc7280-tcsr", "syscon";
2417 compatible = "qcom,sc7280-lpasscc";
2420 reg-names = "qdsp6ss", "top_cc";
2422 clock-names = "iface";
2423 #clock-cells = <1>;
2428 compatible = "qcom,sc7280-lpass-rx-macro";
2431 pinctrl-names = "default";
2432 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2437 clock-names = "mclk", "npl", "fsgen";
2439 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2441 power-domain-names = "macro", "dcodec";
2443 #clock-cells = <0>;
2444 #sound-dai-cells = <1>;
2450 compatible = "qcom,soundwire-v1.6.0";
2455 clock-names = "iface";
2457 qcom,din-ports = <0>;
2458 qcom,dout-ports = <5>;
2461 reset-names = "swr_audio_cgcr";
2463 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2464 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2465 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2466 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2467 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2468 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2469 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2470 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2471 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2473 #sound-dai-cells = <1>;
2474 #address-cells = <2>;
2475 #size-cells = <0>;
2481 compatible = "qcom,sc7280-lpass-tx-macro";
2484 pinctrl-names = "default";
2485 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2490 clock-names = "mclk", "npl", "fsgen";
2492 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2494 power-domain-names = "macro", "dcodec";
2496 #clock-cells = <0>;
2497 #sound-dai-cells = <1>;
2503 compatible = "qcom,soundwire-v1.6.0";
2506 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2509 clock-names = "iface";
2511 qcom,din-ports = <3>;
2512 qcom,dout-ports = <0>;
2515 reset-names = "swr_audio_cgcr";
2517 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2518 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2519 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2522 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2523 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2525 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2527 #sound-dai-cells = <1>;
2528 #address-cells = <2>;
2529 #size-cells = <0>;
2534 lpass_audiocc: clock-controller@3300000 {
2535 compatible = "qcom,sc7280-lpassaudiocc";
2540 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2541 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2542 #clock-cells = <1>;
2543 #power-domain-cells = <1>;
2544 #reset-cells = <1>;
2548 compatible = "qcom,sc7280-lpass-va-macro";
2551 pinctrl-names = "default";
2552 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2555 clock-names = "mclk";
2557 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2559 power-domain-names = "macro", "dcodec";
2561 #clock-cells = <0>;
2562 #sound-dai-cells = <1>;
2567 lpass_aon: clock-controller@3380000 {
2568 compatible = "qcom,sc7280-lpassaoncc";
2573 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2574 #clock-cells = <1>;
2575 #power-domain-cells = <1>;
2579 lpass_core: clock-controller@3900000 {
2580 compatible = "qcom,sc7280-lpasscorecc";
2583 clock-names = "bi_tcxo";
2584 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2585 #clock-cells = <1>;
2586 #power-domain-cells = <1>;
2591 compatible = "qcom,sc7280-lpass-cpu";
2599 reg-names = "lpass-hdmiif",
2600 "lpass-lpaif",
2601 "lpass-rxtx-cdc-dma-lpm",
2602 "lpass-rxtx-lpaif",
2603 "lpass-va-lpaif",
2604 "lpass-va-cdc-dma-lpm";
2610 power-domains = <&rpmhpd SC7280_LCX>;
2611 power-domain-names = "lcx";
2612 required-opps = <&rpmhpd_opp_nom>;
2624 clock-names = "aon_cc_audio_hm_h",
2635 #sound-dai-cells = <1>;
2636 #address-cells = <1>;
2637 #size-cells = <0>;
2643 interrupt-names = "lpass-irq-lpaif",
2644 "lpass-irq-hdmi",
2645 "lpass-irq-vaif",
2646 "lpass-irq-rxtxif";
2651 lpass_hm: clock-controller@3c00000 {
2652 compatible = "qcom,sc7280-lpasshm";
2655 clock-names = "bi_tcxo";
2656 #clock-cells = <1>;
2657 #power-domain-cells = <1>;
2663 compatible = "qcom,sc7280-lpass-ag-noc";
2664 #interconnect-cells = <2>;
2665 qcom,bcm-voters = <&apps_bcm_voter>;
2669 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2672 gpio-controller;
2673 #gpio-cells = <2>;
2674 gpio-ranges = <&lpass_tlmm 0 0 15>;
2676 lpass_dmic01_clk: dmic01-clk-state {
2681 lpass_dmic01_data: dmic01-data-state {
2686 lpass_dmic23_clk: dmic23-clk-state {
2691 lpass_dmic23_data: dmic23-data-state {
2696 lpass_rx_swr_clk: rx-swr-clk-state {
2701 lpass_rx_swr_data: rx-swr-data-state {
2706 lpass_tx_swr_clk: tx-swr-clk-state {
2711 lpass_tx_swr_data: tx-swr-data-state {
2718 compatible = "qcom,adreno-635.0", "qcom,adreno";
2722 reg-names = "kgsl_3d0_reg_memory",
2728 operating-points-v2 = <&gpu_opp_table>;
2731 interconnect-names = "gfx-mem";
2732 #cooling-cells = <2>;
2734 nvmem-cells = <&gpu_speed_bin>;
2735 nvmem-cell-names = "speed_bin";
2737 gpu_zap_shader: zap-shader {
2738 memory-region = <&gpu_zap_mem>;
2741 gpu_opp_table: opp-table {
2742 compatible = "operating-points-v2";
2744 opp-315000000 {
2745 opp-hz = /bits/ 64 <315000000>;
2746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2747 opp-peak-kBps = <1804000>;
2748 opp-supported-hw = <0x07>;
2751 opp-450000000 {
2752 opp-hz = /bits/ 64 <450000000>;
2753 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2754 opp-peak-kBps = <4068000>;
2755 opp-supported-hw = <0x07>;
2759 opp-550000000-0 {
2760 opp-hz = /bits/ 64 <550000000>;
2761 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2762 opp-peak-kBps = <8368000>;
2763 opp-supported-hw = <0x01>;
2766 opp-550000000-1 {
2767 opp-hz = /bits/ 64 <550000000>;
2768 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2769 opp-peak-kBps = <6832000>;
2770 opp-supported-hw = <0x06>;
2773 opp-608000000 {
2774 opp-hz = /bits/ 64 <608000000>;
2775 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2776 opp-peak-kBps = <8368000>;
2777 opp-supported-hw = <0x06>;
2780 opp-700000000 {
2781 opp-hz = /bits/ 64 <700000000>;
2782 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2783 opp-peak-kBps = <8532000>;
2784 opp-supported-hw = <0x06>;
2787 opp-812000000 {
2788 opp-hz = /bits/ 64 <812000000>;
2789 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2790 opp-peak-kBps = <8532000>;
2791 opp-supported-hw = <0x06>;
2794 opp-840000000 {
2795 opp-hz = /bits/ 64 <840000000>;
2796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2797 opp-peak-kBps = <8532000>;
2798 opp-supported-hw = <0x02>;
2801 opp-900000000 {
2802 opp-hz = /bits/ 64 <900000000>;
2803 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2804 opp-peak-kBps = <8532000>;
2805 opp-supported-hw = <0x02>;
2811 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2815 reg-names = "gmu", "rscc", "gmu_pdc";
2818 interrupt-names = "hfi", "gmu";
2826 clock-names = "gmu",
2833 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2835 power-domain-names = "cx",
2838 operating-points-v2 = <&gmu_opp_table>;
2840 gmu_opp_table: opp-table {
2841 compatible = "operating-points-v2";
2843 opp-200000000 {
2844 opp-hz = /bits/ 64 <200000000>;
2845 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2850 gpucc: clock-controller@3d90000 {
2851 compatible = "qcom,sc7280-gpucc";
2856 clock-names = "bi_tcxo",
2859 #clock-cells = <1>;
2860 #reset-cells = <1>;
2861 #power-domain-cells = <1>;
2865 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2871 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2872 "qcom,smmu-500", "arm,mmu-500";
2874 #iommu-cells = <2>;
2875 #global-interrupts = <2>;
2896 clock-names = "gcc_gpu_memnoc_gfx_clk",
2904 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2905 dma-coherent;
2909 compatible = "qcom,sc7280-mpss-pas";
2912 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2918 interrupt-names = "wdog", "fatal", "ready", "handover",
2919 "stop-ack", "shutdown-ack";
2922 clock-names = "xo";
2924 power-domains = <&rpmhpd SC7280_CX>,
2926 power-domain-names = "cx", "mss";
2928 memory-region = <&mpss_mem>;
2932 qcom,smem-states = <&modem_smp2p_out 0>;
2933 qcom,smem-state-names = "stop";
2937 glink-edge {
2938 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2944 qcom,remote-pid = <1>;
2949 compatible = "arm,coresight-stm", "arm,primecell";
2952 reg-names = "stm-base", "stm-stimulus-base";
2955 clock-names = "apb_pclk";
2957 out-ports {
2960 remote-endpoint = <&funnel0_in7>;
2967 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2971 clock-names = "apb_pclk";
2973 out-ports {
2976 remote-endpoint = <&merge_funnel_in0>;
2981 in-ports {
2982 #address-cells = <1>;
2983 #size-cells = <0>;
2988 remote-endpoint = <&stm_out>;
2995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2999 clock-names = "apb_pclk";
3001 out-ports {
3004 remote-endpoint = <&merge_funnel_in1>;
3009 in-ports {
3010 #address-cells = <1>;
3011 #size-cells = <0>;
3016 remote-endpoint = <&apss_merge_funnel_out>;
3023 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3027 clock-names = "apb_pclk";
3029 out-ports {
3032 remote-endpoint = <&swao_funnel_in>;
3037 in-ports {
3038 #address-cells = <1>;
3039 #size-cells = <0>;
3044 remote-endpoint = <&funnel0_out>;
3051 remote-endpoint = <&funnel1_out>;
3058 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3062 clock-names = "apb_pclk";
3064 out-ports {
3067 remote-endpoint = <&etr_in>;
3072 in-ports {
3075 remote-endpoint = <&swao_replicator_out>;
3082 compatible = "arm,coresight-tmc", "arm,primecell";
3087 clock-names = "apb_pclk";
3088 arm,scatter-gather;
3090 in-ports {
3093 remote-endpoint = <&replicator_out>;
3100 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3104 clock-names = "apb_pclk";
3106 out-ports {
3109 remote-endpoint = <&etf_in>;
3114 in-ports {
3115 #address-cells = <1>;
3116 #size-cells = <0>;
3121 remote-endpoint = <&merge_funnel_out>;
3128 compatible = "arm,coresight-tmc", "arm,primecell";
3132 clock-names = "apb_pclk";
3134 out-ports {
3137 remote-endpoint = <&swao_replicator_in>;
3142 in-ports {
3145 remote-endpoint = <&swao_funnel_out>;
3152 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3156 clock-names = "apb_pclk";
3157 qcom,replicator-loses-context;
3159 out-ports {
3162 remote-endpoint = <&replicator_in>;
3167 in-ports {
3170 remote-endpoint = <&etf_out>;
3177 compatible = "arm,coresight-etm4x", "arm,primecell";
3183 clock-names = "apb_pclk";
3184 arm,coresight-loses-context-with-cpu;
3185 qcom,skip-power-up;
3187 out-ports {
3190 remote-endpoint = <&apss_funnel_in0>;
3197 compatible = "arm,coresight-etm4x", "arm,primecell";
3203 clock-names = "apb_pclk";
3204 arm,coresight-loses-context-with-cpu;
3205 qcom,skip-power-up;
3207 out-ports {
3210 remote-endpoint = <&apss_funnel_in1>;
3217 compatible = "arm,coresight-etm4x", "arm,primecell";
3223 clock-names = "apb_pclk";
3224 arm,coresight-loses-context-with-cpu;
3225 qcom,skip-power-up;
3227 out-ports {
3230 remote-endpoint = <&apss_funnel_in2>;
3237 compatible = "arm,coresight-etm4x", "arm,primecell";
3243 clock-names = "apb_pclk";
3244 arm,coresight-loses-context-with-cpu;
3245 qcom,skip-power-up;
3247 out-ports {
3250 remote-endpoint = <&apss_funnel_in3>;
3257 compatible = "arm,coresight-etm4x", "arm,primecell";
3263 clock-names = "apb_pclk";
3264 arm,coresight-loses-context-with-cpu;
3265 qcom,skip-power-up;
3267 out-ports {
3270 remote-endpoint = <&apss_funnel_in4>;
3277 compatible = "arm,coresight-etm4x", "arm,primecell";
3283 clock-names = "apb_pclk";
3284 arm,coresight-loses-context-with-cpu;
3285 qcom,skip-power-up;
3287 out-ports {
3290 remote-endpoint = <&apss_funnel_in5>;
3297 compatible = "arm,coresight-etm4x", "arm,primecell";
3303 clock-names = "apb_pclk";
3304 arm,coresight-loses-context-with-cpu;
3305 qcom,skip-power-up;
3307 out-ports {
3310 remote-endpoint = <&apss_funnel_in6>;
3317 compatible = "arm,coresight-etm4x", "arm,primecell";
3323 clock-names = "apb_pclk";
3324 arm,coresight-loses-context-with-cpu;
3325 qcom,skip-power-up;
3327 out-ports {
3330 remote-endpoint = <&apss_funnel_in7>;
3337 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3341 clock-names = "apb_pclk";
3343 out-ports {
3346 remote-endpoint = <&apss_merge_funnel_in>;
3351 in-ports {
3352 #address-cells = <1>;
3353 #size-cells = <0>;
3358 remote-endpoint = <&etm0_out>;
3365 remote-endpoint = <&etm1_out>;
3372 remote-endpoint = <&etm2_out>;
3379 remote-endpoint = <&etm3_out>;
3386 remote-endpoint = <&etm4_out>;
3393 remote-endpoint = <&etm5_out>;
3400 remote-endpoint = <&etm6_out>;
3407 remote-endpoint = <&etm7_out>;
3414 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3418 clock-names = "apb_pclk";
3420 out-ports {
3423 remote-endpoint = <&funnel1_in4>;
3428 in-ports {
3431 remote-endpoint = <&apss_funnel_out>;
3438 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3439 pinctrl-names = "default", "sleep";
3440 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3441 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3449 interrupt-names = "hc_irq", "pwr_irq";
3454 clock-names = "iface", "core", "xo";
3457 interconnect-names = "sdhc-ddr","cpu-sdhc";
3458 power-domains = <&rpmhpd SC7280_CX>;
3459 operating-points-v2 = <&sdhc2_opp_table>;
3461 bus-width = <4>;
3462 dma-coherent;
3464 qcom,dll-config = <0x0007642c>;
3468 sdhc2_opp_table: opp-table {
3469 compatible = "operating-points-v2";
3471 opp-100000000 {
3472 opp-hz = /bits/ 64 <100000000>;
3473 required-opps = <&rpmhpd_opp_low_svs>;
3474 opp-peak-kBps = <1800000 400000>;
3475 opp-avg-kBps = <100000 0>;
3478 opp-202000000 {
3479 opp-hz = /bits/ 64 <202000000>;
3480 required-opps = <&rpmhpd_opp_nom>;
3481 opp-peak-kBps = <5400000 1600000>;
3482 opp-avg-kBps = <200000 0>;
3488 compatible = "qcom,sc7280-usb-hs-phy",
3489 "qcom,usb-snps-hs-7nm-phy";
3492 #phy-cells = <0>;
3495 clock-names = "ref";
3501 compatible = "qcom,sc7280-usb-hs-phy",
3502 "qcom,usb-snps-hs-7nm-phy";
3505 #phy-cells = <0>;
3508 clock-names = "ref";
3514 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3522 clock-names = "aux",
3529 reset-names = "phy", "common";
3531 #clock-cells = <1>;
3532 #phy-cells = <1>;
3535 #address-cells = <1>;
3536 #size-cells = <0>;
3562 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3565 #address-cells = <2>;
3566 #size-cells = <2>;
3568 dma-ranges;
3575 clock-names = "cfg_noc",
3581 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3583 assigned-clock-rates = <19200000>, <200000000>;
3585 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3588 interrupt-names = "hs_phy_irq",
3592 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3593 required-opps = <&rpmhpd_opp_nom>;
3599 interconnect-names = "usb-ddr", "apps-usb";
3609 phy-names = "usb2-phy";
3610 maximum-speed = "high-speed";
3611 usb-role-switch;
3615 remote-endpoint = <&eud_ep>;
3622 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3625 #address-cells = <1>;
3626 #size-cells = <0>;
3630 clock-names = "iface", "core";
3633 interconnect-names = "qspi-config";
3634 power-domains = <&rpmhpd SC7280_CX>;
3635 operating-points-v2 = <&qspi_opp_table>;
3640 compatible = "qcom,sc7280-adsp-pas";
3643 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3649 interrupt-names = "wdog", "fatal", "ready", "handover",
3650 "stop-ack", "shutdown-ack";
3653 clock-names = "xo";
3655 power-domains = <&rpmhpd SC7280_LCX>,
3657 power-domain-names = "lcx", "lmx";
3659 memory-region = <&adsp_mem>;
3663 qcom,smem-states = <&adsp_smp2p_out 0>;
3664 qcom,smem-state-names = "stop";
3668 glink-edge {
3669 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3677 qcom,remote-pid = <2>;
3681 qcom,glink-channels = "fastrpcglink-apps-dsp";
3683 qcom,non-secure-domain;
3684 #address-cells = <1>;
3685 #size-cells = <0>;
3687 compute-cb@3 {
3688 compatible = "qcom,fastrpc-compute-cb";
3693 compute-cb@4 {
3694 compatible = "qcom,fastrpc-compute-cb";
3699 compute-cb@5 {
3700 compatible = "qcom,fastrpc-compute-cb";
3709 compatible = "qcom,sc7280-wpss-pas";
3712 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3718 interrupt-names = "wdog", "fatal", "ready", "handover",
3719 "stop-ack", "shutdown-ack";
3722 clock-names = "xo";
3724 power-domains = <&rpmhpd SC7280_CX>,
3726 power-domain-names = "cx", "mx";
3728 memory-region = <&wpss_mem>;
3732 qcom,smem-states = <&wpss_smp2p_out 0>;
3733 qcom,smem-state-names = "stop";
3738 glink-edge {
3739 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3746 qcom,remote-pid = <13>;
3751 compatible = "qcom,sc7280-llcc-bwmon";
3758 operating-points-v2 = <&llcc_bwmon_opp_table>;
3760 llcc_bwmon_opp_table: opp-table {
3761 compatible = "operating-points-v2";
3763 opp-0 {
3764 opp-peak-kBps = <800000>;
3766 opp-1 {
3767 opp-peak-kBps = <1804000>;
3769 opp-2 {
3770 opp-peak-kBps = <2188000>;
3772 opp-3 {
3773 opp-peak-kBps = <3072000>;
3775 opp-4 {
3776 opp-peak-kBps = <4068000>;
3778 opp-5 {
3779 opp-peak-kBps = <6220000>;
3781 opp-6 {
3782 opp-peak-kBps = <6832000>;
3784 opp-7 {
3785 opp-peak-kBps = <8532000>;
3791 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3797 operating-points-v2 = <&cpu_bwmon_opp_table>;
3799 cpu_bwmon_opp_table: opp-table {
3800 compatible = "operating-points-v2";
3802 opp-0 {
3803 opp-peak-kBps = <2400000>;
3805 opp-1 {
3806 opp-peak-kBps = <4800000>;
3808 opp-2 {
3809 opp-peak-kBps = <7456000>;
3811 opp-3 {
3812 opp-peak-kBps = <9600000>;
3814 opp-4 {
3815 opp-peak-kBps = <12896000>;
3817 opp-5 {
3818 opp-peak-kBps = <14928000>;
3820 opp-6 {
3821 opp-peak-kBps = <17056000>;
3828 compatible = "qcom,sc7280-dc-noc";
3829 #interconnect-cells = <2>;
3830 qcom,bcm-voters = <&apps_bcm_voter>;
3835 compatible = "qcom,sc7280-gem-noc";
3836 #interconnect-cells = <2>;
3837 qcom,bcm-voters = <&apps_bcm_voter>;
3840 system-cache-controller@9200000 {
3841 compatible = "qcom,sc7280-llcc";
3844 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
3849 compatible = "qcom,sc7280-eud", "qcom,eud";
3852 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3857 #address-cells = <1>;
3858 #size-cells = <0>;
3863 remote-endpoint = <&usb2_role_switch>;
3871 compatible = "qcom,sc7280-nsp-noc";
3872 #interconnect-cells = <2>;
3873 qcom,bcm-voters = <&apps_bcm_voter>;
3877 compatible = "qcom,sc7280-cdsp-pas";
3880 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3886 interrupt-names = "wdog", "fatal", "ready", "handover",
3887 "stop-ack", "shutdown-ack";
3890 clock-names = "xo";
3892 power-domains = <&rpmhpd SC7280_CX>,
3894 power-domain-names = "cx", "mx";
3898 memory-region = <&cdsp_mem>;
3902 qcom,smem-states = <&cdsp_smp2p_out 0>;
3903 qcom,smem-state-names = "stop";
3907 glink-edge {
3908 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3915 qcom,remote-pid = <5>;
3919 qcom,glink-channels = "fastrpcglink-apps-dsp";
3921 qcom,non-secure-domain;
3922 #address-cells = <1>;
3923 #size-cells = <0>;
3925 compute-cb@1 {
3926 compatible = "qcom,fastrpc-compute-cb";
3932 compute-cb@2 {
3933 compatible = "qcom,fastrpc-compute-cb";
3939 compute-cb@3 {
3940 compatible = "qcom,fastrpc-compute-cb";
3946 compute-cb@4 {
3947 compatible = "qcom,fastrpc-compute-cb";
3953 compute-cb@5 {
3954 compatible = "qcom,fastrpc-compute-cb";
3960 compute-cb@6 {
3961 compatible = "qcom,fastrpc-compute-cb";
3967 compute-cb@7 {
3968 compatible = "qcom,fastrpc-compute-cb";
3974 compute-cb@8 {
3975 compatible = "qcom,fastrpc-compute-cb";
3983 compute-cb@11 {
3984 compatible = "qcom,fastrpc-compute-cb";
3990 compute-cb@12 {
3991 compatible = "qcom,fastrpc-compute-cb";
3997 compute-cb@13 {
3998 compatible = "qcom,fastrpc-compute-cb";
4004 compute-cb@14 {
4005 compatible = "qcom,fastrpc-compute-cb";
4015 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
4018 #address-cells = <2>;
4019 #size-cells = <2>;
4021 dma-ranges;
4028 clock-names = "cfg_noc",
4034 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4036 assigned-clock-rates = <19200000>, <200000000>;
4038 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4042 interrupt-names = "hs_phy_irq",
4047 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4048 required-opps = <&rpmhpd_opp_nom>;
4054 interconnect-names = "usb-ddr", "apps-usb";
4056 wakeup-source;
4066 phy-names = "usb2-phy", "usb3-phy";
4067 maximum-speed = "super-speed";
4071 venus: video-codec@aa00000 {
4072 compatible = "qcom,sc7280-venus";
4081 clock-names = "core", "bus", "iface",
4084 power-domains = <&videocc MVSC_GDSC>,
4087 power-domain-names = "venus", "vcodec0", "cx";
4088 operating-points-v2 = <&venus_opp_table>;
4092 interconnect-names = "cpu-cfg", "video-mem";
4096 memory-region = <&video_mem>;
4098 video-decoder {
4099 compatible = "venus-decoder";
4102 video-encoder {
4103 compatible = "venus-encoder";
4106 video-firmware {
4110 venus_opp_table: opp-table {
4111 compatible = "operating-points-v2";
4113 opp-133330000 {
4114 opp-hz = /bits/ 64 <133330000>;
4115 required-opps = <&rpmhpd_opp_low_svs>;
4118 opp-240000000 {
4119 opp-hz = /bits/ 64 <240000000>;
4120 required-opps = <&rpmhpd_opp_svs>;
4123 opp-335000000 {
4124 opp-hz = /bits/ 64 <335000000>;
4125 required-opps = <&rpmhpd_opp_svs_l1>;
4128 opp-424000000 {
4129 opp-hz = /bits/ 64 <424000000>;
4130 required-opps = <&rpmhpd_opp_nom>;
4133 opp-460000048 {
4134 opp-hz = /bits/ 64 <460000048>;
4135 required-opps = <&rpmhpd_opp_turbo>;
4140 videocc: clock-controller@aaf0000 {
4141 compatible = "qcom,sc7280-videocc";
4145 clock-names = "bi_tcxo", "bi_tcxo_ao";
4146 #clock-cells = <1>;
4147 #reset-cells = <1>;
4148 #power-domain-cells = <1>;
4152 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4155 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4162 clock-names = "camnoc_axi",
4167 pinctrl-0 = <&cci0_default &cci1_default>;
4168 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4169 pinctrl-names = "default", "sleep";
4171 #address-cells = <1>;
4172 #size-cells = <0>;
4176 cci0_i2c0: i2c-bus@0 {
4178 clock-frequency = <1000000>;
4179 #address-cells = <1>;
4180 #size-cells = <0>;
4183 cci0_i2c1: i2c-bus@1 {
4185 clock-frequency = <1000000>;
4186 #address-cells = <1>;
4187 #size-cells = <0>;
4192 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4195 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4202 clock-names = "camnoc_axi",
4207 pinctrl-0 = <&cci2_default &cci3_default>;
4208 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4209 pinctrl-names = "default", "sleep";
4211 #address-cells = <1>;
4212 #size-cells = <0>;
4216 cci1_i2c0: i2c-bus@0 {
4218 clock-frequency = <1000000>;
4219 #address-cells = <1>;
4220 #size-cells = <0>;
4223 cci1_i2c1: i2c-bus@1 {
4225 clock-frequency = <1000000>;
4226 #address-cells = <1>;
4227 #size-cells = <0>;
4231 camcc: clock-controller@ad00000 {
4232 compatible = "qcom,sc7280-camcc";
4237 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4238 #clock-cells = <1>;
4239 #reset-cells = <1>;
4240 #power-domain-cells = <1>;
4243 dispcc: clock-controller@af00000 {
4244 compatible = "qcom,sc7280-dispcc";
4254 clock-names = "bi_tcxo",
4262 #clock-cells = <1>;
4263 #reset-cells = <1>;
4264 #power-domain-cells = <1>;
4267 mdss: display-subsystem@ae00000 {
4268 compatible = "qcom,sc7280-mdss";
4270 reg-names = "mdss";
4272 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
4277 clock-names = "iface",
4282 interrupt-controller;
4283 #interrupt-cells = <1>;
4289 interconnect-names = "mdp0-mem",
4290 "cpu-cfg";
4294 #address-cells = <2>;
4295 #size-cells = <2>;
4300 mdss_mdp: display-controller@ae01000 {
4301 compatible = "qcom,sc7280-dpu";
4304 reg-names = "mdp", "vbif";
4312 clock-names = "bus",
4318 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
4320 assigned-clock-rates = <19200000>,
4322 operating-points-v2 = <&mdp_opp_table>;
4323 power-domains = <&rpmhpd SC7280_CX>;
4325 interrupt-parent = <&mdss>;
4329 #address-cells = <1>;
4330 #size-cells = <0>;
4335 remote-endpoint = <&mdss_dsi0_in>;
4342 remote-endpoint = <&edp_in>;
4349 remote-endpoint = <&dp_in>;
4354 mdp_opp_table: opp-table {
4355 compatible = "operating-points-v2";
4357 opp-200000000 {
4358 opp-hz = /bits/ 64 <200000000>;
4359 required-opps = <&rpmhpd_opp_low_svs>;
4362 opp-300000000 {
4363 opp-hz = /bits/ 64 <300000000>;
4364 required-opps = <&rpmhpd_opp_svs>;
4367 opp-380000000 {
4368 opp-hz = /bits/ 64 <380000000>;
4369 required-opps = <&rpmhpd_opp_svs_l1>;
4372 opp-506666667 {
4373 opp-hz = /bits/ 64 <506666667>;
4374 required-opps = <&rpmhpd_opp_nom>;
4380 compatible = "qcom,sc7280-dsi-ctrl",
4381 "qcom,mdss-dsi-ctrl";
4383 reg-names = "dsi_ctrl";
4385 interrupt-parent = <&mdss>;
4394 clock-names = "byte",
4401 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4402 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4404 operating-points-v2 = <&dsi_opp_table>;
4405 power-domains = <&rpmhpd SC7280_CX>;
4409 #address-cells = <1>;
4410 #size-cells = <0>;
4415 #address-cells = <1>;
4416 #size-cells = <0>;
4421 remote-endpoint = <&dpu_intf1_out>;
4432 dsi_opp_table: opp-table {
4433 compatible = "operating-points-v2";
4435 opp-187500000 {
4436 opp-hz = /bits/ 64 <187500000>;
4437 required-opps = <&rpmhpd_opp_low_svs>;
4440 opp-300000000 {
4441 opp-hz = /bits/ 64 <300000000>;
4442 required-opps = <&rpmhpd_opp_svs>;
4445 opp-358000000 {
4446 opp-hz = /bits/ 64 <358000000>;
4447 required-opps = <&rpmhpd_opp_svs_l1>;
4453 compatible = "qcom,sc7280-dsi-phy-7nm";
4457 reg-names = "dsi_phy",
4461 #clock-cells = <1>;
4462 #phy-cells = <0>;
4466 clock-names = "iface", "ref";
4472 compatible = "qcom,sc7280-edp";
4473 pinctrl-names = "default";
4474 pinctrl-0 = <&edp_hot_plug_det>;
4481 interrupt-parent = <&mdss>;
4489 clock-names = "core_iface",
4494 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4496 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4499 phy-names = "dp";
4501 operating-points-v2 = <&edp_opp_table>;
4502 power-domains = <&rpmhpd SC7280_CX>;
4507 #address-cells = <1>;
4508 #size-cells = <0>;
4513 remote-endpoint = <&dpu_intf5_out>;
4523 edp_opp_table: opp-table {
4524 compatible = "operating-points-v2";
4526 opp-160000000 {
4527 opp-hz = /bits/ 64 <160000000>;
4528 required-opps = <&rpmhpd_opp_low_svs>;
4531 opp-270000000 {
4532 opp-hz = /bits/ 64 <270000000>;
4533 required-opps = <&rpmhpd_opp_svs>;
4536 opp-540000000 {
4537 opp-hz = /bits/ 64 <540000000>;
4538 required-opps = <&rpmhpd_opp_nom>;
4541 opp-810000000 {
4542 opp-hz = /bits/ 64 <810000000>;
4543 required-opps = <&rpmhpd_opp_nom>;
4549 compatible = "qcom,sc7280-edp-phy";
4558 clock-names = "aux",
4561 #clock-cells = <1>;
4562 #phy-cells = <0>;
4567 mdss_dp: displayport-controller@ae90000 {
4568 compatible = "qcom,sc7280-dp";
4576 interrupt-parent = <&mdss>;
4584 clock-names = "core_iface",
4589 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4591 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4594 phy-names = "dp";
4596 operating-points-v2 = <&dp_opp_table>;
4597 power-domains = <&rpmhpd SC7280_CX>;
4599 #sound-dai-cells = <0>;
4604 #address-cells = <1>;
4605 #size-cells = <0>;
4610 remote-endpoint = <&dpu_intf0_out>;
4620 dp_opp_table: opp-table {
4621 compatible = "operating-points-v2";
4623 opp-160000000 {
4624 opp-hz = /bits/ 64 <160000000>;
4625 required-opps = <&rpmhpd_opp_low_svs>;
4628 opp-270000000 {
4629 opp-hz = /bits/ 64 <270000000>;
4630 required-opps = <&rpmhpd_opp_svs>;
4633 opp-540000000 {
4634 opp-hz = /bits/ 64 <540000000>;
4635 required-opps = <&rpmhpd_opp_svs_l1>;
4638 opp-810000000 {
4639 opp-hz = /bits/ 64 <810000000>;
4640 required-opps = <&rpmhpd_opp_nom>;
4646 pdc: interrupt-controller@b220000 {
4647 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4649 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4654 #interrupt-cells = <2>;
4655 interrupt-parent = <&intc>;
4656 interrupt-controller;
4659 pdc_reset: reset-controller@b5e0000 {
4660 compatible = "qcom,sc7280-pdc-global";
4662 #reset-cells = <1>;
4666 tsens0: thermal-sensor@c263000 {
4667 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4673 interrupt-names = "uplow","critical";
4674 #thermal-sensor-cells = <1>;
4677 tsens1: thermal-sensor@c265000 {
4678 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4684 interrupt-names = "uplow","critical";
4685 #thermal-sensor-cells = <1>;
4688 aoss_reset: reset-controller@c2a0000 {
4689 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4691 #reset-cells = <1>;
4694 aoss_qmp: power-management@c300000 {
4695 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4697 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4703 #clock-cells = <0>;
4707 compatible = "qcom,rpmh-stats";
4712 compatible = "qcom,spmi-pmic-arb";
4718 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4719 interrupt-names = "periph_irq";
4720 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4723 #address-cells = <2>;
4724 #size-cells = <0>;
4725 interrupt-controller;
4726 #interrupt-cells = <4>;
4730 compatible = "qcom,sc7280-pinctrl";
4733 gpio-controller;
4734 #gpio-cells = <2>;
4735 interrupt-controller;
4736 #interrupt-cells = <2>;
4737 gpio-ranges = <&tlmm 0 0 175>;
4738 wakeup-parent = <&pdc>;
4740 cci0_default: cci0-default-state {
4743 drive-strength = <2>;
4744 bias-pull-up;
4747 cci0_sleep: cci0-sleep-state {
4750 drive-strength = <2>;
4751 bias-pull-down;
4754 cci1_default: cci1-default-state {
4757 drive-strength = <2>;
4758 bias-pull-up;
4761 cci1_sleep: cci1-sleep-state {
4764 drive-strength = <2>;
4765 bias-pull-down;
4768 cci2_default: cci2-default-state {
4771 drive-strength = <2>;
4772 bias-pull-up;
4775 cci2_sleep: cci2-sleep-state {
4778 drive-strength = <2>;
4779 bias-pull-down;
4782 cci3_default: cci3-default-state {
4785 drive-strength = <2>;
4786 bias-pull-up;
4789 cci3_sleep: cci3-sleep-state {
4792 drive-strength = <2>;
4793 bias-pull-down;
4796 dp_hot_plug_det: dp-hot-plug-det-state {
4801 edp_hot_plug_det: edp-hot-plug-det-state {
4806 mi2s0_data0: mi2s0-data0-state {
4811 mi2s0_data1: mi2s0-data1-state {
4816 mi2s0_mclk: mi2s0-mclk-state {
4821 mi2s0_sclk: mi2s0-sclk-state {
4826 mi2s0_ws: mi2s0-ws-state {
4831 mi2s1_data0: mi2s1-data0-state {
4836 mi2s1_sclk: mi2s1-sclk-state {
4841 mi2s1_ws: mi2s1-ws-state {
4846 pcie1_clkreq_n: pcie1-clkreq-n-state {
4851 qspi_clk: qspi-clk-state {
4856 qspi_cs0: qspi-cs0-state {
4861 qspi_cs1: qspi-cs1-state {
4866 qspi_data0: qspi-data0-state {
4871 qspi_data1: qspi-data1-state {
4876 qspi_data23: qspi-data23-state {
4881 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4886 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4891 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4896 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4901 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4906 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4911 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4916 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4921 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4926 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4931 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4936 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4941 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4946 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4951 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4956 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4961 qup_spi0_data_clk: qup-spi0-data-clk-state {
4966 qup_spi0_cs: qup-spi0-cs-state {
4971 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4976 qup_spi1_data_clk: qup-spi1-data-clk-state {
4981 qup_spi1_cs: qup-spi1-cs-state {
4986 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4991 qup_spi2_data_clk: qup-spi2-data-clk-state {
4996 qup_spi2_cs: qup-spi2-cs-state {
5001 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5006 qup_spi3_data_clk: qup-spi3-data-clk-state {
5011 qup_spi3_cs: qup-spi3-cs-state {
5016 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5021 qup_spi4_data_clk: qup-spi4-data-clk-state {
5026 qup_spi4_cs: qup-spi4-cs-state {
5031 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5036 qup_spi5_data_clk: qup-spi5-data-clk-state {
5041 qup_spi5_cs: qup-spi5-cs-state {
5046 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5051 qup_spi6_data_clk: qup-spi6-data-clk-state {
5056 qup_spi6_cs: qup-spi6-cs-state {
5061 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5066 qup_spi7_data_clk: qup-spi7-data-clk-state {
5071 qup_spi7_cs: qup-spi7-cs-state {
5076 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5081 qup_spi8_data_clk: qup-spi8-data-clk-state {
5086 qup_spi8_cs: qup-spi8-cs-state {
5091 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5096 qup_spi9_data_clk: qup-spi9-data-clk-state {
5101 qup_spi9_cs: qup-spi9-cs-state {
5106 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5111 qup_spi10_data_clk: qup-spi10-data-clk-state {
5116 qup_spi10_cs: qup-spi10-cs-state {
5121 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5126 qup_spi11_data_clk: qup-spi11-data-clk-state {
5131 qup_spi11_cs: qup-spi11-cs-state {
5136 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5141 qup_spi12_data_clk: qup-spi12-data-clk-state {
5146 qup_spi12_cs: qup-spi12-cs-state {
5151 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5156 qup_spi13_data_clk: qup-spi13-data-clk-state {
5161 qup_spi13_cs: qup-spi13-cs-state {
5166 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5171 qup_spi14_data_clk: qup-spi14-data-clk-state {
5176 qup_spi14_cs: qup-spi14-cs-state {
5181 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5186 qup_spi15_data_clk: qup-spi15-data-clk-state {
5191 qup_spi15_cs: qup-spi15-cs-state {
5196 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5201 qup_uart0_cts: qup-uart0-cts-state {
5206 qup_uart0_rts: qup-uart0-rts-state {
5211 qup_uart0_tx: qup-uart0-tx-state {
5216 qup_uart0_rx: qup-uart0-rx-state {
5221 qup_uart1_cts: qup-uart1-cts-state {
5226 qup_uart1_rts: qup-uart1-rts-state {
5231 qup_uart1_tx: qup-uart1-tx-state {
5236 qup_uart1_rx: qup-uart1-rx-state {
5241 qup_uart2_cts: qup-uart2-cts-state {
5246 qup_uart2_rts: qup-uart2-rts-state {
5251 qup_uart2_tx: qup-uart2-tx-state {
5256 qup_uart2_rx: qup-uart2-rx-state {
5261 qup_uart3_cts: qup-uart3-cts-state {
5266 qup_uart3_rts: qup-uart3-rts-state {
5271 qup_uart3_tx: qup-uart3-tx-state {
5276 qup_uart3_rx: qup-uart3-rx-state {
5281 qup_uart4_cts: qup-uart4-cts-state {
5286 qup_uart4_rts: qup-uart4-rts-state {
5291 qup_uart4_tx: qup-uart4-tx-state {
5296 qup_uart4_rx: qup-uart4-rx-state {
5301 qup_uart5_cts: qup-uart5-cts-state {
5306 qup_uart5_rts: qup-uart5-rts-state {
5311 qup_uart5_tx: qup-uart5-tx-state {
5316 qup_uart5_rx: qup-uart5-rx-state {
5321 qup_uart6_cts: qup-uart6-cts-state {
5326 qup_uart6_rts: qup-uart6-rts-state {
5331 qup_uart6_tx: qup-uart6-tx-state {
5336 qup_uart6_rx: qup-uart6-rx-state {
5341 qup_uart7_cts: qup-uart7-cts-state {
5346 qup_uart7_rts: qup-uart7-rts-state {
5351 qup_uart7_tx: qup-uart7-tx-state {
5356 qup_uart7_rx: qup-uart7-rx-state {
5361 qup_uart8_cts: qup-uart8-cts-state {
5366 qup_uart8_rts: qup-uart8-rts-state {
5371 qup_uart8_tx: qup-uart8-tx-state {
5376 qup_uart8_rx: qup-uart8-rx-state {
5381 qup_uart9_cts: qup-uart9-cts-state {
5386 qup_uart9_rts: qup-uart9-rts-state {
5391 qup_uart9_tx: qup-uart9-tx-state {
5396 qup_uart9_rx: qup-uart9-rx-state {
5401 qup_uart10_cts: qup-uart10-cts-state {
5406 qup_uart10_rts: qup-uart10-rts-state {
5411 qup_uart10_tx: qup-uart10-tx-state {
5416 qup_uart10_rx: qup-uart10-rx-state {
5421 qup_uart11_cts: qup-uart11-cts-state {
5426 qup_uart11_rts: qup-uart11-rts-state {
5431 qup_uart11_tx: qup-uart11-tx-state {
5436 qup_uart11_rx: qup-uart11-rx-state {
5441 qup_uart12_cts: qup-uart12-cts-state {
5446 qup_uart12_rts: qup-uart12-rts-state {
5451 qup_uart12_tx: qup-uart12-tx-state {
5456 qup_uart12_rx: qup-uart12-rx-state {
5461 qup_uart13_cts: qup-uart13-cts-state {
5466 qup_uart13_rts: qup-uart13-rts-state {
5471 qup_uart13_tx: qup-uart13-tx-state {
5476 qup_uart13_rx: qup-uart13-rx-state {
5481 qup_uart14_cts: qup-uart14-cts-state {
5486 qup_uart14_rts: qup-uart14-rts-state {
5491 qup_uart14_tx: qup-uart14-tx-state {
5496 qup_uart14_rx: qup-uart14-rx-state {
5501 qup_uart15_cts: qup-uart15-cts-state {
5506 qup_uart15_rts: qup-uart15-rts-state {
5511 qup_uart15_tx: qup-uart15-tx-state {
5516 qup_uart15_rx: qup-uart15-rx-state {
5521 sdc1_clk: sdc1-clk-state {
5525 sdc1_cmd: sdc1-cmd-state {
5529 sdc1_data: sdc1-data-state {
5533 sdc1_rclk: sdc1-rclk-state {
5537 sdc1_clk_sleep: sdc1-clk-sleep-state {
5539 drive-strength = <2>;
5540 bias-bus-hold;
5543 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5545 drive-strength = <2>;
5546 bias-bus-hold;
5549 sdc1_data_sleep: sdc1-data-sleep-state {
5551 drive-strength = <2>;
5552 bias-bus-hold;
5555 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5557 drive-strength = <2>;
5558 bias-bus-hold;
5561 sdc2_clk: sdc2-clk-state {
5565 sdc2_cmd: sdc2-cmd-state {
5569 sdc2_data: sdc2-data-state {
5573 sdc2_clk_sleep: sdc2-clk-sleep-state {
5575 drive-strength = <2>;
5576 bias-bus-hold;
5579 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5581 drive-strength = <2>;
5582 bias-bus-hold;
5585 sdc2_data_sleep: sdc2-data-sleep-state {
5587 drive-strength = <2>;
5588 bias-bus-hold;
5593 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5596 #address-cells = <1>;
5597 #size-cells = <1>;
5601 pil-reloc@594c {
5602 compatible = "qcom,pil-reloc-info";
5608 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5610 #iommu-cells = <2>;
5611 #global-interrupts = <1>;
5612 dma-coherent;
5696 intc: interrupt-controller@17a00000 {
5697 compatible = "arm,gic-v3";
5701 #interrupt-cells = <3>;
5702 interrupt-controller;
5703 #address-cells = <2>;
5704 #size-cells = <2>;
5707 msi-controller@17a40000 {
5708 compatible = "arm,gic-v3-its";
5710 msi-controller;
5711 #msi-cells = <1>;
5717 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5725 #address-cells = <1>;
5726 #size-cells = <1>;
5728 compatible = "arm,armv7-timer-mem";
5732 frame-number = <0>;
5740 frame-number = <1>;
5747 frame-number = <2>;
5754 frame-number = <3>;
5761 frame-number = <4>;
5768 frame-number = <5>;
5775 frame-number = <6>;
5783 compatible = "qcom,rpmh-rsc";
5787 reg-names = "drv-0", "drv-1", "drv-2";
5791 qcom,tcs-offset = <0xd00>;
5792 qcom,drv-id = <2>;
5793 qcom,tcs-config = <ACTIVE_TCS 2>,
5797 power-domains = <&CLUSTER_PD>;
5799 apps_bcm_voter: bcm-voter {
5800 compatible = "qcom,bcm-voter";
5803 rpmhpd: power-controller {
5804 compatible = "qcom,sc7280-rpmhpd";
5805 #power-domain-cells = <1>;
5806 operating-points-v2 = <&rpmhpd_opp_table>;
5808 rpmhpd_opp_table: opp-table {
5809 compatible = "operating-points-v2";
5812 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5816 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5820 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5824 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5828 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5832 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5836 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5840 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5844 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5849 rpmhcc: clock-controller {
5850 compatible = "qcom,sc7280-rpmh-clk";
5852 clock-names = "xo";
5853 #clock-cells = <1>;
5858 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
5861 clock-names = "xo", "alternate";
5862 #interconnect-cells = <1>;
5866 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
5874 interrupt-names = "dcvsh-irq-0",
5875 "dcvsh-irq-1",
5876 "dcvsh-irq-2";
5879 clock-names = "xo", "alternate";
5880 #freq-domain-cells = <1>;
5881 #clock-cells = <1>;
5885 thermal_zones: thermal-zones {
5886 cpu0-thermal {
5887 polling-delay-passive = <250>;
5888 polling-delay = <0>;
5890 thermal-sensors = <&tsens0 1>;
5893 cpu0_alert0: trip-point0 {
5899 cpu0_alert1: trip-point1 {
5905 cpu0_crit: cpu-crit {
5912 cooling-maps {
5915 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5922 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5930 cpu1-thermal {
5931 polling-delay-passive = <250>;
5932 polling-delay = <0>;
5934 thermal-sensors = <&tsens0 2>;
5937 cpu1_alert0: trip-point0 {
5943 cpu1_alert1: trip-point1 {
5949 cpu1_crit: cpu-crit {
5956 cooling-maps {
5959 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5966 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5974 cpu2-thermal {
5975 polling-delay-passive = <250>;
5976 polling-delay = <0>;
5978 thermal-sensors = <&tsens0 3>;
5981 cpu2_alert0: trip-point0 {
5987 cpu2_alert1: trip-point1 {
5993 cpu2_crit: cpu-crit {
6000 cooling-maps {
6003 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6010 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6018 cpu3-thermal {
6019 polling-delay-passive = <250>;
6020 polling-delay = <0>;
6022 thermal-sensors = <&tsens0 4>;
6025 cpu3_alert0: trip-point0 {
6031 cpu3_alert1: trip-point1 {
6037 cpu3_crit: cpu-crit {
6044 cooling-maps {
6047 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6054 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6062 cpu4-thermal {
6063 polling-delay-passive = <250>;
6064 polling-delay = <0>;
6066 thermal-sensors = <&tsens0 7>;
6069 cpu4_alert0: trip-point0 {
6075 cpu4_alert1: trip-point1 {
6081 cpu4_crit: cpu-crit {
6088 cooling-maps {
6091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6098 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6106 cpu5-thermal {
6107 polling-delay-passive = <250>;
6108 polling-delay = <0>;
6110 thermal-sensors = <&tsens0 8>;
6113 cpu5_alert0: trip-point0 {
6119 cpu5_alert1: trip-point1 {
6125 cpu5_crit: cpu-crit {
6132 cooling-maps {
6135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6142 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6150 cpu6-thermal {
6151 polling-delay-passive = <250>;
6152 polling-delay = <0>;
6154 thermal-sensors = <&tsens0 9>;
6157 cpu6_alert0: trip-point0 {
6163 cpu6_alert1: trip-point1 {
6169 cpu6_crit: cpu-crit {
6176 cooling-maps {
6179 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6186 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6194 cpu7-thermal {
6195 polling-delay-passive = <250>;
6196 polling-delay = <0>;
6198 thermal-sensors = <&tsens0 10>;
6201 cpu7_alert0: trip-point0 {
6207 cpu7_alert1: trip-point1 {
6213 cpu7_crit: cpu-crit {
6220 cooling-maps {
6223 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6230 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6238 cpu8-thermal {
6239 polling-delay-passive = <250>;
6240 polling-delay = <0>;
6242 thermal-sensors = <&tsens0 11>;
6245 cpu8_alert0: trip-point0 {
6251 cpu8_alert1: trip-point1 {
6257 cpu8_crit: cpu-crit {
6264 cooling-maps {
6267 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6274 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6282 cpu9-thermal {
6283 polling-delay-passive = <250>;
6284 polling-delay = <0>;
6286 thermal-sensors = <&tsens0 12>;
6289 cpu9_alert0: trip-point0 {
6295 cpu9_alert1: trip-point1 {
6301 cpu9_crit: cpu-crit {
6308 cooling-maps {
6311 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6318 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6326 cpu10-thermal {
6327 polling-delay-passive = <250>;
6328 polling-delay = <0>;
6330 thermal-sensors = <&tsens0 13>;
6333 cpu10_alert0: trip-point0 {
6339 cpu10_alert1: trip-point1 {
6345 cpu10_crit: cpu-crit {
6352 cooling-maps {
6355 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6362 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6370 cpu11-thermal {
6371 polling-delay-passive = <250>;
6372 polling-delay = <0>;
6374 thermal-sensors = <&tsens0 14>;
6377 cpu11_alert0: trip-point0 {
6383 cpu11_alert1: trip-point1 {
6389 cpu11_crit: cpu-crit {
6396 cooling-maps {
6399 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6406 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6414 aoss0-thermal {
6415 polling-delay-passive = <0>;
6416 polling-delay = <0>;
6418 thermal-sensors = <&tsens0 0>;
6421 aoss0_alert0: trip-point0 {
6427 aoss0_crit: aoss0-crit {
6435 aoss1-thermal {
6436 polling-delay-passive = <0>;
6437 polling-delay = <0>;
6439 thermal-sensors = <&tsens1 0>;
6442 aoss1_alert0: trip-point0 {
6448 aoss1_crit: aoss1-crit {
6456 cpuss0-thermal {
6457 polling-delay-passive = <0>;
6458 polling-delay = <0>;
6460 thermal-sensors = <&tsens0 5>;
6463 cpuss0_alert0: trip-point0 {
6468 cpuss0_crit: cluster0-crit {
6476 cpuss1-thermal {
6477 polling-delay-passive = <0>;
6478 polling-delay = <0>;
6480 thermal-sensors = <&tsens0 6>;
6483 cpuss1_alert0: trip-point0 {
6488 cpuss1_crit: cluster0-crit {
6496 gpuss0-thermal {
6497 polling-delay-passive = <100>;
6498 polling-delay = <0>;
6500 thermal-sensors = <&tsens1 1>;
6503 gpuss0_alert0: trip-point0 {
6509 gpuss0_crit: gpuss0-crit {
6516 cooling-maps {
6519 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 gpuss1-thermal {
6525 polling-delay-passive = <100>;
6526 polling-delay = <0>;
6528 thermal-sensors = <&tsens1 2>;
6531 gpuss1_alert0: trip-point0 {
6537 gpuss1_crit: gpuss1-crit {
6544 cooling-maps {
6547 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6552 nspss0-thermal {
6553 polling-delay-passive = <0>;
6554 polling-delay = <0>;
6556 thermal-sensors = <&tsens1 3>;
6559 nspss0_alert0: trip-point0 {
6565 nspss0_crit: nspss0-crit {
6573 nspss1-thermal {
6574 polling-delay-passive = <0>;
6575 polling-delay = <0>;
6577 thermal-sensors = <&tsens1 4>;
6580 nspss1_alert0: trip-point0 {
6586 nspss1_crit: nspss1-crit {
6594 video-thermal {
6595 polling-delay-passive = <0>;
6596 polling-delay = <0>;
6598 thermal-sensors = <&tsens1 5>;
6601 video_alert0: trip-point0 {
6607 video_crit: video-crit {
6615 ddr-thermal {
6616 polling-delay-passive = <0>;
6617 polling-delay = <0>;
6619 thermal-sensors = <&tsens1 6>;
6622 ddr_alert0: trip-point0 {
6628 ddr_crit: ddr-crit {
6636 mdmss0-thermal {
6637 polling-delay-passive = <0>;
6638 polling-delay = <0>;
6640 thermal-sensors = <&tsens1 7>;
6643 mdmss0_alert0: trip-point0 {
6649 mdmss0_crit: mdmss0-crit {
6657 mdmss1-thermal {
6658 polling-delay-passive = <0>;
6659 polling-delay = <0>;
6661 thermal-sensors = <&tsens1 8>;
6664 mdmss1_alert0: trip-point0 {
6670 mdmss1_crit: mdmss1-crit {
6678 mdmss2-thermal {
6679 polling-delay-passive = <0>;
6680 polling-delay = <0>;
6682 thermal-sensors = <&tsens1 9>;
6685 mdmss2_alert0: trip-point0 {
6691 mdmss2_crit: mdmss2-crit {
6699 mdmss3-thermal {
6700 polling-delay-passive = <0>;
6701 polling-delay = <0>;
6703 thermal-sensors = <&tsens1 10>;
6706 mdmss3_alert0: trip-point0 {
6712 mdmss3_crit: mdmss3-crit {
6720 camera0-thermal {
6721 polling-delay-passive = <0>;
6722 polling-delay = <0>;
6724 thermal-sensors = <&tsens1 11>;
6727 camera0_alert0: trip-point0 {
6733 camera0_crit: camera0-crit {
6743 compatible = "arm,armv8-timer";