Lines Matching +full:1 +full:a98000
186 qcom,client-id = <1>;
292 clocks = <&cpufreq_hw 1>;
300 qcom,freq-domain = <&cpufreq_hw 1>;
314 clocks = <&cpufreq_hw 1>;
322 qcom,freq-domain = <&cpufreq_hw 1>;
336 clocks = <&cpufreq_hw 1>;
344 qcom,freq-domain = <&cpufreq_hw 1>;
425 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
435 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
445 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
712 #qcom,smem-state-cells = <1>;
736 #qcom,smem-state-cells = <1>;
756 qcom,remote-pid = <1>;
760 #qcom,smem-state-cells = <1>;
771 #qcom,smem-state-cells = <1>;
795 #qcom,smem-state-cells = <1>;
806 #qcom,smem-state-cells = <1>;
935 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
942 #clock-cells = <1>;
943 #reset-cells = <1>;
944 #power-domain-cells = <1>;
966 #address-cells = <1>;
967 #size-cells = <1>;
969 gpu_speed_bin: gpu_speed_bin@1e9 {
979 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1008 mmc-ddr-1_8v;
1009 mmc-hs200-1_8v;
1010 mmc-hs400-1_8v;
1076 #address-cells = <1>;
1086 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1099 #address-cells = <1>;
1107 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1136 #address-cells = <1>;
1145 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1146 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1159 #address-cells = <1>;
1166 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1167 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1196 #address-cells = <1>;
1206 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1219 #address-cells = <1>;
1227 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1256 #address-cells = <1>;
1266 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1279 #address-cells = <1>;
1287 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1316 #address-cells = <1>;
1326 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1339 #address-cells = <1>;
1347 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1376 #address-cells = <1>;
1386 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1399 #address-cells = <1>;
1407 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1436 #address-cells = <1>;
1446 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1459 #address-cells = <1>;
1467 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1496 #address-cells = <1>;
1506 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1519 #address-cells = <1>;
1527 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1591 #address-cells = <1>;
1601 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1614 #address-cells = <1>;
1622 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1651 #address-cells = <1>;
1660 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1661 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1674 #address-cells = <1>;
1681 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1682 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1711 #address-cells = <1>;
1721 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1734 #address-cells = <1>;
1742 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1771 #address-cells = <1>;
1781 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1794 #address-cells = <1>;
1802 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1831 #address-cells = <1>;
1841 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1854 #address-cells = <1>;
1862 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1891 #address-cells = <1>;
1901 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1914 #address-cells = <1>;
1922 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1943 i2c14: i2c@a98000 {
1951 #address-cells = <1>;
1961 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1966 spi14: spi@a98000 {
1974 #address-cells = <1>;
1982 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1987 uart14: serial@a98000 {
2011 #address-cells = <1>;
2021 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2034 #address-cells = <1>;
2042 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2161 pcie1: pcie@1c08000 {
2171 linux,pci-domain = <1>;
2183 #interrupt-cells = <1>;
2185 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2240 pcie1_phy: phy@1c0e000 {
2268 ufs_mem_hc: ufs@1d84000 {
2276 #reset-cells = <1>;
2320 ufs_mem_phy: phy@1d87000 {
2333 #clock-cells = <1>;
2339 cryptobam: dma-controller@1dc4000 {
2343 #dma-cells = <1>;
2350 crypto: crypto@1dfa000 {
2361 ipa: ipa@1e40000 {
2376 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2393 <&ipa_smp2p_out 1>;
2400 tcsr_mutex: hwlock@1f40000 {
2403 #hwlock-cells = <1>;
2406 tcsr_1: syscon@1f60000 {
2411 tcsr_2: syscon@1fc0000 {
2423 #clock-cells = <1>;
2444 #sound-dai-cells = <1>;
2473 #sound-dai-cells = <1>;
2497 #sound-dai-cells = <1>;
2527 #sound-dai-cells = <1>;
2542 #clock-cells = <1>;
2543 #power-domain-cells = <1>;
2544 #reset-cells = <1>;
2562 #sound-dai-cells = <1>;
2574 #clock-cells = <1>;
2575 #power-domain-cells = <1>;
2585 #clock-cells = <1>;
2586 #power-domain-cells = <1>;
2635 #sound-dai-cells = <1>;
2636 #address-cells = <1>;
2656 #clock-cells = <1>;
2657 #power-domain-cells = <1>;
2727 <&adreno_smmu 1 0x400>;
2766 opp-550000000-1 {
2859 #clock-cells = <1>;
2860 #reset-cells = <1>;
2861 #power-domain-cells = <1>;
2914 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2944 qcom,remote-pid = <1>;
2982 #address-cells = <1>;
3010 #address-cells = <1>;
3038 #address-cells = <1>;
3048 port@1 {
3049 reg = <1>;
3115 #address-cells = <1>;
3352 #address-cells = <1>;
3362 port@1 {
3363 reg = <1>;
3441 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3531 #clock-cells = <1>;
3532 #phy-cells = <1>;
3535 #address-cells = <1>;
3545 port@1 {
3546 reg = <1>;
3625 #address-cells = <1>;
3645 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3684 #address-cells = <1>;
3714 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3766 opp-1 {
3805 opp-1 {
3857 #address-cells = <1>;
3882 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3922 #address-cells = <1>;
3925 compute-cb@1 {
3927 reg = <1>;
4146 #clock-cells = <1>;
4147 #reset-cells = <1>;
4148 #power-domain-cells = <1>;
4168 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4171 #address-cells = <1>;
4179 #address-cells = <1>;
4183 cci0_i2c1: i2c-bus@1 {
4184 reg = <1>;
4186 #address-cells = <1>;
4208 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4211 #address-cells = <1>;
4219 #address-cells = <1>;
4223 cci1_i2c1: i2c-bus@1 {
4224 reg = <1>;
4226 #address-cells = <1>;
4238 #clock-cells = <1>;
4239 #reset-cells = <1>;
4240 #power-domain-cells = <1>;
4249 <&mdss_dsi_phy 1>,
4253 <&mdss_edp_phy 1>;
4262 #clock-cells = <1>;
4263 #reset-cells = <1>;
4264 #power-domain-cells = <1>;
4283 #interrupt-cells = <1>;
4329 #address-cells = <1>;
4339 port@1 {
4340 reg = <1>;
4402 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4409 #address-cells = <1>;
4415 #address-cells = <1>;
4425 port@1 {
4426 reg = <1>;
4461 #clock-cells = <1>;
4496 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4507 #address-cells = <1>;
4517 port@1 {
4518 reg = <1>;
4561 #clock-cells = <1>;
4604 #address-cells = <1>;
4614 port@1 {
4615 reg = <1>;
4649 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4651 <64 434 2>, <66 438 3>, <69 86 1>,
4652 <70 520 54>, <124 609 31>, <155 63 1>,
4662 #reset-cells = <1>;
4674 #thermal-sensor-cells = <1>;
4685 #thermal-sensor-cells = <1>;
4691 #reset-cells = <1>;
4720 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5596 #address-cells = <1>;
5597 #size-cells = <1>;
5611 #global-interrupts = <1>;
5711 #msi-cells = <1>;
5725 #address-cells = <1>;
5726 #size-cells = <1>;
5740 frame-number = <1>;
5787 reg-names = "drv-0", "drv-1", "drv-2";
5796 <CONTROL_TCS 1>;
5805 #power-domain-cells = <1>;
5853 #clock-cells = <1>;
5862 #interconnect-cells = <1>;
5875 "dcvsh-irq-1",
5880 #freq-domain-cells = <1>;
5881 #clock-cells = <1>;
5890 thermal-sensors = <&tsens0 1>;
6500 thermal-sensors = <&tsens1 1>;