Lines Matching +full:0 +full:x0aaf0000
80 #clock-cells = <0>;
86 #clock-cells = <0>;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
101 reg = <0x0 0x80000000 0x0 0x600000>;
106 reg = <0x0 0x80600000 0x0 0x200000>;
111 reg = <0x0 0x80800000 0x0 0x60000>;
116 reg = <0x0 0x80860000 0x0 0x20000>;
122 reg = <0x0 0x80884000 0x0 0x10000>;
127 reg = <0x0 0x808ff000 0x0 0x1000>;
132 reg = <0x0 0x80900000 0x0 0x200000>;
138 reg = <0x0 0x80b00000 0x0 0x100000>;
142 reg = <0x0 0x80c00000 0x0 0xc00000>;
147 reg = <0x0 0x86700000 0x0 0x2800000>;
152 reg = <0x0 0x8b200000 0x0 0x500000>;
157 reg = <0x0 0x88f00000 0x0 0x1e00000>;
162 reg = <0 0x8b700000 0 0x10000>;
167 reg = <0 0x8b71a000 0 0x2000>;
172 reg = <0x0 0x8b800000 0x0 0xf600000>;
177 reg = <0x0 0x9ae00000 0x0 0x1900000>;
183 reg = <0x0 0x9c900000 0x0 0x280000>;
193 #size-cells = <0>;
195 CPU0: cpu@0 {
198 reg = <0x0 0x0>;
199 clocks = <&cpufreq_hw 0>;
207 qcom,freq-domain = <&cpufreq_hw 0>;
225 reg = <0x0 0x100>;
226 clocks = <&cpufreq_hw 0>;
234 qcom,freq-domain = <&cpufreq_hw 0>;
247 reg = <0x0 0x200>;
248 clocks = <&cpufreq_hw 0>;
256 qcom,freq-domain = <&cpufreq_hw 0>;
269 reg = <0x0 0x300>;
270 clocks = <&cpufreq_hw 0>;
278 qcom,freq-domain = <&cpufreq_hw 0>;
291 reg = <0x0 0x400>;
313 reg = <0x0 0x500>;
335 reg = <0x0 0x600>;
357 reg = <0x0 0x700>;
415 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
418 arm,psci-suspend-param = <0x40000003>;
425 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
428 arm,psci-suspend-param = <0x40000004>;
435 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
438 arm,psci-suspend-param = <0x40000003>;
448 arm,psci-suspend-param = <0x40000004>;
457 CLUSTER_SLEEP_0: cluster-sleep-0 {
460 arm,psci-suspend-param = <0x40003444>;
677 reg = <0 0x80000000 0 0>;
707 qcom,local-pid = <0>;
731 qcom,local-pid = <0>;
755 qcom,local-pid = <0>;
790 qcom,local-pid = <0>;
826 #power-domain-cells = <0>;
832 #power-domain-cells = <0>;
838 #power-domain-cells = <0>;
844 #power-domain-cells = <0>;
850 #power-domain-cells = <0>;
856 #power-domain-cells = <0>;
862 #power-domain-cells = <0>;
868 #power-domain-cells = <0>;
874 #power-domain-cells = <0>;
922 soc: soc@0 {
925 ranges = <0 0 0 0 0x10 0>;
926 dma-ranges = <0 0 0 0 0x10 0>;
931 reg = <0 0x00100000 0 0x1f0000>;
934 <0>, <&pcie1_phy>,
935 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
950 reg = <0 0x00408000 0 0x1000>;
959 reg = <0 0x00784000 0 0xa20>,
960 <0 0x00780000 0 0xa20>,
961 <0 0x00782000 0 0x120>,
962 <0 0x00786000 0 0x1fff>;
970 reg = <0x1e9 0x2>;
978 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
982 reg = <0 0x007c4000 0 0x1000>,
983 <0 0x007c5000 0 0x1000>;
986 iommus = <&apps_smmu 0xc0 0x0>;
995 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
996 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
1005 qcom,dll-config = <0x0007642c>;
1006 qcom,ddr-config = <0x80040868>;
1022 opp-avg-kBps = <100000 0>;
1029 opp-avg-kBps = <390000 0>;
1037 reg = <0 0x00900000 0 0x60000>;
1051 dma-channel-mask = <0x7f>;
1052 iommus = <&apps_smmu 0x0136 0x0>;
1058 reg = <0 0x009c0000 0 0x2000>;
1065 iommus = <&apps_smmu 0x123 0x0>;
1070 reg = <0 0x00980000 0 0x4000>;
1074 pinctrl-0 = <&qup_i2c0_data_clk>;
1077 #size-cells = <0>;
1078 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1079 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1080 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1085 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1086 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1093 reg = <0 0x00980000 0 0x4000>;
1097 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1100 #size-cells = <0>;
1103 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1104 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1106 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1107 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1114 reg = <0 0x00980000 0 0x4000>;
1118 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1130 reg = <0 0x00984000 0 0x4000>;
1134 pinctrl-0 = <&qup_i2c1_data_clk>;
1137 #size-cells = <0>;
1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1140 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1145 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1153 reg = <0 0x00984000 0 0x4000>;
1157 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1160 #size-cells = <0>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1166 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1174 reg = <0 0x00984000 0 0x4000>;
1178 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1190 reg = <0 0x00988000 0 0x4000>;
1194 pinctrl-0 = <&qup_i2c2_data_clk>;
1197 #size-cells = <0>;
1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1200 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1205 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1213 reg = <0 0x00988000 0 0x4000>;
1217 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1220 #size-cells = <0>;
1223 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1224 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1226 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1234 reg = <0 0x00988000 0 0x4000>;
1238 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1250 reg = <0 0x0098c000 0 0x4000>;
1254 pinctrl-0 = <&qup_i2c3_data_clk>;
1257 #size-cells = <0>;
1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1260 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1265 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 reg = <0 0x0098c000 0 0x4000>;
1277 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1280 #size-cells = <0>;
1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1284 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1286 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1294 reg = <0 0x0098c000 0 0x4000>;
1298 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1310 reg = <0 0x00990000 0 0x4000>;
1314 pinctrl-0 = <&qup_i2c4_data_clk>;
1317 #size-cells = <0>;
1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1320 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1325 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1333 reg = <0 0x00990000 0 0x4000>;
1337 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1340 #size-cells = <0>;
1343 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1344 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1346 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1354 reg = <0 0x00990000 0 0x4000>;
1358 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1370 reg = <0 0x00994000 0 0x4000>;
1374 pinctrl-0 = <&qup_i2c5_data_clk>;
1377 #size-cells = <0>;
1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1379 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1385 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1393 reg = <0 0x00994000 0 0x4000>;
1397 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1400 #size-cells = <0>;
1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1404 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1406 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1414 reg = <0 0x00994000 0 0x4000>;
1418 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1422 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1430 reg = <0 0x00998000 0 0x4000>;
1434 pinctrl-0 = <&qup_i2c6_data_clk>;
1437 #size-cells = <0>;
1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1439 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1440 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1445 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1453 reg = <0 0x00998000 0 0x4000>;
1457 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1460 #size-cells = <0>;
1463 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1464 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1466 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1474 reg = <0 0x00998000 0 0x4000>;
1478 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1482 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1483 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1490 reg = <0 0x0099c000 0 0x4000>;
1494 pinctrl-0 = <&qup_i2c7_data_clk>;
1497 #size-cells = <0>;
1498 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1499 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1500 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1505 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1513 reg = <0 0x0099c000 0 0x4000>;
1517 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1520 #size-cells = <0>;
1523 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1524 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1526 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1534 reg = <0 0x0099c000 0 0x4000>;
1538 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1542 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1543 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1552 reg = <0 0x00a00000 0 0x60000>;
1566 dma-channel-mask = <0x1e>;
1567 iommus = <&apps_smmu 0x56 0x0>;
1573 reg = <0 0x00ac0000 0 0x2000>;
1580 iommus = <&apps_smmu 0x43 0x0>;
1585 reg = <0 0x00a80000 0 0x4000>;
1589 pinctrl-0 = <&qup_i2c8_data_clk>;
1592 #size-cells = <0>;
1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1594 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1595 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1600 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1601 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1608 reg = <0 0x00a80000 0 0x4000>;
1612 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1615 #size-cells = <0>;
1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1619 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1621 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1622 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1629 reg = <0 0x00a80000 0 0x4000>;
1633 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1645 reg = <0 0x00a84000 0 0x4000>;
1649 pinctrl-0 = <&qup_i2c9_data_clk>;
1652 #size-cells = <0>;
1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1654 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1655 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1660 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1668 reg = <0 0x00a84000 0 0x4000>;
1672 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1675 #size-cells = <0>;
1678 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1679 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1681 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1689 reg = <0 0x00a84000 0 0x4000>;
1693 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1705 reg = <0 0x00a88000 0 0x4000>;
1709 pinctrl-0 = <&qup_i2c10_data_clk>;
1712 #size-cells = <0>;
1713 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1715 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1720 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1728 reg = <0 0x00a88000 0 0x4000>;
1732 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1735 #size-cells = <0>;
1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1741 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1749 reg = <0 0x00a88000 0 0x4000>;
1753 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1758 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1765 reg = <0 0x00a8c000 0 0x4000>;
1769 pinctrl-0 = <&qup_i2c11_data_clk>;
1772 #size-cells = <0>;
1773 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1774 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1775 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1780 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1788 reg = <0 0x00a8c000 0 0x4000>;
1792 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1795 #size-cells = <0>;
1798 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1799 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1801 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1809 reg = <0 0x00a8c000 0 0x4000>;
1813 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1817 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1825 reg = <0 0x00a90000 0 0x4000>;
1829 pinctrl-0 = <&qup_i2c12_data_clk>;
1832 #size-cells = <0>;
1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1835 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1840 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1848 reg = <0 0x00a90000 0 0x4000>;
1852 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1855 #size-cells = <0>;
1858 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1859 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1861 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1869 reg = <0 0x00a90000 0 0x4000>;
1873 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1877 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1878 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1885 reg = <0 0x00a94000 0 0x4000>;
1889 pinctrl-0 = <&qup_i2c13_data_clk>;
1892 #size-cells = <0>;
1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1895 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1900 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1908 reg = <0 0x00a94000 0 0x4000>;
1912 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1915 #size-cells = <0>;
1918 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1919 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1921 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1929 reg = <0 0x00a94000 0 0x4000>;
1933 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1937 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1945 reg = <0 0x00a98000 0 0x4000>;
1949 pinctrl-0 = <&qup_i2c14_data_clk>;
1952 #size-cells = <0>;
1953 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1955 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1960 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1968 reg = <0 0x00a98000 0 0x4000>;
1972 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1975 #size-cells = <0>;
1978 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1979 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1981 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1989 reg = <0 0x00a98000 0 0x4000>;
1993 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1997 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1998 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2005 reg = <0 0x00a9c000 0 0x4000>;
2009 pinctrl-0 = <&qup_i2c15_data_clk>;
2012 #size-cells = <0>;
2013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
2015 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
2020 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2028 reg = <0 0x00a9c000 0 0x4000>;
2032 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2035 #size-cells = <0>;
2038 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2039 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2041 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2049 reg = <0 0x00a9c000 0 0x4000>;
2053 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2057 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2066 reg = <0 0x010d3000 0 0x1000>;
2070 reg = <0 0x01500000 0 0x1000>;
2077 reg = <0 0x01502000 0 0x1000>;
2084 reg = <0 0x01580000 0 0x4>;
2091 reg = <0 0x01680000 0 0x15480>;
2099 reg = <0 0x016e0000 0 0x1c080>;
2105 reg = <0 0x01700000 0 0x2b080>;
2112 reg = <0 0x01740000 0 0x1e080>;
2120 reg = <0 0x17a10040 0 0x0>;
2121 iommus = <&apps_smmu 0x1c00 0x1>;
2157 qcom,smem-states = <&wlan_smp2p_out 0>;
2163 reg = <0 0x01c08000 0 0x3000>,
2164 <0 0x40000000 0 0xf1d>,
2165 <0 0x40000f20 0 0xa8>,
2166 <0 0x40001000 0 0x1000>,
2167 <0 0x40100000 0 0x100000>;
2172 bus-range = <0x00 0xff>;
2178 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2179 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2184 interrupt-map-mask = <0 0 0 0x7>;
2185 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2186 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2187 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2188 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2230 pinctrl-0 = <&pcie1_clkreq_n>;
2234 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2235 <0x100 &apps_smmu 0x1c81 0x1>;
2242 reg = <0 0x01c0e000 0 0x1000>;
2255 #clock-cells = <0>;
2257 #phy-cells = <0>;
2271 reg = <0x0 0x01d84000 0x0 0x3000>;
2283 iommus = <&apps_smmu 0x80 0x0>;
2310 <0 0>,
2311 <0 0>,
2313 <0 0>,
2314 <0 0>,
2315 <0 0>,
2316 <0 0>;
2322 reg = <0x0 0x01d87000 0x0 0xe00>;
2330 resets = <&ufs_mem_hc 0>;
2334 #phy-cells = <0>;
2341 reg = <0x0 0x01dc4000 0x0 0x28000>;
2344 iommus = <&apps_smmu 0x4e4 0x0011>,
2345 <&apps_smmu 0x4e6 0x0011>;
2346 qcom,ee = <0>;
2352 reg = <0x0 0x01dfa000 0x0 0x6000>;
2355 iommus = <&apps_smmu 0x4e4 0x0011>,
2356 <&apps_smmu 0x4e4 0x0011>;
2357 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
2364 iommus = <&apps_smmu 0x480 0x0>,
2365 <&apps_smmu 0x482 0x0>;
2366 reg = <0 0x01e40000 0 0x8000>,
2367 <0 0x01e50000 0 0x4ad0>,
2368 <0 0x01e04000 0 0x23000>;
2375 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2385 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2386 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2392 qcom,smem-states = <&ipa_smp2p_out 0>,
2402 reg = <0 0x01f40000 0 0x20000>;
2408 reg = <0 0x01f60000 0 0x20000>;
2413 reg = <0 0x01fc0000 0 0x30000>;
2418 reg = <0 0x03000000 0 0x40>,
2419 <0 0x03c04000 0 0x4>;
2429 reg = <0 0x03200000 0 0x1000>;
2432 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2443 #clock-cells = <0>;
2451 reg = <0 0x03210000 0 0x2000>;
2457 qcom,din-ports = <0>;
2463 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2464 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2465 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2466 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2467 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2468 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2469 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2470 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2471 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2475 #size-cells = <0>;
2482 reg = <0 0x03220000 0 0x1000>;
2485 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2496 #clock-cells = <0>;
2504 reg = <0 0x03230000 0 0x2000>;
2512 qcom,dout-ports = <0>;
2517 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2518 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2519 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2522 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2523 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2525 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2529 #size-cells = <0>;
2536 reg = <0 0x03300000 0 0x30000>,
2537 <0 0x032a9000 0 0x1000>;
2549 reg = <0 0x03370000 0 0x1000>;
2552 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2561 #clock-cells = <0>;
2569 reg = <0 0x03380000 0 0x30000>;
2581 reg = <0 0x03900000 0 0x50000>;
2593 reg = <0 0x03987000 0 0x68000>,
2594 <0 0x03b00000 0 0x29000>,
2595 <0 0x03260000 0 0xc000>,
2596 <0 0x03280000 0 0x29000>,
2597 <0 0x03340000 0 0x29000>,
2598 <0 0x0336c000 0 0x3000>;
2606 iommus = <&apps_smmu 0x1820 0>,
2607 <&apps_smmu 0x1821 0>,
2608 <&apps_smmu 0x1832 0>;
2637 #size-cells = <0>;
2653 reg = <0 0x03c00000 0 0x28>;
2662 reg = <0 0x03c40000 0 0xf080>;
2670 reg = <0 0x033c0000 0x0 0x20000>,
2671 <0 0x03550000 0x0 0x10000>;
2674 gpio-ranges = <&lpass_tlmm 0 0 15>;
2719 reg = <0 0x03d00000 0 0x40000>,
2720 <0 0x03d9e000 0 0x1000>,
2721 <0 0x03d61000 0 0x800>;
2726 iommus = <&adreno_smmu 0 0x400>,
2727 <&adreno_smmu 1 0x400>;
2730 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2748 opp-supported-hw = <0x07>;
2755 opp-supported-hw = <0x07>;
2759 opp-550000000-0 {
2763 opp-supported-hw = <0x01>;
2770 opp-supported-hw = <0x06>;
2777 opp-supported-hw = <0x06>;
2784 opp-supported-hw = <0x06>;
2791 opp-supported-hw = <0x06>;
2798 opp-supported-hw = <0x02>;
2805 opp-supported-hw = <0x02>;
2812 reg = <0 0x03d6a000 0 0x34000>,
2813 <0 0x3de0000 0 0x10000>,
2814 <0 0x0b290000 0 0x10000>;
2837 iommus = <&adreno_smmu 5 0x400>;
2852 reg = <0 0x03d90000 0 0x9000>;
2866 reg = <0x0 0x0117f000 0x0 0x1000>,
2867 <0x0 0x01112000 0x0 0x6000>;
2873 reg = <0 0x03da0000 0 0x20000>;
2910 reg = <0 0x04080000 0 0x10000>;
2913 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2932 qcom,smem-states = <&modem_smp2p_out 0>;
2950 reg = <0 0x06002000 0 0x1000>,
2951 <0 0x16280000 0 0x180000>;
2968 reg = <0 0x06041000 0 0x1000>;
2983 #size-cells = <0>;
2996 reg = <0 0x06042000 0 0x1000>;
3011 #size-cells = <0>;
3024 reg = <0 0x06045000 0 0x1000>;
3039 #size-cells = <0>;
3041 port@0 {
3042 reg = <0>;
3059 reg = <0 0x06046000 0 0x1000>;
3083 reg = <0 0x06048000 0 0x1000>;
3084 iommus = <&apps_smmu 0x04c0 0>;
3101 reg = <0 0x06b04000 0 0x1000>;
3116 #size-cells = <0>;
3129 reg = <0 0x06b05000 0 0x1000>;
3153 reg = <0 0x06b06000 0 0x1000>;
3178 reg = <0 0x07040000 0 0x1000>;
3198 reg = <0 0x07140000 0 0x1000>;
3218 reg = <0 0x07240000 0 0x1000>;
3238 reg = <0 0x07340000 0 0x1000>;
3258 reg = <0 0x07440000 0 0x1000>;
3278 reg = <0 0x07540000 0 0x1000>;
3298 reg = <0 0x07640000 0 0x1000>;
3318 reg = <0 0x07740000 0 0x1000>;
3338 reg = <0 0x07800000 0 0x1000>;
3353 #size-cells = <0>;
3355 port@0 {
3356 reg = <0>;
3415 reg = <0 0x07810000 0 0x1000>;
3440 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3444 reg = <0 0x08804000 0 0x1000>;
3446 iommus = <&apps_smmu 0x100 0x0>;
3455 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3456 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3464 qcom,dll-config = <0x0007642c>;
3475 opp-avg-kBps = <100000 0>;
3482 opp-avg-kBps = <200000 0>;
3490 reg = <0 0x088e3000 0 0x400>;
3492 #phy-cells = <0>;
3503 reg = <0 0x088e4000 0 0x400>;
3505 #phy-cells = <0>;
3515 reg = <0 0x088e8000 0 0x3000>;
3536 #size-cells = <0>;
3538 port@0 {
3539 reg = <0>;
3563 reg = <0 0x08cf8800 0 0x400>;
3597 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3598 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3603 reg = <0 0x08c00000 0 0xe000>;
3605 iommus = <&apps_smmu 0xa0 0x0>;
3623 reg = <0 0x088dc000 0 0x1000>;
3624 iommus = <&apps_smmu 0x20 0x0>;
3626 #size-cells = <0>;
3631 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3632 &cnoc2 SLAVE_QSPI_0 0>;
3641 reg = <0 0x03700000 0 0x100>;
3644 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3663 qcom,smem-states = <&adsp_smp2p_out 0>;
3685 #size-cells = <0>;
3690 iommus = <&apps_smmu 0x1803 0x0>;
3696 iommus = <&apps_smmu 0x1804 0x0>;
3702 iommus = <&apps_smmu 0x1805 0x0>;
3710 reg = <0 0x08a00000 0 0x10000>;
3713 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3732 qcom,smem-states = <&wpss_smp2p_out 0>;
3752 reg = <0 0x09091000 0 0x1000>;
3763 opp-0 {
3792 reg = <0 0x090b6400 0 0x600>;
3802 opp-0 {
3827 reg = <0 0x090e0000 0 0x5080>;
3834 reg = <0 0x09100000 0 0xe2200>;
3842 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3843 <0 0x09600000 0 0x58000>;
3850 reg = <0 0x88e0000 0 0x2000>,
3851 <0 0x88e2000 0 0x1000>;
3858 #size-cells = <0>;
3860 port@0 {
3861 reg = <0>;
3870 reg = <0 0x0a0c0000 0 0x10000>;
3878 reg = <0 0x0a300000 0 0x10000>;
3881 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3896 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3902 qcom,smem-states = <&cdsp_smp2p_out 0>;
3923 #size-cells = <0>;
3928 iommus = <&apps_smmu 0x11a1 0x0420>,
3929 <&apps_smmu 0x1181 0x0420>;
3935 iommus = <&apps_smmu 0x11a2 0x0420>,
3936 <&apps_smmu 0x1182 0x0420>;
3942 iommus = <&apps_smmu 0x11a3 0x0420>,
3943 <&apps_smmu 0x1183 0x0420>;
3949 iommus = <&apps_smmu 0x11a4 0x0420>,
3950 <&apps_smmu 0x1184 0x0420>;
3956 iommus = <&apps_smmu 0x11a5 0x0420>,
3957 <&apps_smmu 0x1185 0x0420>;
3963 iommus = <&apps_smmu 0x11a6 0x0420>,
3964 <&apps_smmu 0x1186 0x0420>;
3970 iommus = <&apps_smmu 0x11a7 0x0420>,
3971 <&apps_smmu 0x1187 0x0420>;
3977 iommus = <&apps_smmu 0x11a8 0x0420>,
3978 <&apps_smmu 0x1188 0x0420>;
3986 iommus = <&apps_smmu 0x11ab 0x0420>,
3987 <&apps_smmu 0x118b 0x0420>;
3993 iommus = <&apps_smmu 0x11ac 0x0420>,
3994 <&apps_smmu 0x118c 0x0420>;
4000 iommus = <&apps_smmu 0x11ad 0x0420>,
4001 <&apps_smmu 0x118d 0x0420>;
4007 iommus = <&apps_smmu 0x11ae 0x0420>,
4008 <&apps_smmu 0x118e 0x0420>;
4016 reg = <0 0x0a6f8800 0 0x400>;
4052 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
4060 reg = <0 0x0a600000 0 0xe000>;
4062 iommus = <&apps_smmu 0xe0 0x0>;
4073 reg = <0 0x0aa00000 0 0xd0600>;
4090 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
4091 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
4094 iommus = <&apps_smmu 0x2180 0x20>,
4095 <&apps_smmu 0x2184 0x20>;
4107 iommus = <&apps_smmu 0x21a2 0x0>;
4142 reg = <0 0x0aaf0000 0 0x10000>;
4153 reg = <0 0x0ac4a000 0 0x1000>;
4167 pinctrl-0 = <&cci0_default &cci1_default>;
4172 #size-cells = <0>;
4176 cci0_i2c0: i2c-bus@0 {
4177 reg = <0>;
4180 #size-cells = <0>;
4187 #size-cells = <0>;
4193 reg = <0 0x0ac4b000 0 0x1000>;
4207 pinctrl-0 = <&cci2_default &cci3_default>;
4212 #size-cells = <0>;
4216 cci1_i2c0: i2c-bus@0 {
4217 reg = <0>;
4220 #size-cells = <0>;
4227 #size-cells = <0>;
4233 reg = <0 0x0ad00000 0 0x10000>;
4245 reg = <0 0x0af00000 0 0x20000>;
4248 <&mdss_dsi_phy 0>,
4252 <&mdss_edp_phy 0>,
4269 reg = <0 0x0ae00000 0 0x1000>;
4292 iommus = <&apps_smmu 0x900 0x402>;
4302 reg = <0 0x0ae01000 0 0x8f030>,
4303 <0 0x0aeb0000 0 0x2008>;
4326 interrupts = <0>;
4330 #size-cells = <0>;
4332 port@0 {
4333 reg = <0>;
4382 reg = <0 0x0ae94000 0 0x400>;
4402 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4410 #size-cells = <0>;
4416 #size-cells = <0>;
4418 port@0 {
4419 reg = <0>;
4454 reg = <0 0x0ae94400 0 0x200>,
4455 <0 0x0ae94600 0 0x280>,
4456 <0 0x0ae94900 0 0x280>;
4462 #phy-cells = <0>;
4474 pinctrl-0 = <&edp_hot_plug_det>;
4476 reg = <0 0x0aea0000 0 0x200>,
4477 <0 0x0aea0200 0 0x200>,
4478 <0 0x0aea0400 0 0xc00>,
4479 <0 0x0aea1000 0 0x400>;
4496 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4508 #size-cells = <0>;
4510 port@0 {
4511 reg = <0>;
4551 reg = <0 0x0aec2a00 0 0x19c>,
4552 <0 0x0aec2200 0 0xa0>,
4553 <0 0x0aec2600 0 0xa0>,
4554 <0 0x0aec2000 0 0x1c0>;
4562 #phy-cells = <0>;
4570 reg = <0 0x0ae90000 0 0x200>,
4571 <0 0x0ae90200 0 0x200>,
4572 <0 0x0ae90400 0 0xc00>,
4573 <0 0x0ae91000 0 0x400>,
4574 <0 0x0ae91400 0 0x400>;
4599 #sound-dai-cells = <0>;
4605 #size-cells = <0>;
4607 port@0 {
4608 reg = <0>;
4648 reg = <0 0x0b220000 0 0x30000>;
4649 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4661 reg = <0 0x0b5e0000 0 0x20000>;
4668 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4669 <0 0x0c222000 0 0x1ff>; /* SROT */
4679 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4680 <0 0x0c223000 0 0x1ff>; /* SROT */
4690 reg = <0 0x0c2a0000 0 0x31000>;
4696 reg = <0 0x0c300000 0 0x400>;
4703 #clock-cells = <0>;
4708 reg = <0 0x0c3f0000 0 0x400>;
4713 reg = <0 0x0c440000 0 0x1100>,
4714 <0 0x0c600000 0 0x2000000>,
4715 <0 0x0e600000 0 0x100000>,
4716 <0 0x0e700000 0 0xa0000>,
4717 <0 0x0c40a000 0 0x26000>;
4721 qcom,ee = <0>;
4722 qcom,channel = <0>;
4724 #size-cells = <0>;
4731 reg = <0 0x0f100000 0 0x300000>;
4737 gpio-ranges = <&tlmm 0 0 175>;
5594 reg = <0 0x146a5000 0 0x6000>;
5599 ranges = <0 0 0x146a5000 0x6000>;
5603 reg = <0x594c 0xc8>;
5609 reg = <0 0x15000000 0 0x100000>;
5698 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5699 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5709 reg = <0 0x17a40000 0 0x20000>;
5718 reg = <0 0x17c10000 0 0x1000>;
5720 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5727 ranges = <0 0 0 0x20000000>;
5729 reg = <0 0x17c20000 0 0x1000>;
5732 frame-number = <0>;
5735 reg = <0x17c21000 0x1000>,
5736 <0x17c22000 0x1000>;
5742 reg = <0x17c23000 0x1000>;
5749 reg = <0x17c25000 0x1000>;
5756 reg = <0x17c27000 0x1000>;
5763 reg = <0x17c29000 0x1000>;
5770 reg = <0x17c2b000 0x1000>;
5777 reg = <0x17c2d000 0x1000>;
5784 reg = <0 0x18200000 0 0x10000>,
5785 <0 0x18210000 0 0x10000>,
5786 <0 0x18220000 0 0x10000>;
5787 reg-names = "drv-0", "drv-1", "drv-2";
5791 qcom,tcs-offset = <0xd00>;
5859 reg = <0 0x18590000 0 0x1000>;
5867 reg = <0 0x18591000 0 0x1000>,
5868 <0 0x18592000 0 0x1000>,
5869 <0 0x18593000 0 0x1000>;
5874 interrupt-names = "dcvsh-irq-0",
5888 polling-delay = <0>;
5907 hysteresis = <0>;
5932 polling-delay = <0>;
5951 hysteresis = <0>;
5976 polling-delay = <0>;
5995 hysteresis = <0>;
6020 polling-delay = <0>;
6039 hysteresis = <0>;
6064 polling-delay = <0>;
6083 hysteresis = <0>;
6108 polling-delay = <0>;
6127 hysteresis = <0>;
6152 polling-delay = <0>;
6171 hysteresis = <0>;
6196 polling-delay = <0>;
6215 hysteresis = <0>;
6240 polling-delay = <0>;
6259 hysteresis = <0>;
6284 polling-delay = <0>;
6303 hysteresis = <0>;
6328 polling-delay = <0>;
6347 hysteresis = <0>;
6372 polling-delay = <0>;
6391 hysteresis = <0>;
6415 polling-delay-passive = <0>;
6416 polling-delay = <0>;
6418 thermal-sensors = <&tsens0 0>;
6429 hysteresis = <0>;
6436 polling-delay-passive = <0>;
6437 polling-delay = <0>;
6439 thermal-sensors = <&tsens1 0>;
6450 hysteresis = <0>;
6457 polling-delay-passive = <0>;
6458 polling-delay = <0>;
6470 hysteresis = <0>;
6477 polling-delay-passive = <0>;
6478 polling-delay = <0>;
6490 hysteresis = <0>;
6498 polling-delay = <0>;
6511 hysteresis = <0>;
6526 polling-delay = <0>;
6539 hysteresis = <0>;
6553 polling-delay-passive = <0>;
6554 polling-delay = <0>;
6567 hysteresis = <0>;
6574 polling-delay-passive = <0>;
6575 polling-delay = <0>;
6588 hysteresis = <0>;
6595 polling-delay-passive = <0>;
6596 polling-delay = <0>;
6609 hysteresis = <0>;
6616 polling-delay-passive = <0>;
6617 polling-delay = <0>;
6630 hysteresis = <0>;
6637 polling-delay-passive = <0>;
6638 polling-delay = <0>;
6651 hysteresis = <0>;
6658 polling-delay-passive = <0>;
6659 polling-delay = <0>;
6672 hysteresis = <0>;
6679 polling-delay-passive = <0>;
6680 polling-delay = <0>;
6693 hysteresis = <0>;
6700 polling-delay-passive = <0>;
6701 polling-delay = <0>;
6714 hysteresis = <0>;
6721 polling-delay-passive = <0>;
6722 polling-delay = <0>;
6735 hysteresis = <0>;