Lines Matching +full:sdm845 +full:- +full:lpasscc
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/sound/qcom,q6afe.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
63 xo_board: xo-board {
64 compatible = "fixed-clock";
65 clock-frequency = <38400000>;
66 #clock-cells = <0>;
69 sleep_clk: sleep-clk {
70 compatible = "fixed-clock";
71 clock-frequency = <32764>;
72 #clock-cells = <0>;
77 #address-cells = <2>;
78 #size-cells = <0>;
85 enable-method = "psci";
86 power-domains = <&CPU_PD0>;
87 power-domain-names = "psci";
88 capacity-dmips-mhz = <415>;
89 dynamic-power-coefficient = <137>;
90 operating-points-v2 = <&cpu0_opp_table>;
93 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache {
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&L3_0>;
101 L3_0: l3-cache {
103 cache-level = <3>;
104 cache-unified;
114 enable-method = "psci";
115 power-domains = <&CPU_PD1>;
116 power-domain-names = "psci";
117 capacity-dmips-mhz = <415>;
118 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L2_100>;
120 operating-points-v2 = <&cpu0_opp_table>;
123 #cooling-cells = <2>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache {
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&L3_0>;
138 enable-method = "psci";
139 power-domains = <&CPU_PD2>;
140 power-domain-names = "psci";
141 capacity-dmips-mhz = <415>;
142 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L2_200>;
144 operating-points-v2 = <&cpu0_opp_table>;
147 #cooling-cells = <2>;
148 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache {
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&L3_0>;
162 enable-method = "psci";
163 power-domains = <&CPU_PD3>;
164 power-domain-names = "psci";
165 capacity-dmips-mhz = <415>;
166 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L2_300>;
168 operating-points-v2 = <&cpu0_opp_table>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache {
175 cache-level = <2>;
176 cache-unified;
177 next-level-cache = <&L3_0>;
186 enable-method = "psci";
187 power-domains = <&CPU_PD4>;
188 power-domain-names = "psci";
189 capacity-dmips-mhz = <415>;
190 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L2_400>;
192 operating-points-v2 = <&cpu0_opp_table>;
195 #cooling-cells = <2>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache {
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&L3_0>;
210 enable-method = "psci";
211 power-domains = <&CPU_PD5>;
212 power-domain-names = "psci";
213 capacity-dmips-mhz = <415>;
214 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L2_500>;
216 operating-points-v2 = <&cpu0_opp_table>;
219 #cooling-cells = <2>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache {
223 cache-level = <2>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
234 enable-method = "psci";
235 power-domains = <&CPU_PD6>;
236 power-domain-names = "psci";
237 capacity-dmips-mhz = <1024>;
238 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L2_600>;
240 operating-points-v2 = <&cpu6_opp_table>;
243 #cooling-cells = <2>;
244 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache {
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
258 enable-method = "psci";
259 power-domains = <&CPU_PD7>;
260 power-domain-names = "psci";
261 capacity-dmips-mhz = <1024>;
262 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L2_700>;
264 operating-points-v2 = <&cpu6_opp_table>;
267 #cooling-cells = <2>;
268 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache {
271 cache-level = <2>;
272 cache-unified;
273 next-level-cache = <&L3_0>;
277 cpu-map {
313 idle_states: idle-states {
314 entry-method = "psci";
316 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = "arm,idle-state";
318 idle-state-name = "little-power-down";
319 arm,psci-suspend-param = <0x40000003>;
320 entry-latency-us = <549>;
321 exit-latency-us = <901>;
322 min-residency-us = <1774>;
323 local-timer-stop;
326 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = "arm,idle-state";
328 idle-state-name = "little-rail-power-down";
329 arm,psci-suspend-param = <0x40000004>;
330 entry-latency-us = <702>;
331 exit-latency-us = <915>;
332 min-residency-us = <4001>;
333 local-timer-stop;
336 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = "arm,idle-state";
338 idle-state-name = "big-power-down";
339 arm,psci-suspend-param = <0x40000003>;
340 entry-latency-us = <523>;
341 exit-latency-us = <1244>;
342 min-residency-us = <2207>;
343 local-timer-stop;
346 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = "arm,idle-state";
348 idle-state-name = "big-rail-power-down";
349 arm,psci-suspend-param = <0x40000004>;
350 entry-latency-us = <526>;
351 exit-latency-us = <1854>;
352 min-residency-us = <5555>;
353 local-timer-stop;
357 domain_idle_states: domain-idle-states {
358 CLUSTER_SLEEP_PC: cluster-sleep-0 {
359 compatible = "domain-idle-state";
360 idle-state-name = "cluster-l3-power-collapse";
361 arm,psci-suspend-param = <0x41000044>;
362 entry-latency-us = <2752>;
363 exit-latency-us = <3048>;
364 min-residency-us = <6118>;
367 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
368 compatible = "domain-idle-state";
369 idle-state-name = "cluster-cx-retention";
370 arm,psci-suspend-param = <0x41001244>;
371 entry-latency-us = <3638>;
372 exit-latency-us = <4562>;
373 min-residency-us = <8467>;
376 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
377 compatible = "domain-idle-state";
378 idle-state-name = "cluster-power-down";
379 arm,psci-suspend-param = <0x4100b244>;
380 entry-latency-us = <3263>;
381 exit-latency-us = <6562>;
382 min-residency-us = <9826>;
389 compatible = "qcom,scm-sc7180", "qcom,scm";
399 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points-v2";
401 opp-shared;
403 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <1200000 4800000>;
408 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <1200000 4800000>;
413 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <1200000 4800000>;
418 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <1804000 8908800>;
423 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <2188000 12902400>;
428 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <2188000 12902400>;
433 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <3072000 15052800>;
438 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <3072000 15052800>;
443 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <3072000 15052800>;
448 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <4068000 22425600>;
454 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points-v2";
456 opp-shared;
458 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <2188000 8908800>;
463 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <2188000 8908800>;
468 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <2188000 8908800>;
473 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <2188000 8908800>;
478 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <2188000 8908800>;
483 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <4068000 12902400>;
488 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <4068000 15052800>;
493 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <6220000 19353600>;
498 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <6220000 19353600>;
503 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <6220000 22425600>;
508 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <6220000 22425600>;
513 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <6220000 22425600>;
518 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <7216000 22425600>;
523 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <7216000 22425600>;
528 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <8532000 23347200>;
533 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <8532000 23347200>;
539 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points-v2";
542 opp-75000000 {
543 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmhpd_opp_low_svs>;
547 opp-150000000 {
548 opp-hz = /bits/ 64 <150000000>;
549 required-opps = <&rpmhpd_opp_svs>;
552 opp-300000000 {
553 opp-hz = /bits/ 64 <300000000>;
554 required-opps = <&rpmhpd_opp_nom>;
558 qup_opp_table: opp-table-qup {
559 compatible = "operating-points-v2";
561 opp-75000000 {
562 opp-hz = /bits/ 64 <75000000>;
563 required-opps = <&rpmhpd_opp_low_svs>;
566 opp-100000000 {
567 opp-hz = /bits/ 64 <100000000>;
568 required-opps = <&rpmhpd_opp_svs>;
571 opp-128000000 {
572 opp-hz = /bits/ 64 <128000000>;
573 required-opps = <&rpmhpd_opp_nom>;
578 compatible = "arm,armv8-pmuv3";
583 compatible = "arm,psci-1.0";
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
593 #power-domain-cells = <0>;
594 power-domains = <&CLUSTER_PD>;
595 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
599 #power-domain-cells = <0>;
600 power-domains = <&CLUSTER_PD>;
601 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
605 #power-domain-cells = <0>;
606 power-domains = <&CLUSTER_PD>;
607 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
634 CLUSTER_PD: cpu-cluster0 {
635 #power-domain-cells = <0>;
636 domain-idle-states = <&CLUSTER_SLEEP_PC
642 reserved_memory: reserved-memory {
643 #address-cells = <2>;
644 #size-cells = <2>;
649 no-map;
654 no-map;
659 no-map;
664 compatible = "qcom,cmd-db";
665 no-map;
670 no-map;
675 no-map;
680 no-map;
685 no-map;
689 compatible = "qcom,rmtfs-mem";
691 no-map;
693 qcom,client-id = <1>;
700 memory-region = <&smem_mem>;
704 smp2p-cdsp {
712 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>;
715 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells = <1>;
720 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "slave-kernel";
723 interrupt-controller;
724 #interrupt-cells = <2>;
728 smp2p-lpass {
736 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>;
739 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells = <1>;
744 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "slave-kernel";
747 interrupt-controller;
748 #interrupt-cells = <2>;
752 smp2p-mpss {
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>;
760 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
765 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
767 interrupt-controller;
768 #interrupt-cells = <2>;
771 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells = <1>;
776 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa";
778 interrupt-controller;
779 #interrupt-cells = <2>;
784 #address-cells = <2>;
785 #size-cells = <2>;
787 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus";
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-sc7180";
796 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>;
798 #reset-cells = <1>;
799 #power-domain-cells = <1>;
800 power-domains = <&rpmhpd SC7180_CX>;
804 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
811 clock-names = "core";
812 #address-cells = <1>;
813 #size-cells = <1>;
815 qusb2p_hstx_trim: hstx-trim-primary@25b {
827 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
830 reg-names = "hc", "cqhci";
835 interrupt-names = "hc_irq", "pwr_irq";
840 clock-names = "iface", "core", "xo";
843 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = <&sdhc1_opp_table>;
847 bus-width = <8>;
848 non-removable;
849 supports-cqe;
851 mmc-ddr-1_8v;
852 mmc-hs200-1_8v;
853 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-strobe;
858 sdhc1_opp_table: opp-table {
859 compatible = "operating-points-v2";
861 opp-100000000 {
862 opp-hz = /bits/ 64 <100000000>;
863 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-peak-kBps = <1800000 600000>;
865 opp-avg-kBps = <100000 0>;
868 opp-384000000 {
869 opp-hz = /bits/ 64 <384000000>;
870 required-opps = <&rpmhpd_opp_nom>;
871 opp-peak-kBps = <5400000 1600000>;
872 opp-avg-kBps = <390000 0>;
878 compatible = "qcom,geni-se-qup";
880 clock-names = "m-ahb", "s-ahb";
883 #address-cells = <2>;
884 #size-cells = <2>;
890 compatible = "qcom,geni-i2c";
892 clock-names = "se";
894 pinctrl-names = "default";
895 pinctrl-0 = <&qup_i2c0_default>;
897 #address-cells = <1>;
898 #size-cells = <0>;
902 interconnect-names = "qup-core", "qup-config",
903 "qup-memory";
904 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps = <&rpmhpd_opp_low_svs>;
910 compatible = "qcom,geni-spi";
912 clock-names = "se";
914 pinctrl-names = "default";
915 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
917 #address-cells = <1>;
918 #size-cells = <0>;
919 power-domains = <&rpmhpd SC7180_CX>;
920 operating-points-v2 = <&qup_opp_table>;
923 interconnect-names = "qup-core", "qup-config";
928 compatible = "qcom,geni-uart";
930 clock-names = "se";
932 pinctrl-names = "default";
933 pinctrl-0 = <&qup_uart0_default>;
935 power-domains = <&rpmhpd SC7180_CX>;
936 operating-points-v2 = <&qup_opp_table>;
939 interconnect-names = "qup-core", "qup-config";
944 compatible = "qcom,geni-i2c";
946 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_i2c1_default>;
951 #address-cells = <1>;
952 #size-cells = <0>;
956 interconnect-names = "qup-core", "qup-config",
957 "qup-memory";
958 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps = <&rpmhpd_opp_low_svs>;
964 compatible = "qcom,geni-spi";
966 clock-names = "se";
968 pinctrl-names = "default";
969 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
971 #address-cells = <1>;
972 #size-cells = <0>;
973 power-domains = <&rpmhpd SC7180_CX>;
974 operating-points-v2 = <&qup_opp_table>;
977 interconnect-names = "qup-core", "qup-config";
982 compatible = "qcom,geni-uart";
984 clock-names = "se";
986 pinctrl-names = "default";
987 pinctrl-0 = <&qup_uart1_default>;
989 power-domains = <&rpmhpd SC7180_CX>;
990 operating-points-v2 = <&qup_opp_table>;
993 interconnect-names = "qup-core", "qup-config";
998 compatible = "qcom,geni-i2c";
1000 clock-names = "se";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_i2c2_default>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1010 interconnect-names = "qup-core", "qup-config",
1011 "qup-memory";
1012 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps = <&rpmhpd_opp_low_svs>;
1018 compatible = "qcom,geni-uart";
1020 clock-names = "se";
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_uart2_default>;
1025 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-points-v2 = <&qup_opp_table>;
1029 interconnect-names = "qup-core", "qup-config";
1034 compatible = "qcom,geni-i2c";
1036 clock-names = "se";
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_i2c3_default>;
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1046 interconnect-names = "qup-core", "qup-config",
1047 "qup-memory";
1048 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps = <&rpmhpd_opp_low_svs>;
1054 compatible = "qcom,geni-spi";
1056 clock-names = "se";
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-points-v2 = <&qup_opp_table>;
1067 interconnect-names = "qup-core", "qup-config";
1072 compatible = "qcom,geni-uart";
1074 clock-names = "se";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_uart3_default>;
1079 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-points-v2 = <&qup_opp_table>;
1083 interconnect-names = "qup-core", "qup-config";
1088 compatible = "qcom,geni-i2c";
1090 clock-names = "se";
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c4_default>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1100 interconnect-names = "qup-core", "qup-config",
1101 "qup-memory";
1102 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps = <&rpmhpd_opp_low_svs>;
1108 compatible = "qcom,geni-uart";
1110 clock-names = "se";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_uart4_default>;
1115 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-points-v2 = <&qup_opp_table>;
1119 interconnect-names = "qup-core", "qup-config";
1124 compatible = "qcom,geni-i2c";
1126 clock-names = "se";
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&qup_i2c5_default>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1136 interconnect-names = "qup-core", "qup-config",
1137 "qup-memory";
1138 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps = <&rpmhpd_opp_low_svs>;
1144 compatible = "qcom,geni-spi";
1146 clock-names = "se";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-points-v2 = <&qup_opp_table>;
1157 interconnect-names = "qup-core", "qup-config";
1162 compatible = "qcom,geni-uart";
1164 clock-names = "se";
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_uart5_default>;
1169 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-points-v2 = <&qup_opp_table>;
1173 interconnect-names = "qup-core", "qup-config";
1179 compatible = "qcom,geni-se-qup";
1181 clock-names = "m-ahb", "s-ahb";
1184 #address-cells = <2>;
1185 #size-cells = <2>;
1191 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_i2c6_default>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1203 interconnect-names = "qup-core", "qup-config",
1204 "qup-memory";
1205 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps = <&rpmhpd_opp_low_svs>;
1211 compatible = "qcom,geni-spi";
1213 clock-names = "se";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-points-v2 = <&qup_opp_table>;
1224 interconnect-names = "qup-core", "qup-config";
1229 compatible = "qcom,geni-uart";
1231 clock-names = "se";
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_uart6_default>;
1236 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-points-v2 = <&qup_opp_table>;
1240 interconnect-names = "qup-core", "qup-config";
1245 compatible = "qcom,geni-i2c";
1247 clock-names = "se";
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_i2c7_default>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1257 interconnect-names = "qup-core", "qup-config",
1258 "qup-memory";
1259 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps = <&rpmhpd_opp_low_svs>;
1265 compatible = "qcom,geni-uart";
1267 clock-names = "se";
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart7_default>;
1272 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1276 interconnect-names = "qup-core", "qup-config";
1281 compatible = "qcom,geni-i2c";
1283 clock-names = "se";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_i2c8_default>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1293 interconnect-names = "qup-core", "qup-config",
1294 "qup-memory";
1295 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps = <&rpmhpd_opp_low_svs>;
1301 compatible = "qcom,geni-spi";
1303 clock-names = "se";
1305 pinctrl-names = "default";
1306 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-points-v2 = <&qup_opp_table>;
1314 interconnect-names = "qup-core", "qup-config";
1319 compatible = "qcom,geni-debug-uart";
1321 clock-names = "se";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_uart8_default>;
1326 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-points-v2 = <&qup_opp_table>;
1330 interconnect-names = "qup-core", "qup-config";
1335 compatible = "qcom,geni-i2c";
1337 clock-names = "se";
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c9_default>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1347 interconnect-names = "qup-core", "qup-config",
1348 "qup-memory";
1349 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps = <&rpmhpd_opp_low_svs>;
1355 compatible = "qcom,geni-uart";
1357 clock-names = "se";
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_uart9_default>;
1362 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-points-v2 = <&qup_opp_table>;
1366 interconnect-names = "qup-core", "qup-config";
1371 compatible = "qcom,geni-i2c";
1373 clock-names = "se";
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&qup_i2c10_default>;
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1383 interconnect-names = "qup-core", "qup-config",
1384 "qup-memory";
1385 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps = <&rpmhpd_opp_low_svs>;
1391 compatible = "qcom,geni-spi";
1393 clock-names = "se";
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-points-v2 = <&qup_opp_table>;
1404 interconnect-names = "qup-core", "qup-config";
1409 compatible = "qcom,geni-uart";
1411 clock-names = "se";
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_uart10_default>;
1416 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-points-v2 = <&qup_opp_table>;
1420 interconnect-names = "qup-core", "qup-config";
1425 compatible = "qcom,geni-i2c";
1427 clock-names = "se";
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&qup_i2c11_default>;
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1437 interconnect-names = "qup-core", "qup-config",
1438 "qup-memory";
1439 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps = <&rpmhpd_opp_low_svs>;
1445 compatible = "qcom,geni-spi";
1447 clock-names = "se";
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1454 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-points-v2 = <&qup_opp_table>;
1458 interconnect-names = "qup-core", "qup-config";
1463 compatible = "qcom,geni-uart";
1465 clock-names = "se";
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&qup_uart11_default>;
1470 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-points-v2 = <&qup_opp_table>;
1474 interconnect-names = "qup-core", "qup-config";
1480 compatible = "qcom,sc7180-config-noc";
1482 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&apps_bcm_voter>;
1487 compatible = "qcom,sc7180-system-noc";
1489 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&apps_bcm_voter>;
1494 compatible = "qcom,sc7180-mc-virt";
1496 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&apps_bcm_voter>;
1501 compatible = "qcom,sc7180-qup-virt";
1503 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&apps_bcm_voter>;
1508 compatible = "qcom,sc7180-aggre1-noc";
1510 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&apps_bcm_voter>;
1515 compatible = "qcom,sc7180-aggre2-noc";
1517 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&apps_bcm_voter>;
1522 compatible = "qcom,sc7180-compute-noc";
1524 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&apps_bcm_voter>;
1529 compatible = "qcom,sc7180-mmss-noc";
1531 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&apps_bcm_voter>;
1536 compatible = "qcom,sc7180-ipa";
1543 reg-names = "ipa-reg",
1544 "ipa-shared",
1547 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1551 interrupt-names = "ipa",
1553 "ipa-clock-query",
1554 "ipa-setup-ready";
1557 clock-names = "core";
1562 interconnect-names = "memory",
1568 qcom,smem-states = <&ipa_smp2p_out 0>,
1570 qcom,smem-state-names = "ipa-clock-enabled-valid",
1571 "ipa-clock-enabled";
1577 compatible = "qcom,tcsr-mutex";
1579 #hwlock-cells = <1>;
1583 compatible = "qcom,sc7180-tcsr", "syscon";
1588 compatible = "qcom,sc7180-tcsr", "syscon";
1593 compatible = "qcom,sc7180-pinctrl";
1597 reg-names = "west", "north", "south";
1599 gpio-controller;
1600 #gpio-cells = <2>;
1601 interrupt-controller;
1602 #interrupt-cells = <2>;
1603 gpio-ranges = <&tlmm 0 0 120>;
1604 wakeup-parent = <&pdc>;
1606 dp_hot_plug_det: dp-hot-plug-det-state {
1611 qspi_clk: qspi-clk-state {
1616 qspi_cs0: qspi-cs0-state {
1621 qspi_cs1: qspi-cs1-state {
1626 qspi_data0: qspi-data0-state {
1631 qspi_data1: qspi-data1-state {
1636 qspi_data23: qspi-data23-state {
1641 qup_i2c0_default: qup-i2c0-default-state {
1646 qup_i2c1_default: qup-i2c1-default-state {
1651 qup_i2c2_default: qup-i2c2-default-state {
1656 qup_i2c3_default: qup-i2c3-default-state {
1661 qup_i2c4_default: qup-i2c4-default-state {
1666 qup_i2c5_default: qup-i2c5-default-state {
1671 qup_i2c6_default: qup-i2c6-default-state {
1676 qup_i2c7_default: qup-i2c7-default-state {
1681 qup_i2c8_default: qup-i2c8-default-state {
1686 qup_i2c9_default: qup-i2c9-default-state {
1691 qup_i2c10_default: qup-i2c10-default-state {
1696 qup_i2c11_default: qup-i2c11-default-state {
1701 qup_spi0_spi: qup-spi0-spi-state {
1706 qup_spi0_cs: qup-spi0-cs-state {
1711 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1716 qup_spi1_spi: qup-spi1-spi-state {
1721 qup_spi1_cs: qup-spi1-cs-state {
1726 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1731 qup_spi3_spi: qup-spi3-spi-state {
1736 qup_spi3_cs: qup-spi3-cs-state {
1741 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1746 qup_spi5_spi: qup-spi5-spi-state {
1751 qup_spi5_cs: qup-spi5-cs-state {
1756 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1761 qup_spi6_spi: qup-spi6-spi-state {
1766 qup_spi6_cs: qup-spi6-cs-state {
1771 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1776 qup_spi8_spi: qup-spi8-spi-state {
1781 qup_spi8_cs: qup-spi8-cs-state {
1786 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1791 qup_spi10_spi: qup-spi10-spi-state {
1796 qup_spi10_cs: qup-spi10-cs-state {
1801 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1806 qup_spi11_spi: qup-spi11-spi-state {
1811 qup_spi11_cs: qup-spi11-cs-state {
1816 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1821 qup_uart0_default: qup-uart0-default-state {
1822 qup_uart0_cts: cts-pins {
1827 qup_uart0_rts: rts-pins {
1832 qup_uart0_tx: tx-pins {
1837 qup_uart0_rx: rx-pins {
1843 qup_uart1_default: qup-uart1-default-state {
1844 qup_uart1_cts: cts-pins {
1849 qup_uart1_rts: rts-pins {
1854 qup_uart1_tx: tx-pins {
1859 qup_uart1_rx: rx-pins {
1865 qup_uart2_default: qup-uart2-default-state {
1866 qup_uart2_tx: tx-pins {
1871 qup_uart2_rx: rx-pins {
1877 qup_uart3_default: qup-uart3-default-state {
1878 qup_uart3_cts: cts-pins {
1883 qup_uart3_rts: rts-pins {
1888 qup_uart3_tx: tx-pins {
1893 qup_uart3_rx: rx-pins {
1899 qup_uart4_default: qup-uart4-default-state {
1900 qup_uart4_tx: tx-pins {
1905 qup_uart4_rx: rx-pins {
1911 qup_uart5_default: qup-uart5-default-state {
1912 qup_uart5_cts: cts-pins {
1917 qup_uart5_rts: rts-pins {
1922 qup_uart5_tx: tx-pins {
1927 qup_uart5_rx: rx-pins {
1933 qup_uart6_default: qup-uart6-default-state {
1934 qup_uart6_cts: cts-pins {
1939 qup_uart6_rts: rts-pins {
1944 qup_uart6_tx: tx-pins {
1949 qup_uart6_rx: rx-pins {
1955 qup_uart7_default: qup-uart7-default-state {
1956 qup_uart7_tx: tx-pins {
1961 qup_uart7_rx: rx-pins {
1967 qup_uart8_default: qup-uart8-default-state {
1968 qup_uart8_tx: tx-pins {
1973 qup_uart8_rx: rx-pins {
1979 qup_uart9_default: qup-uart9-default-state {
1980 qup_uart9_tx: tx-pins {
1985 qup_uart9_rx: rx-pins {
1991 qup_uart10_default: qup-uart10-default-state {
1992 qup_uart10_cts: cts-pins {
1997 qup_uart10_rts: rts-pins {
2002 qup_uart10_tx: tx-pins {
2007 qup_uart10_rx: rx-pins {
2013 qup_uart11_default: qup-uart11-default-state {
2014 qup_uart11_cts: cts-pins {
2019 qup_uart11_rts: rts-pins {
2024 qup_uart11_tx: tx-pins {
2029 qup_uart11_rx: rx-pins {
2035 sec_mi2s_active: sec-mi2s-active-state {
2040 pri_mi2s_active: pri-mi2s-active-state {
2045 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2050 ter_mi2s_active: ter-mi2s-active-state {
2057 compatible = "qcom,sc7180-mpss-pas";
2060 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2066 interrupt-names = "wdog", "fatal", "ready", "handover",
2067 "stop-ack", "shutdown-ack";
2070 clock-names = "xo";
2072 power-domains = <&rpmhpd SC7180_CX>,
2075 power-domain-names = "cx", "mx", "mss";
2077 memory-region = <&mpss_mem>;
2081 qcom,smem-states = <&modem_smp2p_out 0>;
2082 qcom,smem-state-names = "stop";
2086 glink-edge {
2089 qcom,remote-pid = <1>;
2095 compatible = "qcom,adreno-618.0", "qcom,adreno";
2098 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2101 operating-points-v2 = <&gpu_opp_table>;
2104 #cooling-cells = <2>;
2106 nvmem-cells = <&gpu_speed_bin>;
2107 nvmem-cell-names = "speed_bin";
2110 interconnect-names = "gfx-mem";
2112 gpu_opp_table: opp-table {
2113 compatible = "operating-points-v2";
2115 opp-825000000 {
2116 opp-hz = /bits/ 64 <825000000>;
2117 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2118 opp-peak-kBps = <8532000>;
2119 opp-supported-hw = <0x04>;
2122 opp-800000000 {
2123 opp-hz = /bits/ 64 <800000000>;
2124 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2125 opp-peak-kBps = <8532000>;
2126 opp-supported-hw = <0x07>;
2129 opp-650000000 {
2130 opp-hz = /bits/ 64 <650000000>;
2131 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2132 opp-peak-kBps = <7216000>;
2133 opp-supported-hw = <0x07>;
2136 opp-565000000 {
2137 opp-hz = /bits/ 64 <565000000>;
2138 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2139 opp-peak-kBps = <5412000>;
2140 opp-supported-hw = <0x07>;
2143 opp-430000000 {
2144 opp-hz = /bits/ 64 <430000000>;
2145 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2146 opp-peak-kBps = <5412000>;
2147 opp-supported-hw = <0x07>;
2150 opp-355000000 {
2151 opp-hz = /bits/ 64 <355000000>;
2152 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2153 opp-peak-kBps = <3072000>;
2154 opp-supported-hw = <0x07>;
2157 opp-267000000 {
2158 opp-hz = /bits/ 64 <267000000>;
2159 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2160 opp-peak-kBps = <3072000>;
2161 opp-supported-hw = <0x07>;
2164 opp-180000000 {
2165 opp-hz = /bits/ 64 <180000000>;
2166 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2167 opp-peak-kBps = <1804000>;
2168 opp-supported-hw = <0x07>;
2174 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2176 #iommu-cells = <1>;
2177 #global-interrupts = <2>;
2191 clock-names = "bus", "iface";
2193 power-domains = <&gpucc CX_GDSC>;
2197 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2200 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2203 interrupt-names = "hfi", "gmu";
2208 clock-names = "gmu", "cxo", "axi", "memnoc";
2209 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2210 power-domain-names = "cx", "gx";
2212 operating-points-v2 = <&gmu_opp_table>;
2214 gmu_opp_table: opp-table {
2215 compatible = "operating-points-v2";
2217 opp-200000000 {
2218 opp-hz = /bits/ 64 <200000000>;
2219 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2224 gpucc: clock-controller@5090000 {
2225 compatible = "qcom,sc7180-gpucc";
2230 clock-names = "bi_tcxo",
2233 #clock-cells = <1>;
2234 #reset-cells = <1>;
2235 #power-domain-cells = <1>;
2239 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2245 compatible = "arm,coresight-stm", "arm,primecell";
2248 reg-names = "stm-base", "stm-stimulus-base";
2251 clock-names = "apb_pclk";
2253 out-ports {
2256 remote-endpoint = <&funnel0_in7>;
2263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2267 clock-names = "apb_pclk";
2269 out-ports {
2272 remote-endpoint = <&merge_funnel_in0>;
2277 in-ports {
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2284 remote-endpoint = <&stm_out>;
2291 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2295 clock-names = "apb_pclk";
2297 out-ports {
2300 remote-endpoint = <&merge_funnel_in1>;
2305 in-ports {
2306 #address-cells = <1>;
2307 #size-cells = <0>;
2312 remote-endpoint = <&apss_merge_funnel_out>;
2319 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2323 clock-names = "apb_pclk";
2325 out-ports {
2328 remote-endpoint = <&swao_funnel_in>;
2333 in-ports {
2334 #address-cells = <1>;
2335 #size-cells = <0>;
2340 remote-endpoint = <&funnel0_out>;
2347 remote-endpoint = <&funnel1_out>;
2354 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2358 clock-names = "apb_pclk";
2360 out-ports {
2363 remote-endpoint = <&etr_in>;
2368 in-ports {
2371 remote-endpoint = <&swao_replicator_out>;
2378 compatible = "arm,coresight-tmc", "arm,primecell";
2383 clock-names = "apb_pclk";
2384 arm,scatter-gather;
2386 in-ports {
2389 remote-endpoint = <&replicator_out>;
2396 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2400 clock-names = "apb_pclk";
2402 out-ports {
2405 remote-endpoint = <&etf_in>;
2410 in-ports {
2411 #address-cells = <1>;
2412 #size-cells = <0>;
2417 remote-endpoint = <&merge_funnel_out>;
2424 compatible = "arm,coresight-tmc", "arm,primecell";
2428 clock-names = "apb_pclk";
2430 out-ports {
2433 remote-endpoint = <&swao_replicator_in>;
2438 in-ports {
2441 remote-endpoint = <&swao_funnel_out>;
2448 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2452 clock-names = "apb_pclk";
2453 qcom,replicator-loses-context;
2455 out-ports {
2458 remote-endpoint = <&replicator_in>;
2463 in-ports {
2466 remote-endpoint = <&etf_out>;
2473 compatible = "arm,coresight-etm4x", "arm,primecell";
2479 clock-names = "apb_pclk";
2480 arm,coresight-loses-context-with-cpu;
2481 qcom,skip-power-up;
2483 out-ports {
2486 remote-endpoint = <&apss_funnel_in0>;
2493 compatible = "arm,coresight-etm4x", "arm,primecell";
2499 clock-names = "apb_pclk";
2500 arm,coresight-loses-context-with-cpu;
2501 qcom,skip-power-up;
2503 out-ports {
2506 remote-endpoint = <&apss_funnel_in1>;
2513 compatible = "arm,coresight-etm4x", "arm,primecell";
2519 clock-names = "apb_pclk";
2520 arm,coresight-loses-context-with-cpu;
2521 qcom,skip-power-up;
2523 out-ports {
2526 remote-endpoint = <&apss_funnel_in2>;
2533 compatible = "arm,coresight-etm4x", "arm,primecell";
2539 clock-names = "apb_pclk";
2540 arm,coresight-loses-context-with-cpu;
2541 qcom,skip-power-up;
2543 out-ports {
2546 remote-endpoint = <&apss_funnel_in3>;
2553 compatible = "arm,coresight-etm4x", "arm,primecell";
2559 clock-names = "apb_pclk";
2560 arm,coresight-loses-context-with-cpu;
2561 qcom,skip-power-up;
2563 out-ports {
2566 remote-endpoint = <&apss_funnel_in4>;
2573 compatible = "arm,coresight-etm4x", "arm,primecell";
2579 clock-names = "apb_pclk";
2580 arm,coresight-loses-context-with-cpu;
2581 qcom,skip-power-up;
2583 out-ports {
2586 remote-endpoint = <&apss_funnel_in5>;
2593 compatible = "arm,coresight-etm4x", "arm,primecell";
2599 clock-names = "apb_pclk";
2600 arm,coresight-loses-context-with-cpu;
2601 qcom,skip-power-up;
2603 out-ports {
2606 remote-endpoint = <&apss_funnel_in6>;
2613 compatible = "arm,coresight-etm4x", "arm,primecell";
2619 clock-names = "apb_pclk";
2620 arm,coresight-loses-context-with-cpu;
2621 qcom,skip-power-up;
2623 out-ports {
2626 remote-endpoint = <&apss_funnel_in7>;
2633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2637 clock-names = "apb_pclk";
2639 out-ports {
2642 remote-endpoint = <&apss_merge_funnel_in>;
2647 in-ports {
2648 #address-cells = <1>;
2649 #size-cells = <0>;
2654 remote-endpoint = <&etm0_out>;
2661 remote-endpoint = <&etm1_out>;
2668 remote-endpoint = <&etm2_out>;
2675 remote-endpoint = <&etm3_out>;
2682 remote-endpoint = <&etm4_out>;
2689 remote-endpoint = <&etm5_out>;
2696 remote-endpoint = <&etm6_out>;
2703 remote-endpoint = <&etm7_out>;
2710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2714 clock-names = "apb_pclk";
2716 out-ports {
2719 remote-endpoint = <&funnel1_in4>;
2724 in-ports {
2727 remote-endpoint = <&apss_funnel_out>;
2734 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2740 interrupt-names = "hc_irq", "pwr_irq";
2745 clock-names = "iface", "core", "xo";
2749 interconnect-names = "sdhc-ddr","cpu-sdhc";
2750 power-domains = <&rpmhpd SC7180_CX>;
2751 operating-points-v2 = <&sdhc2_opp_table>;
2753 bus-width = <4>;
2757 sdhc2_opp_table: opp-table {
2758 compatible = "operating-points-v2";
2760 opp-100000000 {
2761 opp-hz = /bits/ 64 <100000000>;
2762 required-opps = <&rpmhpd_opp_low_svs>;
2763 opp-peak-kBps = <1800000 600000>;
2764 opp-avg-kBps = <100000 0>;
2767 opp-202000000 {
2768 opp-hz = /bits/ 64 <202000000>;
2769 required-opps = <&rpmhpd_opp_nom>;
2770 opp-peak-kBps = <5400000 1600000>;
2771 opp-avg-kBps = <200000 0>;
2777 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2780 #address-cells = <1>;
2781 #size-cells = <0>;
2785 clock-names = "iface", "core";
2788 interconnect-names = "qspi-config";
2789 power-domains = <&rpmhpd SC7180_CX>;
2790 operating-points-v2 = <&qspi_opp_table>;
2795 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2798 #phy-cells = <0>;
2801 clock-names = "cfg_ahb", "ref";
2804 nvmem-cells = <&qusb2p_hstx_trim>;
2808 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2817 clock-names = "aux",
2825 reset-names = "phy", "common";
2827 #clock-cells = <1>;
2828 #phy-cells = <1>;
2832 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2838 operating-points-v2 = <&cpu_bwmon_opp_table>;
2840 cpu_bwmon_opp_table: opp-table {
2841 compatible = "operating-points-v2";
2843 opp-0 {
2844 opp-peak-kBps = <2288000>;
2847 opp-1 {
2848 opp-peak-kBps = <4577000>;
2851 opp-2 {
2852 opp-peak-kBps = <7110000>;
2855 opp-3 {
2856 opp-peak-kBps = <9155000>;
2859 opp-4 {
2860 opp-peak-kBps = <12298000>;
2863 opp-5 {
2864 opp-peak-kBps = <14236000>;
2870 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2876 operating-points-v2 = <&llcc_bwmon_opp_table>;
2878 llcc_bwmon_opp_table: opp-table {
2879 compatible = "operating-points-v2";
2881 opp-0 {
2882 opp-peak-kBps = <1144000>;
2885 opp-1 {
2886 opp-peak-kBps = <1720000>;
2889 opp-2 {
2890 opp-peak-kBps = <2086000>;
2893 opp-3 {
2894 opp-peak-kBps = <2929000>;
2897 opp-4 {
2898 opp-peak-kBps = <3879000>;
2901 opp-5 {
2902 opp-peak-kBps = <5931000>;
2905 opp-6 {
2906 opp-peak-kBps = <6881000>;
2909 opp-7 {
2910 opp-peak-kBps = <8137000>;
2916 compatible = "qcom,sc7180-dc-noc";
2918 #interconnect-cells = <2>;
2919 qcom,bcm-voters = <&apps_bcm_voter>;
2922 system-cache-controller@9200000 {
2923 compatible = "qcom,sc7180-llcc";
2925 reg-names = "llcc0_base", "llcc_broadcast_base";
2930 compatible = "qcom,sc7180-gem-noc";
2932 #interconnect-cells = <2>;
2933 qcom,bcm-voters = <&apps_bcm_voter>;
2937 compatible = "qcom,sc7180-npu-noc";
2939 #interconnect-cells = <2>;
2940 qcom,bcm-voters = <&apps_bcm_voter>;
2944 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2947 #address-cells = <2>;
2948 #size-cells = <2>;
2950 dma-ranges;
2957 clock-names = "cfg_noc",
2963 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2965 assigned-clock-rates = <19200000>, <150000000>;
2967 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2971 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2974 power-domains = <&gcc USB30_PRIM_GDSC>;
2975 required-opps = <&rpmhpd_opp_nom>;
2981 interconnect-names = "usb-ddr", "apps-usb";
2983 wakeup-source;
2993 phy-names = "usb2-phy", "usb3-phy";
2994 maximum-speed = "super-speed";
2998 venus: video-codec@aa00000 {
2999 compatible = "qcom,sc7180-venus";
3002 power-domains = <&videocc VENUS_GDSC>,
3005 power-domain-names = "venus", "vcodec0", "cx";
3006 operating-points-v2 = <&venus_opp_table>;
3012 clock-names = "core", "iface", "bus",
3015 memory-region = <&venus_mem>;
3018 interconnect-names = "video-mem", "cpu-cfg";
3020 video-decoder {
3021 compatible = "venus-decoder";
3024 video-encoder {
3025 compatible = "venus-encoder";
3028 venus_opp_table: opp-table {
3029 compatible = "operating-points-v2";
3031 opp-150000000 {
3032 opp-hz = /bits/ 64 <150000000>;
3033 required-opps = <&rpmhpd_opp_low_svs>;
3036 opp-270000000 {
3037 opp-hz = /bits/ 64 <270000000>;
3038 required-opps = <&rpmhpd_opp_svs>;
3041 opp-340000000 {
3042 opp-hz = /bits/ 64 <340000000>;
3043 required-opps = <&rpmhpd_opp_svs_l1>;
3046 opp-434000000 {
3047 opp-hz = /bits/ 64 <434000000>;
3048 required-opps = <&rpmhpd_opp_nom>;
3051 opp-500000097 {
3052 opp-hz = /bits/ 64 <500000097>;
3053 required-opps = <&rpmhpd_opp_turbo>;
3058 videocc: clock-controller@ab00000 {
3059 compatible = "qcom,sc7180-videocc";
3062 clock-names = "bi_tcxo";
3063 #clock-cells = <1>;
3064 #reset-cells = <1>;
3065 #power-domain-cells = <1>;
3069 compatible = "qcom,sc7180-camnoc-virt";
3071 #interconnect-cells = <2>;
3072 qcom,bcm-voters = <&apps_bcm_voter>;
3075 camcc: clock-controller@ad00000 {
3076 compatible = "qcom,sc7180-camcc";
3081 clock-names = "bi_tcxo", "iface", "xo";
3082 #clock-cells = <1>;
3083 #reset-cells = <1>;
3084 #power-domain-cells = <1>;
3087 mdss: display-subsystem@ae00000 {
3088 compatible = "qcom,sc7180-mdss";
3090 reg-names = "mdss";
3092 power-domains = <&dispcc MDSS_GDSC>;
3097 clock-names = "iface", "ahb", "core";
3100 interrupt-controller;
3101 #interrupt-cells = <1>;
3107 interconnect-names = "mdp0-mem",
3108 "cpu-cfg";
3112 #address-cells = <2>;
3113 #size-cells = <2>;
3118 mdp: display-controller@ae01000 {
3119 compatible = "qcom,sc7180-dpu";
3122 reg-names = "mdp", "vbif";
3130 clock-names = "bus", "iface", "rot", "lut", "core",
3132 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3135 assigned-clock-rates = <19200000>,
3138 operating-points-v2 = <&mdp_opp_table>;
3139 power-domains = <&rpmhpd SC7180_CX>;
3141 interrupt-parent = <&mdss>;
3145 #address-cells = <1>;
3146 #size-cells = <0>;
3151 remote-endpoint = <&mdss_dsi0_in>;
3158 remote-endpoint = <&dp_in>;
3163 mdp_opp_table: opp-table {
3164 compatible = "operating-points-v2";
3166 opp-200000000 {
3167 opp-hz = /bits/ 64 <200000000>;
3168 required-opps = <&rpmhpd_opp_low_svs>;
3171 opp-300000000 {
3172 opp-hz = /bits/ 64 <300000000>;
3173 required-opps = <&rpmhpd_opp_svs>;
3176 opp-345000000 {
3177 opp-hz = /bits/ 64 <345000000>;
3178 required-opps = <&rpmhpd_opp_svs_l1>;
3181 opp-460000000 {
3182 opp-hz = /bits/ 64 <460000000>;
3183 required-opps = <&rpmhpd_opp_nom>;
3189 compatible = "qcom,sc7180-dsi-ctrl",
3190 "qcom,mdss-dsi-ctrl";
3192 reg-names = "dsi_ctrl";
3194 interrupt-parent = <&mdss>;
3203 clock-names = "byte",
3210 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3211 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3213 operating-points-v2 = <&dsi_opp_table>;
3214 power-domains = <&rpmhpd SC7180_CX>;
3218 #address-cells = <1>;
3219 #size-cells = <0>;
3224 #address-cells = <1>;
3225 #size-cells = <0>;
3230 remote-endpoint = <&dpu_intf1_out>;
3241 dsi_opp_table: opp-table {
3242 compatible = "operating-points-v2";
3244 opp-187500000 {
3245 opp-hz = /bits/ 64 <187500000>;
3246 required-opps = <&rpmhpd_opp_low_svs>;
3249 opp-300000000 {
3250 opp-hz = /bits/ 64 <300000000>;
3251 required-opps = <&rpmhpd_opp_svs>;
3254 opp-358000000 {
3255 opp-hz = /bits/ 64 <358000000>;
3256 required-opps = <&rpmhpd_opp_svs_l1>;
3262 compatible = "qcom,dsi-phy-10nm";
3266 reg-names = "dsi_phy",
3270 #clock-cells = <1>;
3271 #phy-cells = <0>;
3275 clock-names = "iface", "ref";
3280 mdss_dp: displayport-controller@ae90000 {
3281 compatible = "qcom,sc7180-dp";
3290 interrupt-parent = <&mdss>;
3298 clock-names = "core_iface", "core_aux", "ctrl_link",
3300 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3302 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3305 phy-names = "dp";
3307 operating-points-v2 = <&dp_opp_table>;
3308 power-domains = <&rpmhpd SC7180_CX>;
3310 #sound-dai-cells = <0>;
3313 #address-cells = <1>;
3314 #size-cells = <0>;
3318 remote-endpoint = <&dpu_intf0_out>;
3328 dp_opp_table: opp-table {
3329 compatible = "operating-points-v2";
3331 opp-160000000 {
3332 opp-hz = /bits/ 64 <160000000>;
3333 required-opps = <&rpmhpd_opp_low_svs>;
3336 opp-270000000 {
3337 opp-hz = /bits/ 64 <270000000>;
3338 required-opps = <&rpmhpd_opp_svs>;
3341 opp-540000000 {
3342 opp-hz = /bits/ 64 <540000000>;
3343 required-opps = <&rpmhpd_opp_svs_l1>;
3346 opp-810000000 {
3347 opp-hz = /bits/ 64 <810000000>;
3348 required-opps = <&rpmhpd_opp_nom>;
3354 dispcc: clock-controller@af00000 {
3355 compatible = "qcom,sc7180-dispcc";
3363 clock-names = "bi_tcxo",
3369 #clock-cells = <1>;
3370 #reset-cells = <1>;
3371 #power-domain-cells = <1>;
3374 pdc: interrupt-controller@b220000 {
3375 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3377 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3378 #interrupt-cells = <2>;
3379 interrupt-parent = <&intc>;
3380 interrupt-controller;
3383 pdc_reset: reset-controller@b2e0000 {
3384 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3386 #reset-cells = <1>;
3389 tsens0: thermal-sensor@c263000 {
3390 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3396 interrupt-names = "uplow","critical";
3397 #thermal-sensor-cells = <1>;
3400 tsens1: thermal-sensor@c265000 {
3401 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3407 interrupt-names = "uplow","critical";
3408 #thermal-sensor-cells = <1>;
3411 aoss_reset: reset-controller@c2a0000 {
3412 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3414 #reset-cells = <1>;
3417 aoss_qmp: power-management@c300000 {
3418 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3423 #clock-cells = <0>;
3427 compatible = "qcom,rpmh-stats";
3432 compatible = "qcom,spmi-pmic-arb";
3438 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3439 interrupt-names = "periph_irq";
3440 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3443 #address-cells = <2>;
3444 #size-cells = <0>;
3445 interrupt-controller;
3446 #interrupt-cells = <4>;
3450 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3453 #address-cells = <1>;
3454 #size-cells = <1>;
3458 pil-reloc@94c {
3459 compatible = "qcom,pil-reloc-info";
3465 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3467 #iommu-cells = <2>;
3468 #global-interrupts = <1>;
3552 intc: interrupt-controller@17a00000 {
3553 compatible = "arm,gic-v3";
3554 #address-cells = <2>;
3555 #size-cells = <2>;
3557 #interrupt-cells = <3>;
3558 interrupt-controller;
3563 msi-controller@17a40000 {
3564 compatible = "arm,gic-v3-its";
3565 msi-controller;
3566 #msi-cells = <1>;
3573 compatible = "qcom,sc7180-apss-shared",
3574 "qcom,sdm845-apss-shared";
3576 #mbox-cells = <1>;
3580 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3587 #address-cells = <1>;
3588 #size-cells = <1>;
3590 compatible = "arm,armv7-timer-mem";
3594 frame-number = <0>;
3602 frame-number = <1>;
3609 frame-number = <2>;
3616 frame-number = <3>;
3623 frame-number = <4>;
3630 frame-number = <5>;
3637 frame-number = <6>;
3645 compatible = "qcom,rpmh-rsc";
3649 reg-names = "drv-0", "drv-1", "drv-2";
3653 qcom,tcs-offset = <0xd00>;
3654 qcom,drv-id = <2>;
3655 qcom,tcs-config = <ACTIVE_TCS 2>,
3659 power-domains = <&CLUSTER_PD>;
3661 rpmhcc: clock-controller {
3662 compatible = "qcom,sc7180-rpmh-clk";
3664 clock-names = "xo";
3665 #clock-cells = <1>;
3668 rpmhpd: power-controller {
3669 compatible = "qcom,sc7180-rpmhpd";
3670 #power-domain-cells = <1>;
3671 operating-points-v2 = <&rpmhpd_opp_table>;
3673 rpmhpd_opp_table: opp-table {
3674 compatible = "operating-points-v2";
3677 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3681 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3685 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3689 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3693 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3697 opp-level = <224>;
3701 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3705 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3709 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3713 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3717 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3722 apps_bcm_voter: bcm-voter {
3723 compatible = "qcom,bcm-voter";
3728 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3732 clock-names = "xo", "alternate";
3734 #interconnect-cells = <1>;
3738 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3740 reg-names = "freq-domain0", "freq-domain1";
3743 clock-names = "xo", "alternate";
3745 #freq-domain-cells = <1>;
3746 #clock-cells = <1>;
3750 compatible = "qcom,wcn3990-wifi";
3752 reg-names = "membase";
3767 memory-region = <&wlan_mem>;
3768 qcom,msa-fixed-perm;
3773 compatible = "qcom,sc7180-adsp-pas";
3776 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3781 interrupt-names = "wdog",
3785 "stop-ack";
3788 clock-names = "xo";
3790 power-domains = <&rpmhpd SC7180_LCX>,
3792 power-domain-names = "lcx", "lmx";
3795 qcom,smem-states = <&adsp_smp2p_out 0>;
3796 qcom,smem-state-names = "stop";
3800 glink-edge {
3803 qcom,remote-pid = <2>;
3807 compatible = "qcom,apr-v2";
3808 qcom,glink-channels = "apr_audio_svc";
3810 #address-cells = <1>;
3811 #size-cells = <0>;
3816 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3822 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3825 compatible = "qcom,q6afe-dais";
3826 #address-cells = <1>;
3827 #size-cells = <0>;
3828 #sound-dai-cells = <1>;
3831 q6afecc: clock-controller {
3832 compatible = "qcom,q6afe-clocks";
3833 #clock-cells = <2>;
3840 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3843 compatible = "qcom,q6asm-dais";
3844 #address-cells = <1>;
3845 #size-cells = <0>;
3846 #sound-dai-cells = <1>;
3854 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3857 compatible = "qcom,q6adm-routing";
3858 #sound-dai-cells = <0>;
3865 qcom,glink-channels = "fastrpcglink-apps-dsp";
3867 #address-cells = <1>;
3868 #size-cells = <0>;
3870 compute-cb@3 {
3871 compatible = "qcom,fastrpc-compute-cb";
3876 compute-cb@4 {
3877 compatible = "qcom,fastrpc-compute-cb";
3882 compute-cb@5 {
3883 compatible = "qcom,fastrpc-compute-cb";
3892 lpasscc: clock-controller@62d00000 {
3893 compatible = "qcom,sc7180-lpasscorecc";
3896 reg-names = "lpass_core_cc", "lpass_audio_cc";
3899 clock-names = "iface", "bi_tcxo";
3900 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3901 #clock-cells = <1>;
3902 #power-domain-cells = <1>;
3908 compatible = "qcom,sc7180-lpass-cpu";
3911 reg-names = "lpass-hdmiif", "lpass-lpaif";
3917 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3918 required-opps = <&rpmhpd_opp_nom>;
3923 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3924 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3925 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3926 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3927 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3929 clock-names = "pcnoc-sway-clk", "audio-core",
3930 "mclk0", "pcnoc-mport-clk",
3931 "mi2s-bit-clk0", "mi2s-bit-clk1";
3934 #sound-dai-cells = <1>;
3935 #address-cells = <1>;
3936 #size-cells = <0>;
3940 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3943 lpass_hm: clock-controller@63000000 {
3944 compatible = "qcom,sc7180-lpasshm";
3948 clock-names = "iface", "bi_tcxo";
3949 power-domains = <&rpmhpd SC7180_CX>;
3951 #clock-cells = <1>;
3952 #power-domain-cells = <1>;
3958 thermal-zones {
3959 cpu0_thermal: cpu0-thermal {
3960 polling-delay-passive = <250>;
3961 polling-delay = <0>;
3963 thermal-sensors = <&tsens0 1>;
3964 sustainable-power = <1052>;
3967 cpu0_alert0: trip-point0 {
3973 cpu0_alert1: trip-point1 {
3979 cpu0_crit: cpu-crit {
3986 cooling-maps {
3989 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4008 cpu1_thermal: cpu1-thermal {
4009 polling-delay-passive = <250>;
4010 polling-delay = <0>;
4012 thermal-sensors = <&tsens0 2>;
4013 sustainable-power = <1052>;
4016 cpu1_alert0: trip-point0 {
4022 cpu1_alert1: trip-point1 {
4028 cpu1_crit: cpu-crit {
4035 cooling-maps {
4038 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4047 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4057 cpu2_thermal: cpu2-thermal {
4058 polling-delay-passive = <250>;
4059 polling-delay = <0>;
4061 thermal-sensors = <&tsens0 3>;
4062 sustainable-power = <1052>;
4065 cpu2_alert0: trip-point0 {
4071 cpu2_alert1: trip-point1 {
4077 cpu2_crit: cpu-crit {
4084 cooling-maps {
4087 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4096 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4106 cpu3_thermal: cpu3-thermal {
4107 polling-delay-passive = <250>;
4108 polling-delay = <0>;
4110 thermal-sensors = <&tsens0 4>;
4111 sustainable-power = <1052>;
4114 cpu3_alert0: trip-point0 {
4120 cpu3_alert1: trip-point1 {
4126 cpu3_crit: cpu-crit {
4133 cooling-maps {
4136 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4145 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4155 cpu4_thermal: cpu4-thermal {
4156 polling-delay-passive = <250>;
4157 polling-delay = <0>;
4159 thermal-sensors = <&tsens0 5>;
4160 sustainable-power = <1052>;
4163 cpu4_alert0: trip-point0 {
4169 cpu4_alert1: trip-point1 {
4175 cpu4_crit: cpu-crit {
4182 cooling-maps {
4185 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4194 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4204 cpu5_thermal: cpu5-thermal {
4205 polling-delay-passive = <250>;
4206 polling-delay = <0>;
4208 thermal-sensors = <&tsens0 6>;
4209 sustainable-power = <1052>;
4212 cpu5_alert0: trip-point0 {
4218 cpu5_alert1: trip-point1 {
4224 cpu5_crit: cpu-crit {
4231 cooling-maps {
4234 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4243 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4253 cpu6_thermal: cpu6-thermal {
4254 polling-delay-passive = <250>;
4255 polling-delay = <0>;
4257 thermal-sensors = <&tsens0 9>;
4258 sustainable-power = <1425>;
4261 cpu6_alert0: trip-point0 {
4267 cpu6_alert1: trip-point1 {
4273 cpu6_crit: cpu-crit {
4280 cooling-maps {
4283 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4288 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4294 cpu7_thermal: cpu7-thermal {
4295 polling-delay-passive = <250>;
4296 polling-delay = <0>;
4298 thermal-sensors = <&tsens0 10>;
4299 sustainable-power = <1425>;
4302 cpu7_alert0: trip-point0 {
4308 cpu7_alert1: trip-point1 {
4314 cpu7_crit: cpu-crit {
4321 cooling-maps {
4324 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4329 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4335 cpu8_thermal: cpu8-thermal {
4336 polling-delay-passive = <250>;
4337 polling-delay = <0>;
4339 thermal-sensors = <&tsens0 11>;
4340 sustainable-power = <1425>;
4343 cpu8_alert0: trip-point0 {
4349 cpu8_alert1: trip-point1 {
4355 cpu8_crit: cpu-crit {
4362 cooling-maps {
4365 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4370 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4376 cpu9_thermal: cpu9-thermal {
4377 polling-delay-passive = <250>;
4378 polling-delay = <0>;
4380 thermal-sensors = <&tsens0 12>;
4381 sustainable-power = <1425>;
4384 cpu9_alert0: trip-point0 {
4390 cpu9_alert1: trip-point1 {
4396 cpu9_crit: cpu-crit {
4403 cooling-maps {
4406 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4411 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4417 aoss0-thermal {
4418 polling-delay-passive = <250>;
4419 polling-delay = <0>;
4421 thermal-sensors = <&tsens0 0>;
4424 aoss0_alert0: trip-point0 {
4430 aoss0_crit: aoss0-crit {
4438 cpuss0-thermal {
4439 polling-delay-passive = <250>;
4440 polling-delay = <0>;
4442 thermal-sensors = <&tsens0 7>;
4445 cpuss0_alert0: trip-point0 {
4450 cpuss0_crit: cluster0-crit {
4458 cpuss1-thermal {
4459 polling-delay-passive = <250>;
4460 polling-delay = <0>;
4462 thermal-sensors = <&tsens0 8>;
4465 cpuss1_alert0: trip-point0 {
4470 cpuss1_crit: cluster0-crit {
4478 gpuss0-thermal {
4479 polling-delay-passive = <250>;
4480 polling-delay = <0>;
4482 thermal-sensors = <&tsens0 13>;
4485 gpuss0_alert0: trip-point0 {
4491 gpuss0_crit: gpuss0-crit {
4498 cooling-maps {
4501 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4506 gpuss1-thermal {
4507 polling-delay-passive = <250>;
4508 polling-delay = <0>;
4510 thermal-sensors = <&tsens0 14>;
4513 gpuss1_alert0: trip-point0 {
4519 gpuss1_crit: gpuss1-crit {
4526 cooling-maps {
4529 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4534 aoss1-thermal {
4535 polling-delay-passive = <250>;
4536 polling-delay = <0>;
4538 thermal-sensors = <&tsens1 0>;
4541 aoss1_alert0: trip-point0 {
4547 aoss1_crit: aoss1-crit {
4555 cwlan-thermal {
4556 polling-delay-passive = <250>;
4557 polling-delay = <0>;
4559 thermal-sensors = <&tsens1 1>;
4562 cwlan_alert0: trip-point0 {
4568 cwlan_crit: cwlan-crit {
4576 audio-thermal {
4577 polling-delay-passive = <250>;
4578 polling-delay = <0>;
4580 thermal-sensors = <&tsens1 2>;
4583 audio_alert0: trip-point0 {
4589 audio_crit: audio-crit {
4597 ddr-thermal {
4598 polling-delay-passive = <250>;
4599 polling-delay = <0>;
4601 thermal-sensors = <&tsens1 3>;
4604 ddr_alert0: trip-point0 {
4610 ddr_crit: ddr-crit {
4618 q6-hvx-thermal {
4619 polling-delay-passive = <250>;
4620 polling-delay = <0>;
4622 thermal-sensors = <&tsens1 4>;
4625 q6_hvx_alert0: trip-point0 {
4631 q6_hvx_crit: q6-hvx-crit {
4639 camera-thermal {
4640 polling-delay-passive = <250>;
4641 polling-delay = <0>;
4643 thermal-sensors = <&tsens1 5>;
4646 camera_alert0: trip-point0 {
4652 camera_crit: camera-crit {
4660 mdm-core-thermal {
4661 polling-delay-passive = <250>;
4662 polling-delay = <0>;
4664 thermal-sensors = <&tsens1 6>;
4667 mdm_alert0: trip-point0 {
4673 mdm_crit: mdm-crit {
4681 mdm-dsp-thermal {
4682 polling-delay-passive = <250>;
4683 polling-delay = <0>;
4685 thermal-sensors = <&tsens1 7>;
4688 mdm_dsp_alert0: trip-point0 {
4694 mdm_dsp_crit: mdm-dsp-crit {
4702 npu-thermal {
4703 polling-delay-passive = <250>;
4704 polling-delay = <0>;
4706 thermal-sensors = <&tsens1 8>;
4709 npu_alert0: trip-point0 {
4715 npu_crit: npu-crit {
4723 video-thermal {
4724 polling-delay-passive = <250>;
4725 polling-delay = <0>;
4727 thermal-sensors = <&tsens1 9>;
4730 video_alert0: trip-point0 {
4736 video_crit: video-crit {
4746 compatible = "arm,armv8-timer";