Lines Matching +full:0 +full:x0c600000
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
136 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw 0>;
148 qcom,freq-domain = <&cpufreq_hw 0>;
160 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw 0>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
184 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw 0>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
208 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw 0>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
232 reg = <0x0 0x600>;
256 reg = <0x0 0x700>;
316 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
319 arm,psci-suspend-param = <0x40000003>;
326 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
329 arm,psci-suspend-param = <0x40000004>;
336 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 arm,psci-suspend-param = <0x40000003>;
349 arm,psci-suspend-param = <0x40000004>;
358 CLUSTER_SLEEP_PC: cluster-sleep-0 {
361 arm,psci-suspend-param = <0x41000044>;
370 arm,psci-suspend-param = <0x41001244>;
379 arm,psci-suspend-param = <0x4100b244>;
396 reg = <0 0x80000000 0 0>;
587 #power-domain-cells = <0>;
593 #power-domain-cells = <0>;
599 #power-domain-cells = <0>;
605 #power-domain-cells = <0>;
611 #power-domain-cells = <0>;
617 #power-domain-cells = <0>;
623 #power-domain-cells = <0>;
629 #power-domain-cells = <0>;
635 #power-domain-cells = <0>;
648 reg = <0x0 0x80000000 0x0 0x600000>;
653 reg = <0x0 0x80600000 0x0 0x200000>;
658 reg = <0x0 0x80800000 0x0 0x20000>;
663 reg = <0x0 0x80820000 0x0 0x20000>;
669 reg = <0x0 0x808ff000 0x0 0x1000>;
674 reg = <0x0 0x80900000 0x0 0x200000>;
679 reg = <0x0 0x80b00000 0x0 0x3900000>;
684 reg = <0 0x8b700000 0 0x10000>;
690 reg = <0x0 0x94600000 0x0 0x200000>;
712 qcom,local-pid = <0>;
736 qcom,local-pid = <0>;
757 qcom,local-pid = <0>;
783 soc: soc@0 {
786 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>;
792 reg = <0 0x00100000 0 0x1f0000>;
805 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 0x1fff>;
816 reg = <0x25b 0x1>;
821 reg = <0x1d2 0x2>;
828 reg = <0 0x007c4000 0 0x1000>,
829 <0 0x007c5000 0 0x1000>;
832 iommus = <&apps_smmu 0x60 0x0>;
841 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
865 opp-avg-kBps = <100000 0>;
872 opp-avg-kBps = <390000 0>;
879 reg = <0 0x008c0000 0 0x6000>;
886 iommus = <&apps_smmu 0x43 0x0>;
891 reg = <0 0x00880000 0 0x4000>;
895 pinctrl-0 = <&qup_i2c0_default>;
898 #size-cells = <0>;
899 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
911 reg = <0 0x00880000 0 0x4000>;
915 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
918 #size-cells = <0>;
921 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
929 reg = <0 0x00880000 0 0x4000>;
933 pinctrl-0 = <&qup_uart0_default>;
937 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
945 reg = <0 0x00884000 0 0x4000>;
949 pinctrl-0 = <&qup_i2c1_default>;
952 #size-cells = <0>;
953 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
965 reg = <0 0x00884000 0 0x4000>;
969 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
972 #size-cells = <0>;
975 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
983 reg = <0 0x00884000 0 0x4000>;
987 pinctrl-0 = <&qup_uart1_default>;
991 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
999 reg = <0 0x00888000 0 0x4000>;
1003 pinctrl-0 = <&qup_i2c2_default>;
1006 #size-cells = <0>;
1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1019 reg = <0 0x00888000 0 0x4000>;
1023 pinctrl-0 = <&qup_uart2_default>;
1027 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1035 reg = <0 0x0088c000 0 0x4000>;
1039 pinctrl-0 = <&qup_i2c3_default>;
1042 #size-cells = <0>;
1043 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1055 reg = <0 0x0088c000 0 0x4000>;
1059 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1062 #size-cells = <0>;
1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1073 reg = <0 0x0088c000 0 0x4000>;
1077 pinctrl-0 = <&qup_uart3_default>;
1081 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1089 reg = <0 0x00890000 0 0x4000>;
1093 pinctrl-0 = <&qup_i2c4_default>;
1096 #size-cells = <0>;
1097 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1109 reg = <0 0x00890000 0 0x4000>;
1113 pinctrl-0 = <&qup_uart4_default>;
1117 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1125 reg = <0 0x00894000 0 0x4000>;
1129 pinctrl-0 = <&qup_i2c5_default>;
1132 #size-cells = <0>;
1133 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1145 reg = <0 0x00894000 0 0x4000>;
1149 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1152 #size-cells = <0>;
1155 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1163 reg = <0 0x00894000 0 0x4000>;
1167 pinctrl-0 = <&qup_uart5_default>;
1171 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1180 reg = <0 0x00ac0000 0 0x6000>;
1187 iommus = <&apps_smmu 0x4c3 0x0>;
1192 reg = <0 0x00a80000 0 0x4000>;
1196 pinctrl-0 = <&qup_i2c6_default>;
1199 #size-cells = <0>;
1200 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1212 reg = <0 0x00a80000 0 0x4000>;
1216 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1219 #size-cells = <0>;
1222 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1230 reg = <0 0x00a80000 0 0x4000>;
1234 pinctrl-0 = <&qup_uart6_default>;
1238 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1246 reg = <0 0x00a84000 0 0x4000>;
1250 pinctrl-0 = <&qup_i2c7_default>;
1253 #size-cells = <0>;
1254 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1266 reg = <0 0x00a84000 0 0x4000>;
1270 pinctrl-0 = <&qup_uart7_default>;
1274 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1282 reg = <0 0x00a88000 0 0x4000>;
1286 pinctrl-0 = <&qup_i2c8_default>;
1289 #size-cells = <0>;
1290 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1302 reg = <0 0x00a88000 0 0x4000>;
1306 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1309 #size-cells = <0>;
1312 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1320 reg = <0 0x00a88000 0 0x4000>;
1324 pinctrl-0 = <&qup_uart8_default>;
1328 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1336 reg = <0 0x00a8c000 0 0x4000>;
1340 pinctrl-0 = <&qup_i2c9_default>;
1343 #size-cells = <0>;
1344 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1356 reg = <0 0x00a8c000 0 0x4000>;
1360 pinctrl-0 = <&qup_uart9_default>;
1364 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1372 reg = <0 0x00a90000 0 0x4000>;
1376 pinctrl-0 = <&qup_i2c10_default>;
1379 #size-cells = <0>;
1380 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1392 reg = <0 0x00a90000 0 0x4000>;
1396 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1399 #size-cells = <0>;
1402 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1410 reg = <0 0x00a90000 0 0x4000>;
1414 pinctrl-0 = <&qup_uart10_default>;
1418 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1426 reg = <0 0x00a94000 0 0x4000>;
1430 pinctrl-0 = <&qup_i2c11_default>;
1433 #size-cells = <0>;
1434 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1446 reg = <0 0x00a94000 0 0x4000>;
1450 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1453 #size-cells = <0>;
1456 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1464 reg = <0 0x00a94000 0 0x4000>;
1468 pinctrl-0 = <&qup_uart11_default>;
1472 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1481 reg = <0 0x01500000 0 0x28000>;
1488 reg = <0 0x01620000 0 0x17080>;
1495 reg = <0 0x01638000 0 0x1000>;
1502 reg = <0 0x01650000 0 0x1000>;
1509 reg = <0 0x016e0000 0 0x15080>;
1516 reg = <0 0x01705000 0 0x9000>;
1523 reg = <0 0x0170e000 0 0x6000>;
1530 reg = <0 0x01740000 0 0x1c100>;
1538 iommus = <&apps_smmu 0x440 0x0>,
1539 <&apps_smmu 0x442 0x0>;
1540 reg = <0 0x01e40000 0 0x7000>,
1541 <0 0x01e47000 0 0x2000>,
1542 <0 0x01e04000 0 0x2c000>;
1549 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1559 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1560 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1561 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1568 qcom,smem-states = <&ipa_smp2p_out 0>,
1578 reg = <0 0x01f40000 0 0x20000>;
1584 reg = <0 0x01f60000 0 0x20000>;
1589 reg = <0 0x01fc0000 0 0x40000>;
1594 reg = <0 0x03500000 0 0x300000>,
1595 <0 0x03900000 0 0x300000>,
1596 <0 0x03d00000 0 0x300000>;
1603 gpio-ranges = <&tlmm 0 0 120>;
2058 reg = <0 0x04080000 0 0x4040>;
2061 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2081 qcom,smem-states = <&modem_smp2p_out 0>;
2096 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2097 <0 0x05061000 0 0x800>;
2100 iommus = <&adreno_smmu 0>;
2109 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2119 opp-supported-hw = <0x04>;
2126 opp-supported-hw = <0x07>;
2133 opp-supported-hw = <0x07>;
2140 opp-supported-hw = <0x07>;
2147 opp-supported-hw = <0x07>;
2154 opp-supported-hw = <0x07>;
2161 opp-supported-hw = <0x07>;
2168 opp-supported-hw = <0x07>;
2175 reg = <0 0x05040000 0 0x10000>;
2198 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2199 <0 0x0b490000 0 0x10000>;
2226 reg = <0 0x05090000 0 0x9000>;
2240 reg = <0x0 0x010a2000 0x0 0x1000>,
2241 <0x0 0x010ae000 0x0 0x2000>;
2246 reg = <0 0x06002000 0 0x1000>,
2247 <0 0x16280000 0 0x180000>;
2264 reg = <0 0x06041000 0 0x1000>;
2279 #size-cells = <0>;
2292 reg = <0 0x06042000 0 0x1000>;
2307 #size-cells = <0>;
2320 reg = <0 0x06045000 0 0x1000>;
2335 #size-cells = <0>;
2337 port@0 {
2338 reg = <0>;
2355 reg = <0 0x06046000 0 0x1000>;
2379 reg = <0 0x06048000 0 0x1000>;
2380 iommus = <&apps_smmu 0x04a0 0x20>;
2397 reg = <0 0x06b04000 0 0x1000>;
2412 #size-cells = <0>;
2425 reg = <0 0x06b05000 0 0x1000>;
2449 reg = <0 0x06b06000 0 0x1000>;
2474 reg = <0 0x07040000 0 0x1000>;
2494 reg = <0 0x07140000 0 0x1000>;
2514 reg = <0 0x07240000 0 0x1000>;
2534 reg = <0 0x07340000 0 0x1000>;
2554 reg = <0 0x07440000 0 0x1000>;
2574 reg = <0 0x07540000 0 0x1000>;
2594 reg = <0 0x07640000 0 0x1000>;
2614 reg = <0 0x07740000 0 0x1000>;
2634 reg = <0 0x07800000 0 0x1000>;
2649 #size-cells = <0>;
2651 port@0 {
2652 reg = <0>;
2711 reg = <0 0x07810000 0 0x1000>;
2735 reg = <0 0x08804000 0 0x1000>;
2737 iommus = <&apps_smmu 0x80 0>;
2747 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2748 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2764 opp-avg-kBps = <100000 0>;
2771 opp-avg-kBps = <200000 0>;
2778 reg = <0 0x088dc000 0 0x600>;
2779 iommus = <&apps_smmu 0x20 0x0>;
2781 #size-cells = <0>;
2786 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2787 &config_noc SLAVE_QSPI_0 0>;
2796 reg = <0 0x088e3000 0 0x400>;
2798 #phy-cells = <0>;
2809 reg = <0 0x088e8000 0 0x3000>;
2833 reg = <0 0x090b6300 0 0x600>;
2843 opp-0 {
2871 reg = <0 0x090cd000 0 0x1000>;
2881 opp-0 {
2917 reg = <0 0x09160000 0 0x03200>;
2924 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2931 reg = <0 0x09680000 0 0x3e200>;
2938 reg = <0 0x09990000 0 0x1600>;
2945 reg = <0 0x0a6f8800 0 0x400>;
2979 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2980 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2987 reg = <0 0x0a600000 0 0xe000>;
2989 iommus = <&apps_smmu 0x540 0>;
3000 reg = <0 0x0aa00000 0 0xff000>;
3014 iommus = <&apps_smmu 0x0c00 0x60>;
3016 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3060 reg = <0 0x0ab00000 0 0x10000>;
3070 reg = <0 0x0ac00000 0 0x1000>;
3077 reg = <0 0x0ad00000 0 0x10000>;
3089 reg = <0 0x0ae00000 0 0x1000>;
3110 iommus = <&apps_smmu 0x800 0x2>;
3120 reg = <0 0x0ae01000 0 0x8f000>,
3121 <0 0x0aeb0000 0 0x2008>;
3142 interrupts = <0>;
3146 #size-cells = <0>;
3148 port@0 {
3149 reg = <0>;
3191 reg = <0 0x0ae94000 0 0x400>;
3211 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3219 #size-cells = <0>;
3225 #size-cells = <0>;
3227 port@0 {
3228 reg = <0>;
3263 reg = <0 0x0ae94400 0 0x200>,
3264 <0 0x0ae94600 0 0x280>,
3265 <0 0x0ae94a00 0 0x1e0>;
3271 #phy-cells = <0>;
3284 reg = <0 0x0ae90000 0 0x200>,
3285 <0 0x0ae90200 0 0x200>,
3286 <0 0x0ae90400 0 0xc00>,
3287 <0 0x0ae91000 0 0x400>,
3288 <0 0x0ae91400 0 0x400>;
3310 #sound-dai-cells = <0>;
3314 #size-cells = <0>;
3315 port@0 {
3316 reg = <0>;
3356 reg = <0 0x0af00000 0 0x200000>;
3359 <&mdss_dsi0_phy 0>,
3376 reg = <0 0x0b220000 0 0x30000>;
3377 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3385 reg = <0 0x0b2e0000 0 0x20000>;
3391 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3392 <0 0x0c222000 0 0x1ff>; /* SROT */
3402 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3403 <0 0x0c223000 0 0x1ff>; /* SROT */
3413 reg = <0 0x0c2a0000 0 0x31000>;
3419 reg = <0 0x0c300000 0 0x400>;
3421 mboxes = <&apss_shared 0>;
3423 #clock-cells = <0>;
3428 reg = <0 0x0c3f0000 0 0x400>;
3433 reg = <0 0x0c440000 0 0x1100>,
3434 <0 0x0c600000 0 0x2000000>,
3435 <0 0x0e600000 0 0x100000>,
3436 <0 0x0e700000 0 0xa0000>,
3437 <0 0x0c40a000 0 0x26000>;
3441 qcom,ee = <0>;
3442 qcom,channel = <0>;
3444 #size-cells = <0>;
3451 reg = <0 0x146aa000 0 0x2000>;
3456 ranges = <0 0 0x146aa000 0x2000>;
3460 reg = <0x94c 0xc8>;
3466 reg = <0 0x15000000 0 0x100000>;
3559 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3560 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3567 reg = <0 0x17a40000 0 0x20000>;
3575 reg = <0 0x17c00000 0 0x10000>;
3581 reg = <0 0x17c10000 0 0x1000>;
3583 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3589 ranges = <0 0 0 0x20000000>;
3591 reg = <0 0x17c20000 0 0x1000>;
3594 frame-number = <0>;
3597 reg = <0x17c21000 0x1000>,
3598 <0x17c22000 0x1000>;
3604 reg = <0x17c23000 0x1000>;
3611 reg = <0x17c25000 0x1000>;
3618 reg = <0x17c27000 0x1000>;
3625 reg = <0x17c29000 0x1000>;
3632 reg = <0x17c2b000 0x1000>;
3639 reg = <0x17c2d000 0x1000>;
3646 reg = <0 0x18200000 0 0x10000>,
3647 <0 0x18210000 0 0x10000>,
3648 <0 0x18220000 0 0x10000>;
3649 reg-names = "drv-0", "drv-1", "drv-2";
3653 qcom,tcs-offset = <0xd00>;
3729 reg = <0 0x18321000 0 0x1400>;
3739 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3751 reg = <0 0x18800000 0 0x800000>;
3753 iommus = <&apps_smmu 0xc0 0x1>;
3774 reg = <0 0x62400000 0 0x100>;
3777 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3795 qcom,smem-states = <&adsp_smp2p_out 0>;
3811 #size-cells = <0>;
3827 #size-cells = <0>;
3845 #size-cells = <0>;
3847 iommus = <&apps_smmu 0x1001 0x0>;
3858 #sound-dai-cells = <0>;
3868 #size-cells = <0>;
3873 iommus = <&apps_smmu 0x1003 0x0>;
3879 iommus = <&apps_smmu 0x1004 0x0>;
3885 iommus = <&apps_smmu 0x1005 0x0>;
3894 reg = <0 0x62d00000 0 0x50000>,
3895 <0 0x62780000 0 0x30000>;
3910 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3913 iommus = <&apps_smmu 0x1020 0>,
3914 <&apps_smmu 0x1021 0>,
3915 <&apps_smmu 0x1032 0>;
3936 #size-cells = <0>;
3945 reg = <0 0x63000000 0 0x28>;
3961 polling-delay = <0>;
4010 polling-delay = <0>;
4059 polling-delay = <0>;
4108 polling-delay = <0>;
4157 polling-delay = <0>;
4206 polling-delay = <0>;
4255 polling-delay = <0>;
4296 polling-delay = <0>;
4337 polling-delay = <0>;
4378 polling-delay = <0>;
4419 polling-delay = <0>;
4421 thermal-sensors = <&tsens0 0>;
4440 polling-delay = <0>;
4460 polling-delay = <0>;
4480 polling-delay = <0>;
4508 polling-delay = <0>;
4536 polling-delay = <0>;
4538 thermal-sensors = <&tsens1 0>;
4557 polling-delay = <0>;
4578 polling-delay = <0>;
4599 polling-delay = <0>;
4620 polling-delay = <0>;
4641 polling-delay = <0>;
4662 polling-delay = <0>;
4683 polling-delay = <0>;
4704 polling-delay = <0>;
4725 polling-delay = <0>;
4750 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;