Lines Matching +full:data +full:- +full:pins
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a55";
31 enable-method = "psci";
32 power-domains = <&CPU_PD0>;
33 power-domain-names = "psci";
34 qcom,freq-domains = <&cpufreq_hw 0>;
35 next-level-cache = <&L2_0>;
36 L2_0: l2-cache {
38 cache-level = <2>;
39 cache-unified;
40 next-level-cache = <&L3_0>;
41 L3_0: l3-cache {
43 cache-level = <3>;
44 cache-unified;
51 compatible = "arm,cortex-a55";
54 enable-method = "psci";
55 power-domains = <&CPU_PD1>;
56 power-domain-names = "psci";
57 qcom,freq-domains = <&cpufreq_hw 0>;
58 next-level-cache = <&L2_100>;
59 L2_100: l2-cache {
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
69 compatible = "arm,cortex-a55";
72 enable-method = "psci";
73 power-domains = <&CPU_PD2>;
74 power-domain-names = "psci";
75 qcom,freq-domains = <&cpufreq_hw 0>;
76 next-level-cache = <&L2_200>;
77 L2_200: l2-cache {
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&L3_0>;
87 compatible = "arm,cortex-a55";
90 enable-method = "psci";
91 power-domains = <&CPU_PD3>;
92 power-domain-names = "psci";
93 qcom,freq-domains = <&cpufreq_hw 0>;
94 next-level-cache = <&L2_300>;
95 L2_300: l2-cache {
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
103 cpu-map {
124 idle-states {
125 entry-method = "psci";
127 CPU_OFF: cpu-sleep-0 {
128 compatible = "arm,idle-state";
129 entry-latency-us = <274>;
130 exit-latency-us = <480>;
131 min-residency-us = <3934>;
132 arm,psci-suspend-param = <0x40000004>;
133 local-timer-stop;
137 domain-idle-states {
138 CLUSTER_SLEEP_0: cluster-sleep-0 {
139 compatible = "domain-idle-state";
140 entry-latency-us = <584>;
141 exit-latency-us = <2332>;
142 min-residency-us = <6118>;
143 arm,psci-suspend-param = <0x41000044>;
146 CLUSTER_SLEEP_1: cluster-sleep-1 {
147 compatible = "domain-idle-state";
148 entry-latency-us = <2893>;
149 exit-latency-us = <4023>;
150 min-residency-us = <9987>;
151 arm,psci-suspend-param = <0x41003344>;
157 compatible = "qcom,scm-qdu1000", "qcom,scm";
161 mc_virt: interconnect-0 {
162 compatible = "qcom,qdu1000-mc-virt";
163 qcom,bcm-voters = <&apps_bcm_voter>;
164 #interconnect-cells = <2>;
167 clk_virt: interconnect-1 {
168 compatible = "qcom,qdu1000-clk-virt";
169 qcom,bcm-voters = <&apps_bcm_voter>;
170 #interconnect-cells = <2>;
180 compatible = "arm,armv8-pmuv3";
185 compatible = "arm,psci-1.0";
188 CPU_PD0: power-domain-cpu0 {
189 #power-domain-cells = <0>;
190 power-domains = <&CLUSTER_PD>;
191 domain-idle-states = <&CPU_OFF>;
194 CPU_PD1: power-domain-cpu1 {
195 #power-domain-cells = <0>;
196 power-domains = <&CLUSTER_PD>;
197 domain-idle-states = <&CPU_OFF>;
200 CPU_PD2: power-domain-cpu2 {
201 #power-domain-cells = <0>;
202 power-domains = <&CLUSTER_PD>;
203 domain-idle-states = <&CPU_OFF>;
206 CPU_PD3: power-domain-cpu3 {
207 #power-domain-cells = <0>;
208 power-domains = <&CLUSTER_PD>;
209 domain-idle-states = <&CPU_OFF>;
212 CLUSTER_PD: power-domain-cluster {
213 #power-domain-cells = <0>;
214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
218 reserved_memory: reserved-memory {
219 #address-cells = <2>;
220 #size-cells = <2>;
225 no-map;
228 xbl_dt_log_mem: xbl-dt-log@80600000 {
230 no-map;
233 xbl_ramdump_mem: xbl-ramdump@80640000 {
235 no-map;
238 aop_image_mem: aop-image@80800000 {
240 no-map;
243 aop_cmd_db_mem: aop-cmd-db@80860000 {
244 compatible = "qcom,cmd-db";
246 no-map;
249 aop_config_mem: aop-config@80880000 {
251 no-map;
254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
256 no-map;
259 tme_log_mem: tme-log@808e0000 {
261 no-map;
264 uefi_log_mem: uefi-log@808e4000 {
266 no-map;
272 no-map;
276 cpucp_fw_mem: cpucp-fw@80b00000 {
278 no-map;
283 no-map;
286 tz_stat_mem: tz-stat@81d00000 {
288 no-map;
293 no-map;
298 no-map;
303 no-map;
308 no-map;
313 no-map;
318 no-map;
323 ipa_fw_mem: ipa-fw@8be00000 {
325 no-map;
328 ipa_gsi_mem: ipa-gsi@8be10000 {
330 no-map;
335 no-map;
338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
340 no-map;
345 no-map;
348 oem_tenx_mem: oem-tenx@b9600000 {
350 no-map;
353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
355 no-map;
358 ipa_buffer_mem: ipa-buffer@c3200000 {
360 no-map;
365 compatible = "simple-bus";
366 #address-cells = <2>;
367 #size-cells = <2>;
369 dma-ranges = <0 0 0 0 0x10 0>;
371 gcc: clock-controller@80000 {
372 compatible = "qcom,qdu1000-gcc";
379 #clock-cells = <1>;
380 #reset-cells = <1>;
381 #power-domain-cells = <1>;
384 ecpricc: clock-controller@280000 {
385 compatible = "qcom,qdu1000-ecpricc";
394 #clock-cells = <1>;
395 #reset-cells = <1>;
398 gpi_dma0: dma-controller@900000 {
399 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
413 dma-channels = <12>;
414 dma-channel-mask = <0x3f>;
416 #dma-cells = <3>;
420 compatible = "qcom,geni-se-qup";
424 clock-names = "m-ahb", "s-ahb";
428 interconnect-names = "qup-core";
430 #address-cells = <2>;
431 #size-cells = <2>;
436 compatible = "qcom,geni-uart";
439 clock-names = "se";
440 pinctrl-0 = <&qup_uart0_default>;
441 pinctrl-names = "default";
447 compatible = "qcom,geni-i2c";
450 clock-names = "se";
452 pinctrl-0 = <&qup_i2c1_data_clk>;
453 pinctrl-names = "default";
454 #address-cells = <1>;
455 #size-cells = <0>;
460 compatible = "qcom,geni-spi";
462 #address-cells = <1>;
463 #size-cells = <0>;
466 clock-names = "se";
467 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
468 pinctrl-names = "default";
473 compatible = "qcom,geni-i2c";
476 clock-names = "se";
478 pinctrl-0 = <&qup_i2c2_data_clk>;
479 pinctrl-names = "default";
480 #address-cells = <1>;
481 #size-cells = <0>;
486 compatible = "qcom,geni-spi";
488 #address-cells = <1>;
489 #size-cells = <0>;
492 clock-names = "se";
493 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
494 pinctrl-names = "default";
499 compatible = "qcom,geni-i2c";
502 clock-names = "se";
504 pinctrl-0 = <&qup_i2c3_data_clk>;
505 pinctrl-names = "default";
506 #address-cells = <1>;
507 #size-cells = <0>;
512 compatible = "qcom,geni-spi";
514 #address-cells = <1>;
515 #size-cells = <0>;
518 clock-names = "se";
519 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
520 pinctrl-names = "default";
525 compatible = "qcom,geni-i2c";
528 clock-names = "se";
530 pinctrl-0 = <&qup_i2c4_data_clk>;
531 pinctrl-names = "default";
532 #address-cells = <1>;
533 #size-cells = <0>;
538 compatible = "qcom,geni-spi";
540 #address-cells = <1>;
541 #size-cells = <0>;
544 clock-names = "se";
545 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
546 pinctrl-names = "default";
551 compatible = "qcom,geni-i2c";
554 clock-names = "se";
556 pinctrl-0 = <&qup_i2c5_data_clk>;
557 pinctrl-names = "default";
558 #address-cells = <1>;
559 #size-cells = <0>;
564 compatible = "qcom,geni-spi";
566 #address-cells = <1>;
567 #size-cells = <0>;
570 clock-names = "se";
571 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
572 pinctrl-names = "default";
577 compatible = "qcom,geni-i2c";
580 clock-names = "se";
582 pinctrl-0 = <&qup_i2c6_data_clk>;
583 pinctrl-names = "default";
584 #address-cells = <1>;
585 #size-cells = <0>;
590 compatible = "qcom,geni-spi";
592 #address-cells = <1>;
593 #size-cells = <0>;
596 clock-names = "se";
597 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
598 pinctrl-names = "default";
603 compatible = "qcom,geni-debug-uart";
606 clock-names = "se";
607 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
608 pinctrl-names = "default";
614 gpi_dma1: dma-controller@a00000 {
615 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
629 dma-channels = <12>;
630 dma-channel-mask = <0x3f>;
632 #dma-cells = <3>;
636 compatible = "qcom,geni-se-qup";
640 clock-names = "m-ahb", "s-ahb";
642 #address-cells = <2>;
643 #size-cells = <2>;
648 compatible = "qcom,geni-uart";
651 clock-names = "se";
652 pinctrl-0 = <&qup_uart8_default>;
653 pinctrl-names = "default";
655 #address-cells = <1>;
656 #size-cells = <0>;
661 compatible = "qcom,geni-i2c";
664 clock-names = "se";
666 pinctrl-0 = <&qup_i2c9_data_clk>;
667 pinctrl-names = "default";
668 #address-cells = <1>;
669 #size-cells = <0>;
674 compatible = "qcom,geni-spi";
676 #address-cells = <1>;
677 #size-cells = <0>;
680 clock-names = "se";
681 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
682 pinctrl-names = "default";
687 compatible = "qcom,geni-i2c";
690 clock-names = "se";
692 pinctrl-0 = <&qup_i2c10_data_clk>;
693 pinctrl-names = "default";
694 #address-cells = <1>;
695 #size-cells = <0>;
700 compatible = "qcom,geni-spi";
702 #address-cells = <1>;
703 #size-cells = <0>;
706 clock-names = "se";
707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
708 pinctrl-names = "default";
713 compatible = "qcom,geni-i2c";
716 clock-names = "se";
718 pinctrl-0 = <&qup_i2c11_data_clk>;
719 pinctrl-names = "default";
720 #address-cells = <1>;
721 #size-cells = <0>;
726 compatible = "qcom,geni-spi";
728 #address-cells = <1>;
729 #size-cells = <0>;
732 clock-names = "se";
733 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
734 pinctrl-names = "default";
739 compatible = "qcom,geni-i2c";
742 clock-names = "se";
744 pinctrl-0 = <&qup_i2c12_data_clk>;
745 pinctrl-names = "default";
746 #address-cells = <1>;
747 #size-cells = <0>;
752 compatible = "qcom,geni-spi";
754 #address-cells = <1>;
755 #size-cells = <0>;
758 clock-names = "se";
759 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
760 pinctrl-names = "default";
765 compatible = "qcom,geni-i2c";
768 clock-names = "se";
770 pinctrl-0 = <&qup_i2c13_data_clk>;
771 pinctrl-names = "default";
772 #address-cells = <1>;
773 #size-cells = <0>;
778 compatible = "qcom,geni-uart";
781 clock-names = "se";
782 pinctrl-0 = <&qup_uart13_default>;
783 pinctrl-names = "default";
785 #address-cells = <1>;
786 #size-cells = <0>;
791 compatible = "qcom,geni-spi";
793 #address-cells = <1>;
794 #size-cells = <0>;
797 clock-names = "se";
798 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
799 pinctrl-names = "default";
804 compatible = "qcom,geni-i2c";
807 clock-names = "se";
809 pinctrl-0 = <&qup_i2c14_data_clk>;
810 pinctrl-names = "default";
811 #address-cells = <1>;
812 #size-cells = <0>;
817 compatible = "qcom,geni-spi";
819 #address-cells = <1>;
820 #size-cells = <0>;
823 clock-names = "se";
824 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
825 pinctrl-names = "default";
830 compatible = "qcom,geni-i2c";
833 clock-names = "se";
835 pinctrl-0 = <&qup_i2c15_data_clk>;
836 pinctrl-names = "default";
837 #address-cells = <1>;
838 #size-cells = <0>;
843 compatible = "qcom,geni-spi";
845 #address-cells = <1>;
846 #size-cells = <0>;
849 clock-names = "se";
850 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
851 pinctrl-names = "default";
857 compatible = "qcom,qdu1000-system-noc";
859 qcom,bcm-voters = <&apps_bcm_voter>;
860 #interconnect-cells = <2>;
864 compatible = "qcom,tcsr-mutex";
866 #hwlock-cells = <1>;
870 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
873 reg-names = "hc", "cqhci";
877 interrupt-names = "hc_irq", "pwr_irq";
882 clock-names = "iface",
890 interconnect-names = "sdhc-ddr", "cpu-sdhc";
891 power-domains = <&rpmhpd QDU1000_CX>;
892 operating-points-v2 = <&sdhc1_opp_table>;
895 dma-coherent;
897 bus-width = <8>;
899 qcom,dll-config = <0x0007642c>;
900 qcom,ddr-config = <0x80040868>;
904 sdhc1_opp_table: opp-table {
905 compatible = "operating-points-v2";
907 opp-384000000 {
908 opp-hz = /bits/ 64 <384000000>;
909 required-opps = <&rpmhpd_opp_nom>;
910 opp-peak-kBps = <6528000 1652800>;
911 opp-avg-kBps = <400000 0>;
916 pdc: interrupt-controller@b220000 {
917 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
919 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
921 #interrupt-cells = <2>;
922 interrupt-parent = <&intc>;
923 interrupt-controller;
927 compatible = "qcom,spmi-pmic-arb";
933 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
934 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-names = "periph_irq";
938 #address-cells = <2>;
939 #size-cells = <0>;
940 interrupt-controller;
941 #interrupt-cells = <4>;
945 compatible = "qcom,qdu1000-tlmm";
948 gpio-controller;
949 #gpio-cells = <2>;
950 interrupt-controller;
951 #interrupt-cells = <2>;
952 gpio-ranges = <&tlmm 0 0 151>;
953 wakeup-parent = <&pdc>;
955 qup_uart0_default: qup-uart0-default-state {
956 pins = "gpio6", "gpio7", "gpio8", "gpio9";
960 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
961 pins = "gpio10", "gpio11";
965 qup_spi1_data_clk: qup-spi1-data-clk-state {
966 pins = "gpio10", "gpio11", "gpio12";
970 qup_spi1_cs: qup-spi1-cs-state {
971 pins = "gpio13";
975 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
976 pins = "gpio12", "gpio13";
980 qup_spi2_data_clk: qup-spi2-data-clk-state {
981 pins = "gpio12", "gpio13", "gpio10";
985 qup_spi2_cs: qup-spi2-cs-state {
986 pins = "gpio11";
990 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
991 pins = "gpio14", "gpio15";
995 qup_spi3_data_clk: qup-spi3-data-clk-state {
996 pins = "gpio14", "gpio15", "gpio16";
1000 qup_spi3_cs: qup-spi3-cs-state {
1001 pins = "gpio17";
1005 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1006 pins = "gpio16", "gpio17";
1010 qup_spi4_data_clk: qup-spi4-data-clk-state {
1011 pins = "gpio16", "gpio17", "gpio14";
1015 qup_spi4_cs: qup-spi4-cs-state {
1016 pins = "gpio15";
1020 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1021 pins = "gpio130", "gpio131";
1025 qup_spi5_data_clk: qup-spi5-data-clk-state {
1026 pins = "gpio130", "gpio131", "gpio132";
1030 qup_spi5_cs: qup-spi5-cs-state {
1031 pins = "gpio133";
1035 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1036 pins = "gpio132", "gpio133";
1040 qup_spi6_data_clk: qup-spi6-data-clk-state {
1041 pins = "gpio132", "gpio133", "gpio130";
1045 qup_spi6_cs: qup-spi6-cs-state {
1046 pins = "gpio131";
1050 qup_uart7_rx: qup-uart7-rx-state {
1051 pins = "gpio135";
1055 qup_uart7_tx: qup-uart7-tx-state {
1056 pins = "gpio134";
1060 qup_uart8_default: qup-uart8-default-state {
1061 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1065 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1066 pins = "gpio22", "gpio23";
1070 qup_spi9_data_clk: qup-spi9-data-clk-state {
1071 pins = "gpio22", "gpio23", "gpio24";
1075 qup_spi9_cs: qup-spi9-cs-state {
1076 pins = "gpio25";
1080 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1081 pins = "gpio24", "gpio25";
1085 qup_spi10_data_clk: qup-spi10-data-clk-state {
1086 pins = "gpio24", "gpio25", "gpio22";
1090 qup_spi10_cs: qup-spi10-cs-state {
1091 pins = "gpio23";
1095 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1096 pins = "gpio26", "gpio27";
1100 qup_spi11_data_clk: qup-spi11-data-clk-state {
1101 pins = "gpio26", "gpio27", "gpio28";
1105 qup_spi11_cs: qup-spi11-cs-state {
1106 pins = "gpio29";
1110 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1111 pins = "gpio28", "gpio29";
1115 qup_spi12_data_clk: qup-spi12-data-clk-state {
1116 pins = "gpio28", "gpio29", "gpio26";
1120 qup_spi12_cs: qup-spi12-cs-state {
1121 pins = "gpio27";
1125 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1126 pins = "gpio30", "gpio31";
1130 qup_spi13_data_clk: qup-spi13-data-clk-state {
1131 pins = "gpio30", "gpio31", "gpio32";
1135 qup_spi13_cs: qup-spi13-cs-state {
1136 pins = "gpio33";
1140 qup_uart13_default: qup-uart13-default-state {
1141 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1145 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1146 pins = "gpio34", "gpio35";
1150 qup_spi14_data_clk: qup-spi14-data-clk-state {
1151 pins = "gpio34", "gpio35", "gpio36";
1155 qup_spi14_cs: qup-spi14-cs-state {
1156 pins = "gpio37", "gpio38";
1160 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1161 pins = "gpio40", "gpio41";
1165 qup_spi15_data_clk: qup-spi15-data-clk-state {
1166 pins = "gpio40", "gpio41", "gpio30";
1170 qup_spi15_cs: qup-spi15-cs-state {
1171 pins = "gpio31";
1175 sdc_on_state: sdc-on-state {
1176 clk-pins {
1177 pins = "sdc1_clk";
1178 drive-strength = <16>;
1179 bias-disable;
1182 cmd-pins {
1183 pins = "sdc1_cmd";
1184 drive-strength = <10>;
1185 bias-pull-up;
1188 data-pins {
1189 pins = "sdc1_data";
1190 drive-strength = <10>;
1191 bias-pull-up;
1194 rclk-pins {
1195 pins = "sdc1_rclk";
1196 bias-pull-down;
1200 sdc_off_state: sdc-off-state {
1201 clk-pins {
1202 pins = "sdc1_clk";
1203 drive-strength = <2>;
1204 bias-disable;
1207 cmd-pins {
1208 pins = "sdc1_cmd";
1209 drive-strength = <2>;
1210 bias-pull-up;
1213 data-pins {
1214 pins = "sdc1_data";
1215 drive-strength = <2>;
1216 bias-pull-up;
1219 rclk-pins {
1220 pins = "sdc1_rclk";
1221 bias-pull-down;
1227 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1230 #address-cells = <1>;
1231 #size-cells = <1>;
1233 pil-reloc@94c {
1234 compatible = "qcom,pil-reloc-info";
1240 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1242 #iommu-cells = <2>;
1243 #global-interrupts = <2>;
1295 intc: interrupt-controller@17200000 {
1296 compatible = "arm,gic-v3";
1300 #interrupt-cells = <3>;
1301 interrupt-controller;
1302 #redistributor-regions = <1>;
1303 redistributor-stride = <0x0 0x20000>;
1307 compatible = "arm,armv7-timer-mem";
1309 #address-cells = <1>;
1310 #size-cells = <1>;
1318 frame-number = <0>;
1324 frame-number = <1>;
1332 frame-number = <2>;
1339 frame-number = <3>;
1346 frame-number = <4>;
1353 frame-number = <5>;
1360 frame-number = <6>;
1366 compatible = "qcom,rpmh-rsc";
1370 reg-names = "drv-0", "drv-1", "drv-2";
1374 qcom,tcs-offset = <0xd00>;
1375 qcom,drv-id = <2>;
1376 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1379 power-domains = <&CLUSTER_PD>;
1381 apps_bcm_voter: bcm-voter {
1382 compatible = "qcom,bcm-voter";
1385 rpmhcc: clock-controller {
1386 compatible = "qcom,qdu1000-rpmh-clk";
1388 clock-names = "xo";
1389 #clock-cells = <1>;
1392 rpmhpd: power-controller {
1393 compatible = "qcom,qdu1000-rpmhpd";
1394 #power-domain-cells = <1>;
1395 operating-points-v2 = <&rpmhpd_opp_table>;
1397 rpmhpd_opp_table: opp-table {
1398 compatible = "operating-points-v2";
1401 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1405 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1409 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1413 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1417 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1421 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1425 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1429 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1433 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1437 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1444 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1446 reg-names = "freq-domain0", "freq-domain1";
1448 clock-names = "xo", "alternate";
1449 #freq-domain-cells = <1>;
1450 #clock-cells = <1>;
1454 compatible = "qcom,qdu1000-gem-noc";
1456 qcom,bcm-voters = <&apps_bcm_voter>;
1457 #interconnect-cells = <2>;
1460 system-cache-controller@19200000 {
1461 compatible = "qcom,qdu1000-llcc";
1464 reg-names = "llcc0_base",
1471 compatible = "arm,armv8-timer";