Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 next-level-cache = <&L2_0>;
46 #cooling-cells = <2>;
48 operating-points-v2 = <&cpu_opp_table>;
49 power-domains = <&cpr>;
50 power-domain-names = "cpr";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0>;
59 next-level-cache = <&L2_0>;
60 #cooling-cells = <2>;
62 operating-points-v2 = <&cpu_opp_table>;
63 power-domains = <&cpr>;
64 power-domain-names = "cpr";
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&CPU_SLEEP_0>;
73 next-level-cache = <&L2_0>;
74 #cooling-cells = <2>;
76 operating-points-v2 = <&cpu_opp_table>;
77 power-domains = <&cpr>;
78 power-domain-names = "cpr";
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 cpu-idle-states = <&CPU_SLEEP_0>;
87 next-level-cache = <&L2_0>;
88 #cooling-cells = <2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 power-domains = <&cpr>;
92 power-domain-names = "cpr";
95 L2_0: l2-cache {
97 cache-level = <2>;
98 cache-unified;
101 idle-states {
102 entry-method = "psci";
104 CPU_SLEEP_0: cpu-sleep-0 {
105 compatible = "arm,idle-state";
106 idle-state-name = "standalone-power-collapse";
107 arm,psci-suspend-param = <0x40000003>;
108 entry-latency-us = <125>;
109 exit-latency-us = <180>;
110 min-residency-us = <595>;
111 local-timer-stop;
116 cpu_opp_table: opp-table-cpu {
117 compatible = "operating-points-v2-kryo-cpu";
118 opp-shared;
120 opp-1094400000 {
121 opp-hz = /bits/ 64 <1094400000>;
122 required-opps = <&cpr_opp1>;
124 opp-1248000000 {
125 opp-hz = /bits/ 64 <1248000000>;
126 required-opps = <&cpr_opp2>;
128 opp-1401600000 {
129 opp-hz = /bits/ 64 <1401600000>;
130 required-opps = <&cpr_opp3>;
134 cpr_opp_table: opp-table-cpr {
135 compatible = "operating-points-v2-qcom-level";
138 opp-level = <1>;
139 qcom,opp-fuse-level = <1>;
142 opp-level = <2>;
143 qcom,opp-fuse-level = <2>;
146 opp-level = <3>;
147 qcom,opp-fuse-level = <3>;
153 compatible = "qcom,scm-qcs404", "qcom,scm";
154 #reset-cells = <1>;
165 compatible = "arm,psci-1.0";
170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
172 glink-edge {
173 compatible = "qcom,glink-rpm";
176 qcom,rpm-msg-ram = <&rpm_msg_ram>;
179 rpm_requests: rpm-requests {
180 compatible = "qcom,rpm-qcs404";
181 qcom,glink-channels = "rpm_requests";
183 rpmcc: clock-controller {
184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
185 #clock-cells = <1>;
187 clock-names = "xo";
190 rpmpd: power-controller {
191 compatible = "qcom,qcs404-rpmpd";
192 #power-domain-cells = <1>;
193 operating-points-v2 = <&rpmpd_opp_table>;
195 rpmpd_opp_table: opp-table {
196 compatible = "operating-points-v2";
199 opp-level = <16>;
203 opp-level = <32>;
207 opp-level = <48>;
211 opp-level = <64>;
215 opp-level = <128>;
219 opp-level = <192>;
223 opp-level = <256>;
227 opp-level = <320>;
231 opp-level = <384>;
235 opp-level = <416>;
239 opp-level = <512>;
247 reserved-memory {
248 #address-cells = <2>;
249 #size-cells = <2>;
254 no-map;
259 no-map;
264 no-map;
269 no-map;
274 no-map;
279 no-map;
284 no-map;
289 no-map;
294 no-map;
301 memory-region = <&smem_region>;
302 qcom,rpm-msg-ram = <&rpm_msg_ram>;
308 #address-cells = <1>;
309 #size-cells = <1>;
311 compatible = "simple-bus";
313 turingcc: clock-controller@800000 {
314 compatible = "qcom,qcs404-turingcc";
318 #clock-cells = <1>;
319 #reset-cells = <1>;
325 compatible = "qcom,rpm-msg-ram";
330 compatible = "qcom,usb-ss-28nm-phy";
332 #phy-cells = <0>;
336 clock-names = "ref", "ahb", "pipe";
339 reset-names = "com", "phy";
344 compatible = "qcom,usb-hs-28nm-femtophy";
346 #phy-cells = <0>;
350 clock-names = "ref", "ahb", "sleep";
353 reset-names = "phy", "por";
358 compatible = "qcom,usb-hs-28nm-femtophy";
360 #phy-cells = <0>;
364 clock-names = "ref", "ahb", "sleep";
367 reset-names = "phy", "por";
372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
374 #address-cells = <1>;
375 #size-cells = <1>;
381 tsens_s0_p1: s0-p1@1f8 {
386 tsens_s0_p2: s0-p2@1f8 {
391 tsens_s1_p1: s1-p1@1f9 {
396 tsens_s1_p2: s1-p2@1fa {
401 tsens_s2_p1: s2-p1@1fb {
406 tsens_s2_p2: s2-p2@1fb {
411 tsens_s3_p1: s3-p1@1fc {
416 tsens_s3_p2: s3-p2@1fd {
421 tsens_s4_p1: s4-p1@1fe {
426 tsens_s4_p2: s4-p2@1fe {
431 tsens_s5_p1: s5-p1@200 {
436 tsens_s5_p2: s5-p2@200 {
441 tsens_s6_p1: s6-p1@201 {
446 tsens_s6_p2: s6-p2@202 {
451 tsens_s7_p1: s7-p1@203 {
456 tsens_s7_p2: s7-p2@203 {
461 tsens_s8_p1: s8-p1@204 {
466 tsens_s8_p2: s8-p2@205 {
471 tsens_s9_p1: s9-p1@206 {
476 tsens_s9_p2: s9-p2@206 {
551 compatible = "qcom,prng-ee";
554 clock-names = "core";
559 compatible = "qcom,qcs404-bimc";
560 #interconnect-cells = <1>;
563 tsens: thermal-sensor@4a9000 {
564 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
567 nvmem-cells = <&tsens_mode>,
579 nvmem-cell-names = "mode",
593 interrupt-names = "uplow";
594 #thermal-sensor-cells = <1>;
599 compatible = "qcom,qcs404-pcnoc";
600 #interconnect-cells = <1>;
605 compatible = "qcom,qcs404-snoc";
606 #interconnect-cells = <1>;
610 compatible = "qcom,qcs404-cdsp-pas";
613 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
618 interrupt-names = "wdog", "fatal", "ready",
619 "handover", "stop-ack";
622 clock-names = "xo";
634 * clock-names = "xo",
643 * reset-names = "restart";
644 * qcom,halt-regs = <&tcsr 0x19004>;
647 memory-region = <&cdsp_fw_mem>;
649 qcom,smem-states = <&cdsp_smp2p_out 0>;
650 qcom,smem-state-names = "stop";
654 glink-edge {
657 qcom,remote-pid = <5>;
665 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
667 #address-cells = <1>;
668 #size-cells = <1>;
674 clock-names = "core", "iface", "sleep", "mock_utmi";
675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
677 assigned-clock-rates = <19200000>, <200000000>;
685 phy-names = "usb2-phy", "usb3-phy";
686 snps,has-lpm-erratum;
687 snps,hird-threshold = /bits/ 8 <0x10>;
694 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
696 #address-cells = <1>;
697 #size-cells = <1>;
703 clock-names = "core", "iface", "sleep", "mock_utmi";
704 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
706 assigned-clock-rates = <19200000>, <133333333>;
714 phy-names = "usb2-phy";
715 snps,has-lpm-erratum;
716 snps,hird-threshold = /bits/ 8 <0x10>;
723 compatible = "qcom,qcs404-pinctrl";
727 reg-names = "south", "north", "east";
729 gpio-ranges = <&tlmm 0 0 120>;
730 gpio-controller;
731 #gpio-cells = <2>;
732 interrupt-controller;
733 #interrupt-cells = <2>;
735 blsp1_i2c0_default: blsp1-i2c0-default-state {
740 blsp1_i2c1_default: blsp1-i2c1-default-state {
745 blsp1_i2c2_default: blsp1-i2c2-default-state {
746 sda-pins {
751 scl-pins {
757 blsp1_i2c3_default: blsp1-i2c3-default-state {
762 blsp1_i2c4_default: blsp1-i2c4-default-state {
767 blsp1_uart0_default: blsp1-uart0-default-state {
772 blsp1_uart1_default: blsp1-uart1-default-state {
777 blsp1_uart2_default: blsp1-uart2-default-state {
778 rx-pins {
783 tx-pins {
789 blsp1_uart3_default: blsp1-uart3-default-state {
790 cts-pins {
795 rts-tx-pins {
800 rx-pins {
806 blsp2_i2c0_default: blsp2-i2c0-default-state {
811 blsp1_spi0_default: blsp1-spi0-default-state {
816 blsp1_spi1_default: blsp1-spi1-default-state {
817 mosi-pins {
822 miso-pins {
827 cs-n-pins {
832 clk-pins {
838 blsp1_spi2_default: blsp1-spi2-default-state {
843 blsp1_spi3_default: blsp1-spi3-default-state {
848 blsp1_spi4_default: blsp1-spi4-default-state {
853 blsp2_spi0_default: blsp2-spi0-default-state {
858 blsp2_uart0_default: blsp2-uart0-default-state {
864 gcc: clock-controller@1800000 {
865 compatible = "qcom,gcc-qcs404";
867 #clock-cells = <1>;
868 #reset-cells = <1>;
869 #power-domain-cells = <1>;
878 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
879 assigned-clock-rates = <19200000>;
883 compatible = "qcom,tcsr-mutex";
885 #hwlock-cells = <1>;
889 compatible = "qcom,qcs404-tcsr", "syscon";
894 compatible = "qcom,rpm-stats";
899 compatible = "qcom,spmi-pmic-arb";
905 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
906 interrupt-names = "periph_irq";
910 #address-cells = <2>;
911 #size-cells = <0>;
912 interrupt-controller;
913 #interrupt-cells = <4>;
917 compatible = "qcom,qcs404-wcss-pas";
920 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
925 interrupt-names = "wdog", "fatal", "ready",
926 "handover", "stop-ack";
929 clock-names = "xo";
931 memory-region = <&wlan_fw_mem>;
933 qcom,smem-states = <&wcss_smp2p_out 0>;
934 qcom,smem-state-names = "stop";
938 glink-edge {
941 qcom,remote-pid = <1>;
949 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
955 reset-names = "phy", "pipe";
957 clock-output-names = "pcie_0_pipe_clk";
958 #clock-cells = <0>;
959 #phy-cells = <0>;
965 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
967 reg-names = "hc", "cqhci";
971 interrupt-names = "hc_irq", "pwr_irq";
976 clock-names = "iface", "core", "xo";
981 blsp1_dma: dma-controller@7884000 {
982 compatible = "qcom,bam-v1.7.0";
986 clock-names = "bam_clk";
987 #dma-cells = <1>;
993 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
997 clock-names = "core", "iface";
999 dma-names = "tx", "rx";
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&blsp1_uart0_default>;
1006 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1010 clock-names = "core", "iface";
1012 dma-names = "tx", "rx";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&blsp1_uart1_default>;
1019 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1023 clock-names = "core", "iface";
1025 dma-names = "tx", "rx";
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&blsp1_uart2_default>;
1032 compatible = "qcom,qcs404-ethqos";
1035 reg-names = "stmmaceth", "rgmii";
1036 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
1043 interrupt-names = "macirq", "eth_lpi";
1046 rx-fifo-depth = <4096>;
1047 tx-fifo-depth = <4096>;
1053 compatible = "qcom,wcn3990-wifi";
1055 reg-names = "membase";
1056 memory-region = <&wlan_msa_mem>;
1073 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1077 clock-names = "core", "iface";
1079 dma-names = "tx", "rx";
1080 pinctrl-names = "default";
1081 pinctrl-0 = <&blsp1_uart3_default>;
1086 compatible = "qcom,i2c-qup-v2.2.1";
1091 clock-names = "core", "iface";
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&blsp1_i2c0_default>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1100 compatible = "qcom,spi-qup-v2.2.1";
1105 clock-names = "core", "iface";
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&blsp1_spi0_default>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1114 compatible = "qcom,i2c-qup-v2.2.1";
1119 clock-names = "core", "iface";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&blsp1_i2c1_default>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,spi-qup-v2.2.1";
1133 clock-names = "core", "iface";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&blsp1_spi1_default>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1142 compatible = "qcom,i2c-qup-v2.2.1";
1147 clock-names = "core", "iface";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&blsp1_i2c2_default>;
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1156 compatible = "qcom,spi-qup-v2.2.1";
1161 clock-names = "core", "iface";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&blsp1_spi2_default>;
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1170 compatible = "qcom,i2c-qup-v2.2.1";
1175 clock-names = "core", "iface";
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&blsp1_i2c3_default>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1184 compatible = "qcom,spi-qup-v2.2.1";
1189 clock-names = "core", "iface";
1190 pinctrl-names = "default";
1191 pinctrl-0 = <&blsp1_spi3_default>;
1192 #address-cells = <1>;
1193 #size-cells = <0>;
1198 compatible = "qcom,i2c-qup-v2.2.1";
1203 clock-names = "core", "iface";
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&blsp1_i2c4_default>;
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1212 compatible = "qcom,spi-qup-v2.2.1";
1217 clock-names = "core", "iface";
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&blsp1_spi4_default>;
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1225 blsp2_dma: dma-controller@7ac4000 {
1226 compatible = "qcom,bam-v1.7.0";
1230 clock-names = "bam_clk";
1231 #dma-cells = <1>;
1237 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1241 clock-names = "core", "iface";
1243 dma-names = "tx", "rx";
1244 pinctrl-names = "default";
1245 pinctrl-0 = <&blsp2_uart0_default>;
1250 compatible = "qcom,i2c-qup-v2.2.1";
1255 clock-names = "core", "iface";
1256 pinctrl-names = "default";
1257 pinctrl-0 = <&blsp2_i2c0_default>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1264 compatible = "qcom,spi-qup-v2.2.1";
1269 clock-names = "core", "iface";
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&blsp2_spi0_default>;
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1278 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1281 #address-cells = <1>;
1282 #size-cells = <1>;
1286 pil-reloc@94c {
1287 compatible = "qcom,pil-reloc-info";
1292 intc: interrupt-controller@b000000 {
1293 compatible = "qcom,msm-qgic2";
1294 interrupt-controller;
1295 #interrupt-cells = <3>;
1301 compatible = "qcom,qcs404-apcs-apps-global",
1302 "qcom,msm8916-apcs-kpss-global", "syscon";
1304 #mbox-cells = <1>;
1306 clock-names = "pll", "aux";
1307 #clock-cells = <0>;
1310 apcs_hfpll: clock-controller@b016000 {
1313 #clock-cells = <0>;
1314 clock-output-names = "apcs_hfpll";
1316 clock-names = "xo";
1320 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1325 cpr: power-controller@b018000 {
1326 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1330 clock-names = "ref";
1331 vdd-apc-supply = <&pms405_s3>;
1332 #power-domain-cells = <0>;
1333 operating-points-v2 = <&cpr_opp_table>;
1334 acc-syscon = <&tcsr>;
1336 nvmem-cells = <&cpr_efuse_quot_offset1>,
1349 nvmem-cell-names = "cpr_quotient_offset1",
1365 #address-cells = <1>;
1366 #size-cells = <1>;
1368 compatible = "arm,armv7-timer-mem";
1370 clock-frequency = <19200000>;
1373 frame-number = <0>;
1381 frame-number = <1>;
1388 frame-number = <2>;
1395 frame-number = <3>;
1402 frame-number = <4>;
1409 frame-number = <5>;
1416 frame-number = <6>;
1424 compatible = "qcom,qcs404-adsp-pas";
1427 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1432 interrupt-names = "wdog", "fatal", "ready",
1433 "handover", "stop-ack";
1436 clock-names = "xo";
1438 memory-region = <&adsp_fw_mem>;
1440 qcom,smem-states = <&adsp_smp2p_out 0>;
1441 qcom,smem-state-names = "stop";
1445 glink-edge {
1448 qcom,remote-pid = <2>;
1456 compatible = "qcom,pcie-qcs404";
1461 reg-names = "dbi", "elbi", "parf", "config";
1463 linux,pci-domain = <0>;
1464 bus-range = <0x00 0xff>;
1465 num-lanes = <1>;
1466 #address-cells = <3>;
1467 #size-cells = <2>;
1473 interrupt-names = "msi";
1474 #interrupt-cells = <1>;
1475 interrupt-map-mask = <0 0 0 0x7>;
1476 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1484 clock-names = "iface", "aux", "master_bus", "slave_bus";
1492 reset-names = "axi_m",
1500 phy-names = "pciephy";
1507 compatible = "arm,armv8-timer";
1514 smp2p-adsp {
1519 qcom,local-pid = <0>;
1520 qcom,remote-pid = <2>;
1522 adsp_smp2p_out: master-kernel {
1523 qcom,entry-name = "master-kernel";
1524 #qcom,smem-state-cells = <1>;
1527 adsp_smp2p_in: slave-kernel {
1528 qcom,entry-name = "slave-kernel";
1529 interrupt-controller;
1530 #interrupt-cells = <2>;
1534 smp2p-cdsp {
1539 qcom,local-pid = <0>;
1540 qcom,remote-pid = <5>;
1542 cdsp_smp2p_out: master-kernel {
1543 qcom,entry-name = "master-kernel";
1544 #qcom,smem-state-cells = <1>;
1547 cdsp_smp2p_in: slave-kernel {
1548 qcom,entry-name = "slave-kernel";
1549 interrupt-controller;
1550 #interrupt-cells = <2>;
1554 smp2p-wcss {
1559 qcom,local-pid = <0>;
1560 qcom,remote-pid = <1>;
1562 wcss_smp2p_out: master-kernel {
1563 qcom,entry-name = "master-kernel";
1564 #qcom,smem-state-cells = <1>;
1567 wcss_smp2p_in: slave-kernel {
1568 qcom,entry-name = "slave-kernel";
1569 interrupt-controller;
1570 #interrupt-cells = <2>;
1574 thermal-zones {
1575 aoss-thermal {
1576 polling-delay-passive = <250>;
1577 polling-delay = <1000>;
1579 thermal-sensors = <&tsens 0>;
1582 aoss_alert0: trip-point0 {
1590 q6-hvx-thermal {
1591 polling-delay-passive = <250>;
1592 polling-delay = <1000>;
1594 thermal-sensors = <&tsens 1>;
1597 q6_hvx_alert0: trip-point0 {
1605 lpass-thermal {
1606 polling-delay-passive = <250>;
1607 polling-delay = <1000>;
1609 thermal-sensors = <&tsens 2>;
1612 lpass_alert0: trip-point0 {
1620 wlan-thermal {
1621 polling-delay-passive = <250>;
1622 polling-delay = <1000>;
1624 thermal-sensors = <&tsens 3>;
1627 wlan_alert0: trip-point0 {
1635 cluster-thermal {
1636 polling-delay-passive = <250>;
1637 polling-delay = <1000>;
1639 thermal-sensors = <&tsens 4>;
1642 cluster_alert0: trip-point0 {
1647 cluster_alert1: trip-point1 {
1652 cluster_crit: cluster-crit {
1658 cooling-maps {
1661 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1669 cpu0-thermal {
1670 polling-delay-passive = <250>;
1671 polling-delay = <1000>;
1673 thermal-sensors = <&tsens 5>;
1676 cpu0_alert0: trip-point0 {
1681 cpu0_alert1: trip-point1 {
1686 cpu0_crit: cpu-crit {
1692 cooling-maps {
1695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1703 cpu1-thermal {
1704 polling-delay-passive = <250>;
1705 polling-delay = <1000>;
1707 thermal-sensors = <&tsens 6>;
1710 cpu1_alert0: trip-point0 {
1715 cpu1_alert1: trip-point1 {
1720 cpu1_crit: cpu-crit {
1726 cooling-maps {
1729 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1737 cpu2-thermal {
1738 polling-delay-passive = <250>;
1739 polling-delay = <1000>;
1741 thermal-sensors = <&tsens 7>;
1744 cpu2_alert0: trip-point0 {
1749 cpu2_alert1: trip-point1 {
1754 cpu2_crit: cpu-crit {
1760 cooling-maps {
1763 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771 cpu3-thermal {
1772 polling-delay-passive = <250>;
1773 polling-delay = <1000>;
1775 thermal-sensors = <&tsens 8>;
1778 cpu3_alert0: trip-point0 {
1783 cpu3_alert1: trip-point1 {
1788 cpu3_crit: cpu-crit {
1794 cooling-maps {
1797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1805 gpu-thermal {
1806 polling-delay-passive = <250>;
1807 polling-delay = <1000>;
1809 thermal-sensors = <&tsens 9>;
1812 gpu_alert0: trip-point0 {