Lines Matching +full:0 +full:x01c40000
30 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
48 clocks = <&cpufreq_hw 0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x1>;
67 clocks = <&cpufreq_hw 0>;
72 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x2>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
94 reg = <0x0 0x3>;
95 clocks = <&cpufreq_hw 0>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
126 CLUSTER_SLEEP: cluster-sleep-0 {
128 arm,psci-suspend-param = <0x41000043>;
138 CPU_SLEEP: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x40000003>;
164 reg = <0 0x40000000 0 0>;
177 #power-domain-cells = <0>;
183 #power-domain-cells = <0>;
189 #power-domain-cells = <0>;
195 #power-domain-cells = <0>;
201 #power-domain-cells = <0>;
214 mboxes = <&apcs_glb 0>;
278 #power-domain-cells = <0>;
296 reg = <0x0 0x45700000 0x0 0x600000>;
301 reg = <0x0 0x45e00000 0x0 0x140000>;
306 reg = <0x0 0x45fff000 0x0 0x1000>;
312 reg = <0x0 0x46000000 0x0 0x200000>;
320 reg = <0x0 0x4ab00000 0x0 0x6900000>;
325 reg = <0x0 0x51400000 0x0 0x500000>;
330 reg = <0x0 0x51900000 0x0 0x100000>;
335 reg = <0x0 0x51a00000 0x0 0x1c00000>;
340 reg = <0x0 0x53600000 0x0 0x10000>;
345 reg = <0x0 0x53610000 0x0 0x5000>;
351 reg = <0x0 0x53615000 0x0 0x2000>;
356 reg = <0x0 0x5c000000 0x0 0x00f00000>;
361 reg = <0x0 0x5cf00000 0x0 0x0100000>;
366 reg = <0x0 0x60000000 0x0 0x3900000>;
372 reg = <0x0 0x89b01000 0x0 0x200000>;
388 qcom,local-pid = <0>;
411 qcom,local-pid = <0>;
432 soc: soc@0 {
436 ranges = <0 0 0 0 0x10 0>;
437 dma-ranges = <0 0 0 0 0x10 0>;
441 reg = <0x0 0x00340000 0x0 0x20000>;
447 reg = <0x0 0x00500000 0x0 0x300000>;
450 gpio-ranges = <&tlmm 0 0 127>;
647 reg = <0x0 0x01400000 0x0 0x1f0000>;
657 reg = <0x0 0x01613000 0x0 0x180>;
665 #phy-cells = <0>;
672 reg = <0x0 0x01615000 0x0 0x1000>;
688 #clock-cells = <0>;
691 #phy-cells = <0>;
698 reg = <0x0 0x01880000 0x0 0x60200>;
719 reg = <0x0 0x01900000 0x0 0x8200>;
725 reg = <0x0 0x01b44000 0x0 0x3000>;
730 reg = <0x25b 0x1>;
737 reg = <0x0 0x01b8e300 0x0 0x600>;
747 opp-0 {
791 reg = <0x0 0x01c40000 0x0 0x1100>,
792 <0x0 0x01e00000 0x0 0x2000000>,
793 <0x0 0x03e00000 0x0 0x100000>,
794 <0x0 0x03f00000 0x0 0xa0000>,
795 <0x0 0x01c0a000 0x0 0x26000>;
803 qcom,ee = <0>;
804 qcom,channel = <0>;
806 #size-cells = <0>;
813 reg = <0x0 0x04411000 0x0 0x1ff>,
814 <0x0 0x04410000 0x0 0x8>;
824 reg = <0x0 0x04453000 0x0 0x1000>;
831 reg = <0x0 0x04480000 0x0 0x80000>;
837 reg = <0x0 0x045f0000 0x0 0x7000>;
840 ranges = <0 0x0 0x045f0000 0x7000>;
843 reg = <0x1b8 0x48>;
849 reg = <0x0 0x04690000 0x0 0x10000>;
854 reg = <0x0 0x04744000 0x0 0x1000>,
855 <0x0 0x04745000 0x0 0x1000>,
856 <0x0 0x04748000 0x0 0x8000>;
878 iommus = <&apps_smmu 0xc0 0x0>;
886 qcom,dll-config = <0x000f642c>;
887 qcom,ddr-config = <0x80040868>;
920 reg = <0x0 0x04784000 0x0 0x1000>;
938 iommus = <&apps_smmu 0xa0 0x0>;
946 qcom,dll-config = <0x0007642c>;
947 qcom,ddr-config = <0x80040868>;
973 reg = <0x0 0x04a00000 0x0 0x60000>;
985 dma-channel-mask = <0x1f>;
986 iommus = <&apps_smmu 0xf6 0x0>;
993 reg = <0x0 0x04ac0000 0x0 0x2000>;
997 iommus = <&apps_smmu 0xe3 0x0>;
1005 reg = <0x0 0x04a80000 0x0 0x4000>;
1009 pinctrl-0 = <&qup_i2c0_default>;
1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1024 #size-cells = <0>;
1030 reg = <0x0 0x04a80000 0x0 0x4000>;
1034 pinctrl-0 = <&qup_spi0_default>;
1036 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1037 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1046 #size-cells = <0>;
1052 reg = <0x0 0x04a80000 0x0 0x4000>;
1056 pinctrl-0 = <&qup_uart0_default>;
1069 reg = <0x0 0x04a84000 0x0 0x4000>;
1073 pinctrl-0 = <&qup_i2c1_default>;
1075 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1088 #size-cells = <0>;
1094 reg = <0x0 0x04a84000 0x0 0x4000>;
1098 pinctrl-0 = <&qup_spi1_default>;
1100 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1110 #size-cells = <0>;
1116 reg = <0x0 0x04a88000 0x0 0x4000>;
1120 pinctrl-0 = <&qup_i2c2_default>;
1122 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1135 #size-cells = <0>;
1141 reg = <0x0 0x04a88000 0x0 0x4000>;
1145 pinctrl-0 = <&qup_spi2_default>;
1147 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1157 #size-cells = <0>;
1163 reg = <0x0 0x04a8c000 0x0 0x4000>;
1167 pinctrl-0 = <&qup_i2c3_default>;
1169 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1182 #size-cells = <0>;
1188 reg = <0x0 0x04a8c000 0x0 0x4000>;
1192 pinctrl-0 = <&qup_spi3_default>;
1194 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1204 #size-cells = <0>;
1210 reg = <0x0 0x04a90000 0x0 0x4000>;
1214 pinctrl-0 = <&qup_i2c4_default>;
1216 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1229 #size-cells = <0>;
1235 reg = <0x0 0x04a90000 0x0 0x4000>;
1240 pinctrl-0 = <&qup_spi4_default>;
1241 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1251 #size-cells = <0>;
1257 reg = <0x0 0x04a90000 0x0 0x4000>;
1261 pinctrl-0 = <&qup_uart4_default>;
1274 reg = <0x0 0x04a94000 0x0 0x4000>;
1278 pinctrl-0 = <&qup_i2c5_default>;
1280 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1293 #size-cells = <0>;
1299 reg = <0x0 0x04a94000 0x0 0x4000>;
1303 pinctrl-0 = <&qup_spi5_default>;
1305 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1315 #size-cells = <0>;
1322 reg = <0x0 0x04ef8800 0x0 0x400>;
1364 reg = <0x0 0x04e00000 0x0 0xcd00>;
1368 iommus = <&apps_smmu 0x120 0x0>;
1372 snps,hird-threshold = /bits/ 8 <0x10>;
1381 reg = <0x0 0x05e00000 0x0 0x1000>;
1398 iommus = <&apps_smmu 0x420 0x2>,
1399 <&apps_smmu 0x421 0x0>;
1415 reg = <0x0 0x05e01000 0x0 0x8f000>,
1416 <0x0 0x05eb0000 0x0 0x2008>;
1421 interrupts = <0>;
1439 #size-cells = <0>;
1441 port@0 {
1442 reg = <0>;
1481 reg = <0x0 0x05e94000 0x0 0x400>;
1502 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1510 #size-cells = <0>;
1535 #size-cells = <0>;
1537 port@0 {
1538 reg = <0>;
1556 reg = <0x0 0x05e94400 0x0 0x100>,
1557 <0x0 0x05e94500 0x0 0x300>,
1558 <0x0 0x05e94800 0x0 0x188>;
1572 #phy-cells = <0>;
1580 reg = <0x0 0x05f00000 0x0 0x20000>;
1585 <&mdss_dsi0_phy 0>,
1600 reg = <0x0 0x06080000 0x0 0x100>;
1603 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 qcom,smem-states = <&modem_smp2p_out 0>;
1637 reg = <0x0 0x0ab00000 0x0 0x100>;
1640 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1658 qcom,smem-states = <&adsp_smp2p_out 0>;
1673 reg = <0x0 0x0c600000 0x0 0x80000>;
1746 reg = <0x0 0x0c800000 0x0 0x800000>;
1761 iommus = <&apps_smmu 0x1a0 0x1>;
1768 reg = <0x0 0x0f017000 0x0 0x1000>;
1776 reg = <0x0 0x0f111000 0x0 0x1000>;
1782 reg = <0x0 0x0f120000 0x0 0x1000>;
1785 ranges = <0 0x0 0x0f121000 0x8000>;
1787 frame@0 {
1788 reg = <0x0 0x1000>,
1789 <0x1000 0x1000>;
1792 frame-number = <0>;
1796 reg = <0x2000 0x1000>;
1803 reg = <0x3000 0x1000>;
1810 reg = <0x4000 0x1000>;
1817 reg = <0x5000 0x1000>;
1824 reg = <0x6000 0x1000>;
1831 reg = <0x7000 0x1000>;
1840 reg = <0x0 0x0f200000 0x0 0x10000>,
1841 <0x0 0x0f300000 0x0 0x100000>;
1847 redistributor-stride = <0x0 0x20000>;
1852 reg = <0x0 0x0f521000 0x0 0x1000>;
1855 interrupt-names = "dcvsh-irq-0";
1866 polling-delay-passive = <0>;
1867 polling-delay = <0>;
1869 thermal-sensors = <&tsens0 0>;
1893 polling-delay-passive = <0>;
1894 polling-delay = <0>;
1920 polling-delay-passive = <0>;
1921 polling-delay = <0>;
1947 polling-delay-passive = <0>;
1948 polling-delay = <0>;
1974 polling-delay-passive = <0>;
1975 polling-delay = <0>;
2001 polling-delay-passive = <0>;
2002 polling-delay = <0>;
2028 polling-delay-passive = <0>;
2029 polling-delay = <0>;
2055 polling-delay-passive = <0>;
2056 polling-delay = <0>;
2082 polling-delay-passive = <0>;
2083 polling-delay = <0>;
2109 polling-delay-passive = <0>;
2110 polling-delay = <0>;
2141 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;