Lines Matching +full:0 +full:x1901
16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
79 reg = <0x0 0x93c00000 0x0 0x500000>;
84 reg = <0x0 0x94100000 0x0 0x200000>;
89 reg = <0x0 0x94300000 0x0 0xf00000>;
94 reg = <0x0 0x95200000 0x0 0x10000>;
99 reg = <0x0 0x95210000 0x0 0x5000>;
104 reg = <0x0 0x95600000 0x0 0x100000>;
109 reg = <0x0 0x95700000 0x0 0x100000>;
114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>;
123 #clock-cells = <0>;
130 #clock-cells = <0>;
137 #size-cells = <0>;
139 CPU0: cpu@0 {
142 reg = <0x0 0x0>;
157 reg = <0x0 0x1>;
167 reg = <0x0 0x2>;
177 reg = <0x0 0x3>;
187 reg = <0x0 0x100>;
202 reg = <0x0 0x101>;
212 reg = <0x0 0x102>;
222 reg = <0x0 0x103>;
270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
274 arm,psci-suspend-param = <0x00000002>;
280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
284 arm,psci-suspend-param = <0x40000003>;
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x00000002>;
305 arm,psci-suspend-param = <0x40000003>;
352 mboxes = <&apcs_glb 0>;
432 qcom,local-pid = <0>;
453 qcom,local-pid = <0>;
473 qcom,local-pid = <0>;
828 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
831 soc: soc@0 {
834 ranges = <0 0 0 0xffffffff>;
842 reg = <0x00100000 0xb0000>;
865 reg = <0x00778000 0x7000>;
870 reg = <0x00784000 0x621c>;
875 reg = <0x23a 0x1>;
876 bits = <0 4>;
882 reg = <0x010ab000 0x1000>, /* TM */
883 <0x010aa000 0x1000>; /* SROT */
893 reg = <0x010ae000 0x1000>, /* TM */
894 <0x010ad000 0x1000>; /* SROT */
904 reg = <0x01680000 0x10000>;
907 #global-interrupts = <0>;
919 reg = <0x016c0000 0x40000>;
922 #global-interrupts = <0>;
938 reg = <0x01c00000 0x2000>,
939 <0x1b000000 0xf1d>,
940 <0x1b000f20 0xa8>,
941 <0x1b100000 0x100000>;
944 linux,pci-domain = <0>;
945 bus-range = <0x00 0xff>;
953 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
954 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
959 interrupt-map-mask = <0 0 0 0x7>;
960 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
961 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
962 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
963 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
973 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
979 reg = <0x01c06000 0x1000>;
992 #clock-cells = <0>;
994 #phy-cells = <0>;
1005 reg = <0x01da4000 0x2500>;
1034 <0 0>,
1035 <0 0>,
1037 <0 0>,
1038 <0 0>,
1039 <0 0>,
1040 <0 0>;
1048 reg = <0x01da7000 0x1000>;
1058 resets = <&ufshc 0>;
1060 #phy-cells = <0>;
1066 reg = <0x01f40000 0x20000>;
1072 reg = <0x01f60000 0x20000>;
1077 reg = <0x03400000 0xc00000>;
1079 gpio-ranges = <&tlmm 0 0 150>;
1426 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1431 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1451 qcom,smem-states = <&modem_smp2p_out 0>;
1457 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1487 reg = <0x05000000 0x40000>;
1504 iommus = <&adreno_smmu 0>;
1514 opp-supported-hw = <0xff>;
1520 opp-supported-hw = <0xff>;
1526 opp-supported-hw = <0xff>;
1532 opp-supported-hw = <0xff>;
1538 opp-supported-hw = <0xff>;
1544 opp-supported-hw = <0xff>;
1550 opp-supported-hw = <0xff>;
1557 reg = <0x05040000 0x10000>;
1563 #global-interrupts = <0>;
1586 reg = <0x05065000 0x9000>;
1596 reg = <0x05800000 0x4040>;
1599 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1613 qcom,smem-states = <&slpi_smp2p_out 0>;
1631 reg = <0x06002000 0x1000>,
1632 <0x16280000 0x180000>;
1650 reg = <0x06041000 0x1000>;
1667 #size-cells = <0>;
1680 reg = <0x06042000 0x1000>;
1697 #size-cells = <0>;
1711 reg = <0x06045000 0x1000>;
1728 #size-cells = <0>;
1730 port@0 {
1731 reg = <0>;
1750 reg = <0x06046000 0x1000>;
1775 reg = <0x06047000 0x1000>;
1802 reg = <0x06048000 0x1000>;
1821 reg = <0x07840000 0x1000>;
1841 reg = <0x07940000 0x1000>;
1861 reg = <0x07a40000 0x1000>;
1881 reg = <0x07b40000 0x1000>;
1901 reg = <0x07b60000 0x1000>;
1918 #size-cells = <0>;
1920 port@0 {
1921 reg = <0>;
1988 reg = <0x07b70000 0x1000>;
2015 reg = <0x07c40000 0x1000>;
2034 reg = <0x07d40000 0x1000>;
2053 reg = <0x07e40000 0x1000>;
2072 reg = <0x07f40000 0x1000>;
2091 reg = <0x00290000 0x10000>;
2096 reg = <0x0800f000 0x1000>,
2097 <0x08400000 0x1000000>,
2098 <0x09400000 0x1000000>,
2099 <0x0a400000 0x220000>,
2100 <0x0800a000 0x3000>;
2104 qcom,ee = <0>;
2105 qcom,channel = <0>;
2107 #size-cells = <0>;
2114 reg = <0x0a8f8800 0x400>;
2145 reg = <0x0a800000 0xcd00>;
2152 snps,hird-threshold = /bits/ 8 <0x10>;
2158 reg = <0x0c010000 0x1000>;
2169 #clock-cells = <0>;
2170 #phy-cells = <0>;
2182 reg = <0x0c012000 0x2a8>;
2184 #phy-cells = <0>;
2197 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2214 reg = <0x0c144000 0x25000>;
2219 qcom,ee = <0>;
2227 reg = <0x0c171000 0x1000>;
2235 pinctrl-0 = <&blsp1_uart3_on>;
2241 reg = <0x0c175000 0x600>;
2250 pinctrl-0 = <&blsp1_i2c1_default>;
2256 #size-cells = <0>;
2261 reg = <0x0c176000 0x600>;
2270 pinctrl-0 = <&blsp1_i2c2_default>;
2276 #size-cells = <0>;
2281 reg = <0x0c177000 0x600>;
2290 pinctrl-0 = <&blsp1_i2c3_default>;
2296 #size-cells = <0>;
2301 reg = <0x0c178000 0x600>;
2310 pinctrl-0 = <&blsp1_i2c4_default>;
2316 #size-cells = <0>;
2321 reg = <0x0c179000 0x600>;
2330 pinctrl-0 = <&blsp1_i2c5_default>;
2336 #size-cells = <0>;
2341 reg = <0x0c17a000 0x600>;
2350 pinctrl-0 = <&blsp1_i2c6_default>;
2356 #size-cells = <0>;
2361 reg = <0x0c175000 0x600>;
2370 pinctrl-0 = <&blsp1_spi1_default>;
2374 #size-cells = <0>;
2379 reg = <0x0c176000 0x600>;
2388 pinctrl-0 = <&blsp1_spi2_default>;
2392 #size-cells = <0>;
2397 reg = <0x0c177000 0x600>;
2406 pinctrl-0 = <&blsp1_spi3_default>;
2410 #size-cells = <0>;
2415 reg = <0x0c178000 0x600>;
2424 pinctrl-0 = <&blsp1_spi4_default>;
2428 #size-cells = <0>;
2433 reg = <0x0c179000 0x600>;
2442 pinctrl-0 = <&blsp1_spi5_default>;
2446 #size-cells = <0>;
2451 reg = <0x0c17a000 0x600>;
2460 pinctrl-0 = <&blsp1_spi6_default>;
2464 #size-cells = <0>;
2469 reg = <0x0c184000 0x25000>;
2474 qcom,ee = <0>;
2482 reg = <0x0c1b0000 0x1000>;
2492 reg = <0x0c1b5000 0x600>;
2501 pinctrl-0 = <&blsp2_i2c1_default>;
2507 #size-cells = <0>;
2512 reg = <0x0c1b6000 0x600>;
2521 pinctrl-0 = <&blsp2_i2c2_default>;
2527 #size-cells = <0>;
2532 reg = <0x0c1b7000 0x600>;
2541 pinctrl-0 = <&blsp2_i2c3_default>;
2547 #size-cells = <0>;
2552 reg = <0x0c1b8000 0x600>;
2561 pinctrl-0 = <&blsp2_i2c4_default>;
2567 #size-cells = <0>;
2572 reg = <0x0c1b9000 0x600>;
2581 pinctrl-0 = <&blsp2_i2c5_default>;
2587 #size-cells = <0>;
2592 reg = <0x0c1ba000 0x600>;
2601 pinctrl-0 = <&blsp2_i2c6_default>;
2607 #size-cells = <0>;
2612 reg = <0x0c1b5000 0x600>;
2621 pinctrl-0 = <&blsp2_spi1_default>;
2625 #size-cells = <0>;
2630 reg = <0x0c1b6000 0x600>;
2639 pinctrl-0 = <&blsp2_spi2_default>;
2643 #size-cells = <0>;
2648 reg = <0x0c1b7000 0x600>;
2657 pinctrl-0 = <&blsp2_spi3_default>;
2661 #size-cells = <0>;
2666 reg = <0x0c1b8000 0x600>;
2675 pinctrl-0 = <&blsp2_spi4_default>;
2679 #size-cells = <0>;
2684 reg = <0x0c1b9000 0x600>;
2693 pinctrl-0 = <&blsp2_spi5_default>;
2697 #size-cells = <0>;
2702 reg = <0x0c1ba000 0x600>;
2711 pinctrl-0 = <&blsp2_spi6_default>;
2715 #size-cells = <0>;
2723 reg = <0xc8c0000 0x40000>;
2738 <&mdss_dsi0_phy 0>,
2740 <&mdss_dsi1_phy 0>,
2741 <0>,
2742 <0>,
2743 <0>,
2749 reg = <0x0c900000 0x1000>;
2764 iommus = <&mmss_smmu 0>;
2774 reg = <0x0c901000 0x8f000>,
2775 <0x0c9a8e00 0xf0>,
2776 <0x0c9b0000 0x2008>,
2777 <0x0c9b8000 0x1040>;
2784 interrupts = <0>;
2829 #size-cells = <0>;
2831 port@0 {
2832 reg = <0>;
2851 reg = <0x0c994000 0x400>;
2871 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2881 #size-cells = <0>;
2887 #size-cells = <0>;
2889 port@0 {
2890 reg = <0>;
2908 reg = <0x0c994400 0x200>,
2909 <0x0c994600 0x280>,
2910 <0x0c994a00 0x1e0>;
2920 #phy-cells = <0>;
2927 reg = <0x0c996000 0x400>;
2947 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2957 #size-cells = <0>;
2963 #size-cells = <0>;
2965 port@0 {
2966 reg = <0>;
2984 reg = <0x0c996400 0x200>,
2985 <0x0c996600 0x280>,
2986 <0x0c996a00 0x10e>;
2997 #phy-cells = <0>;
3005 reg = <0x0cd00000 0x40000>;
3015 #global-interrupts = <0>;
3043 reg = <0x17300000 0x4040>;
3046 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3058 qcom,smem-states = <&adsp_smp2p_out 0>;
3077 reg = <0x17911000 0x1000>;
3087 reg = <0x17920000 0x1000>;
3090 frame-number = <0>;
3093 reg = <0x17921000 0x1000>,
3094 <0x17922000 0x1000>;
3100 reg = <0x17923000 0x1000>;
3107 reg = <0x17924000 0x1000>;
3114 reg = <0x17925000 0x1000>;
3121 reg = <0x17926000 0x1000>;
3128 reg = <0x17927000 0x1000>;
3135 reg = <0x17928000 0x1000>;
3142 reg = <0x17a00000 0x10000>, /* GICD */
3143 <0x17b00000 0x100000>; /* GICR * 8 */
3150 redistributor-stride = <0x0 0x20000>;
3157 reg = <0x18800000 0x800000>;
3175 iommus = <&anoc2_smmu 0x1900>,
3176 <&anoc2_smmu 0x1901>;