Lines Matching +full:smmu +full:- +full:v3
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
43 #address-cells = <2>;
44 #size-cells = <0>;
50 enable-method = "psci";
51 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = <1024>;
55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
60 cache-level = <2>;
61 cache-unified;
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = <1024>;
74 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>;
76 next-level-cache = <&L2_0>;
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = <1024>;
88 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
93 cache-level = <2>;
94 cache-unified;
102 enable-method = "psci";
103 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>;
109 next-level-cache = <&L2_1>;
112 cpu-map {
134 idle-states {
135 entry-method = "psci";
137 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = "arm,idle-state";
139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency-us = <130>;
142 exit-latency-us = <80>;
143 min-residency-us = <300>;
148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse>;
151 opp-shared;
154 opp-307200000 {
155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <307200>;
160 opp-422400000 {
161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <307200>;
166 opp-480000000 {
167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <307200>;
172 opp-556800000 {
173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <307200>;
178 opp-652800000 {
179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <384000>;
184 opp-729600000 {
185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <460800>;
190 opp-844800000 {
191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <537600>;
196 opp-960000000 {
197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <672000>;
202 opp-1036800000 {
203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <672000>;
208 opp-1113600000 {
209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <825600>;
214 opp-1190400000 {
215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <825600>;
220 opp-1228800000 {
221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <902400>;
226 opp-1324800000 {
227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <1056000>;
232 opp-1363200000 {
233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <1132800>;
238 opp-1401600000 {
239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <1132800>;
244 opp-1478400000 {
245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <1190400>;
250 opp-1497600000 {
251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <1305600>;
256 opp-1593600000 {
257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <1382400>;
264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse>;
267 opp-shared;
270 opp-307200000 {
271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <307200>;
276 opp-403200000 {
277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <307200>;
282 opp-480000000 {
283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <307200>;
288 opp-556800000 {
289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <307200>;
294 opp-652800000 {
295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <307200>;
300 opp-729600000 {
301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <307200>;
306 opp-806400000 {
307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <384000>;
312 opp-883200000 {
313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <460800>;
318 opp-940800000 {
319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <537600>;
324 opp-1036800000 {
325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <595200>;
330 opp-1113600000 {
331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <672000>;
336 opp-1190400000 {
337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <672000>;
342 opp-1248000000 {
343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <748800>;
348 opp-1324800000 {
349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <825600>;
354 opp-1401600000 {
355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <902400>;
360 opp-1478400000 {
361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <979200>;
366 opp-1555200000 {
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <1056000>;
372 opp-1632000000 {
373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <1190400>;
378 opp-1708800000 {
379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <1228800>;
384 opp-1785600000 {
385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <1305600>;
390 opp-1804800000 {
391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <1305600>;
396 opp-1824000000 {
397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <1382400>;
402 opp-1900800000 {
403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <1305600>;
408 opp-1920000000 {
409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <1459200>;
414 opp-1996800000 {
415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <1593600>;
420 opp-2073600000 {
421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <1593600>;
426 opp-2150400000 {
427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <1593600>;
436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tcsr_2 0x13000>;
448 compatible = "qcom,coresight-remote-etm";
450 out-ports {
453 remote-endpoint =
461 compatible = "arm,psci-1.0";
466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
468 glink-edge {
469 compatible = "qcom,glink-rpm";
471 qcom,rpm-msg-ram = <&rpm_msg_ram>;
474 rpm_requests: rpm-requests {
475 compatible = "qcom,rpm-msm8996";
476 qcom,glink-channels = "rpm_requests";
478 rpmcc: clock-controller {
479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
480 #clock-cells = <1>;
482 clock-names = "xo";
485 rpmpd: power-controller {
486 compatible = "qcom,msm8996-rpmpd";
487 #power-domain-cells = <1>;
488 operating-points-v2 = <&rpmpd_opp_table>;
490 rpmpd_opp_table: opp-table {
491 compatible = "operating-points-v2";
494 opp-level = <1>;
498 opp-level = <2>;
502 opp-level = <3>;
506 opp-level = <4>;
510 opp-level = <5>;
514 opp-level = <6>;
522 reserved-memory {
523 #address-cells = <2>;
524 #size-cells = <2>;
529 no-map;
534 no-map;
537 smem_mem: smem-mem@86000000 {
539 no-map;
544 no-map;
548 compatible = "qcom,rmtfs-mem";
551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map;
554 qcom,client-id = <1>;
560 no-map;
565 no-map;
570 no-map;
574 compatible = "shared-dma-pool";
576 no-map;
581 no-map;
586 no-map;
589 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
592 no-map;
598 memory-region = <&smem_mem>;
602 smp2p-adsp {
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>;
613 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
618 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
621 interrupt-controller;
622 #interrupt-cells = <2>;
626 smp2p-mpss {
634 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>;
637 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells = <1>;
642 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "slave-kernel";
645 interrupt-controller;
646 #interrupt-cells = <2>;
650 smp2p-slpi {
658 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>;
661 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells = <1>;
666 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "slave-kernel";
669 interrupt-controller;
670 #interrupt-cells = <2>;
675 #address-cells = <1>;
676 #size-cells = <1>;
678 compatible = "simple-bus";
680 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm8996-qmp-pcie-phy";
683 #address-cells = <1>;
684 #size-cells = <1>;
690 clock-names = "aux", "cfg_ahb", "ref";
695 reset-names = "phy", "common", "cfg";
705 clock-names = "pipe0";
707 reset-names = "lane0";
709 #clock-cells = <0>;
710 clock-output-names = "pcie_0_pipe_clk_src";
712 #phy-cells = <0>;
721 clock-names = "pipe1";
723 reset-names = "lane1";
725 #clock-cells = <0>;
726 clock-output-names = "pcie_1_pipe_clk_src";
728 #phy-cells = <0>;
737 clock-names = "pipe2";
739 reset-names = "lane2";
741 #clock-cells = <0>;
742 clock-output-names = "pcie_2_pipe_clk_src";
744 #phy-cells = <0>;
749 compatible = "qcom,rpm-msg-ram";
754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
756 #address-cells = <1>;
757 #size-cells = <1>;
776 compatible = "qcom,prng-ee";
779 clock-names = "core";
782 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
799 clock-names = "cxo",
812 compatible = "qcom,msm8996-bimc";
814 #interconnect-cells = <1>;
817 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
824 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells = <1>;
828 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
835 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells = <1>;
839 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam-v1.7.0";
844 clock-names = "bam_clk";
845 #dma-cells = <1>;
847 qcom,controlled-remotely;
851 compatible = "qcom,crypto-v5.4";
856 clock-names = "iface", "bus", "core";
858 dma-names = "rx", "tx";
862 compatible = "qcom,msm8996-cnoc";
864 #interconnect-cells = <1>;
868 compatible = "qcom,msm8996-snoc";
870 #interconnect-cells = <1>;
874 compatible = "qcom,msm8996-a0noc";
876 #interconnect-cells = <1>;
877 clock-names = "aggre0_snoc_axi",
883 power-domains = <&gcc AGGRE0_NOC_GDSC>;
887 compatible = "qcom,msm8996-a1noc";
889 #interconnect-cells = <1>;
893 compatible = "qcom,msm8996-a2noc";
895 #interconnect-cells = <1>;
896 clock-names = "aggre2_ufs_axi", "ufs_axi";
902 compatible = "qcom,msm8996-mnoc";
904 #interconnect-cells = <1>;
905 clock-names = "iface";
910 compatible = "qcom,msm8996-pnoc";
912 #interconnect-cells = <1>;
916 compatible = "qcom,tcsr-mutex";
918 #hwlock-cells = <1>;
922 compatible = "qcom,tcsr-msm8996", "syscon";
927 compatible = "qcom,tcsr-msm8996", "syscon";
931 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>;
934 #reset-cells = <1>;
935 #power-domain-cells = <1>;
945 clock-names = "xo",
953 assigned-clocks = <&mmcc MMPLL9_PLL>,
958 assigned-clock-rates = <624000000>,
965 mdss: display-subsystem@900000 {
971 reg-names = "mdss_phys",
975 power-domains = <&mmcc MDSS_GDSC>;
978 interrupt-controller;
979 #interrupt-cells = <1>;
983 clock-names = "iface", "core";
985 #address-cells = <1>;
986 #size-cells = <1>;
991 mdp: display-controller@901000 {
992 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
994 reg-names = "mdp_phys";
996 interrupt-parent = <&mdss>;
1004 clock-names = "iface",
1012 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1014 assigned-clock-rates = <300000000>,
1020 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1029 remote-endpoint = <&mdss_hdmi_in>;
1036 remote-endpoint = <&mdss_dsi0_in>;
1043 remote-endpoint = <&mdss_dsi1_in>;
1050 compatible = "qcom,msm8996-dsi-ctrl",
1051 "qcom,mdss-dsi-ctrl";
1053 reg-names = "dsi_ctrl";
1055 interrupt-parent = <&mdss>;
1065 clock-names = "mdp_core",
1072 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1073 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1088 remote-endpoint = <&mdp5_intf1_out>;
1101 compatible = "qcom,dsi-phy-14nm";
1105 reg-names = "dsi_phy",
1109 #clock-cells = <1>;
1110 #phy-cells = <0>;
1113 clock-names = "iface", "ref";
1118 compatible = "qcom,msm8996-dsi-ctrl",
1119 "qcom,mdss-dsi-ctrl";
1121 reg-names = "dsi_ctrl";
1123 interrupt-parent = <&mdss>;
1133 clock-names = "mdp_core",
1140 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1141 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1156 remote-endpoint = <&mdp5_intf2_out>;
1169 compatible = "qcom,dsi-phy-14nm";
1173 reg-names = "dsi_phy",
1177 #clock-cells = <1>;
1178 #phy-cells = <0>;
1181 clock-names = "iface", "ref";
1185 mdss_hdmi: hdmi-tx@9a0000 {
1186 compatible = "qcom,hdmi-tx-8996";
1190 reg-names = "core_physical",
1194 interrupt-parent = <&mdss>;
1202 clock-names =
1210 #sound-dai-cells = <1>;
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 remote-endpoint = <&mdp5_intf3_out>;
1228 #phy-cells = <0>;
1229 compatible = "qcom,hdmi-phy-8996";
1236 reg-names = "hdmi_pll",
1246 clock-names = "iface",
1250 #clock-cells = <0>;
1257 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 reg-names = "kgsl_3d0_reg_memory";
1270 clock-names = "core",
1277 interconnect-names = "gfx-mem";
1279 power-domains = <&mmcc GPU_GX_GDSC>;
1282 nvmem-cells = <&speedbin_efuse>;
1283 nvmem-cell-names = "speed_bin";
1285 operating-points-v2 = <&gpu_opp_table>;
1289 #cooling-cells = <2>;
1291 gpu_opp_table: opp-table {
1292 compatible = "operating-points-v2";
1299 opp-624000000 {
1300 opp-hz = /bits/ 64 <624000000>;
1301 opp-supported-hw = <0x09>;
1303 opp-560000000 {
1304 opp-hz = /bits/ 64 <560000000>;
1305 opp-supported-hw = <0x0d>;
1307 opp-510000000 {
1308 opp-hz = /bits/ 64 <510000000>;
1309 opp-supported-hw = <0xff>;
1311 opp-401800000 {
1312 opp-hz = /bits/ 64 <401800000>;
1313 opp-supported-hw = <0xff>;
1315 opp-315000000 {
1316 opp-hz = /bits/ 64 <315000000>;
1317 opp-supported-hw = <0xff>;
1319 opp-214000000 {
1320 opp-hz = /bits/ 64 <214000000>;
1321 opp-supported-hw = <0xff>;
1323 opp-133000000 {
1324 opp-hz = /bits/ 64 <133000000>;
1325 opp-supported-hw = <0xff>;
1329 zap-shader {
1330 memory-region = <&gpu_mem>;
1335 compatible = "qcom,msm8996-pinctrl";
1338 gpio-controller;
1339 gpio-ranges = <&tlmm 0 0 150>;
1340 #gpio-cells = <2>;
1341 interrupt-controller;
1342 #interrupt-cells = <2>;
1344 blsp1_spi1_default: blsp1-spi1-default-state {
1345 spi-pins {
1348 drive-strength = <12>;
1349 bias-disable;
1352 cs-pins {
1355 drive-strength = <16>;
1356 bias-disable;
1357 output-high;
1361 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1364 drive-strength = <2>;
1365 bias-pull-down;
1368 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 drive-strength = <16>;
1372 bias-disable;
1375 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 drive-strength = <2>;
1379 bias-disable;
1382 blsp2_i2c2_default: blsp2-i2c2-state {
1385 drive-strength = <16>;
1386 bias-disable;
1389 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1392 drive-strength = <2>;
1393 bias-disable;
1396 blsp1_i2c6_default: blsp1-i2c6-state {
1399 drive-strength = <16>;
1400 bias-disable;
1403 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1406 drive-strength = <2>;
1407 bias-pull-up;
1410 cci0_default: cci0-default-state {
1413 drive-strength = <16>;
1414 bias-disable;
1418 camera_rear_default: camera-rear-default-state {
1419 camera0_mclk: mclk0-pins {
1422 drive-strength = <16>;
1423 bias-disable;
1426 camera0_rst: rst-pins {
1429 drive-strength = <16>;
1430 bias-disable;
1433 camera0_pwdn: pwdn-pins {
1436 drive-strength = <16>;
1437 bias-disable;
1441 cci1_default: cci1-default-state {
1444 drive-strength = <16>;
1445 bias-disable;
1449 camera_board_default: camera-board-default-state {
1450 mclk1-pins {
1453 drive-strength = <16>;
1454 bias-disable;
1457 pwdn-pins {
1460 drive-strength = <16>;
1461 bias-disable;
1464 rst-pins {
1467 drive-strength = <16>;
1468 bias-disable;
1473 camera_front_default: camera-front-default-state {
1474 camera2_mclk: mclk2-pins {
1477 drive-strength = <16>;
1478 bias-disable;
1481 camera2_rst: rst-pins {
1484 drive-strength = <16>;
1485 bias-disable;
1488 pwdn-pins {
1491 drive-strength = <16>;
1492 bias-disable;
1496 pcie0_state_on: pcie0-state-on-state {
1497 perst-pins {
1500 drive-strength = <2>;
1501 bias-pull-down;
1504 clkreq-pins {
1507 drive-strength = <2>;
1508 bias-pull-up;
1511 wake-pins {
1514 drive-strength = <2>;
1515 bias-pull-up;
1519 pcie0_state_off: pcie0-state-off-state {
1520 perst-pins {
1523 drive-strength = <2>;
1524 bias-pull-down;
1527 clkreq-pins {
1530 drive-strength = <2>;
1531 bias-disable;
1534 wake-pins {
1537 drive-strength = <2>;
1538 bias-disable;
1542 blsp1_uart2_default: blsp1-uart2-default-state {
1545 drive-strength = <16>;
1546 bias-disable;
1549 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1552 drive-strength = <2>;
1553 bias-disable;
1556 blsp1_i2c3_default: blsp1-i2c3-default-state {
1559 drive-strength = <16>;
1560 bias-disable;
1563 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1566 drive-strength = <2>;
1567 bias-disable;
1570 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1573 drive-strength = <16>;
1574 bias-disable;
1577 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1580 drive-strength = <2>;
1581 bias-disable;
1584 blsp2_i2c3_default: blsp2-i2c3-state-state {
1587 drive-strength = <16>;
1588 bias-disable;
1591 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1594 drive-strength = <2>;
1595 bias-disable;
1598 wcd_intr_default: wcd-intr-default-state {
1601 drive-strength = <2>;
1602 bias-pull-down;
1605 blsp2_i2c1_default: blsp2-i2c1-state {
1608 drive-strength = <16>;
1609 bias-disable;
1612 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1615 drive-strength = <2>;
1616 bias-disable;
1619 blsp2_i2c5_default: blsp2-i2c5-state {
1622 drive-strength = <2>;
1623 bias-disable;
1628 cdc_reset_active: cdc-reset-active-state {
1631 drive-strength = <16>;
1632 bias-pull-down;
1633 output-high;
1636 cdc_reset_sleep: cdc-reset-sleep-state {
1639 drive-strength = <16>;
1640 bias-disable;
1641 output-low;
1644 blsp2_spi6_default: blsp2-spi6-default-state {
1645 spi-pins {
1648 drive-strength = <12>;
1649 bias-disable;
1652 cs-pins {
1655 drive-strength = <16>;
1656 bias-disable;
1657 output-high;
1661 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1664 drive-strength = <2>;
1665 bias-pull-down;
1668 blsp2_i2c6_default: blsp2-i2c6-state {
1671 drive-strength = <16>;
1672 bias-disable;
1675 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1678 drive-strength = <2>;
1679 bias-disable;
1682 pcie1_state_on: pcie1-on-state {
1683 perst-pins {
1686 drive-strength = <2>;
1687 bias-pull-down;
1690 clkreq-pins {
1693 drive-strength = <2>;
1694 bias-pull-up;
1697 wake-pins {
1700 drive-strength = <2>;
1701 bias-pull-down;
1705 pcie1_state_off: pcie1-off-state {
1707 clkreq-pins {
1710 drive-strength = <2>;
1711 bias-disable;
1714 wake-pins {
1717 drive-strength = <2>;
1718 bias-disable;
1722 pcie2_state_on: pcie2-on-state {
1723 perst-pins {
1726 drive-strength = <2>;
1727 bias-pull-down;
1730 clkreq-pins {
1733 drive-strength = <2>;
1734 bias-pull-up;
1737 wake-pins {
1740 drive-strength = <2>;
1741 bias-pull-down;
1745 pcie2_state_off: pcie2-off-state {
1747 clkreq-pins {
1750 drive-strength = <2>;
1751 bias-disable;
1754 wake-pins {
1757 drive-strength = <2>;
1758 bias-disable;
1762 sdc1_state_on: sdc1-on-state {
1763 clk-pins {
1765 bias-disable;
1766 drive-strength = <16>;
1769 cmd-pins {
1771 bias-pull-up;
1772 drive-strength = <10>;
1775 data-pins {
1777 bias-pull-up;
1778 drive-strength = <10>;
1781 rclk-pins {
1783 bias-pull-down;
1787 sdc1_state_off: sdc1-off-state {
1788 clk-pins {
1790 bias-disable;
1791 drive-strength = <2>;
1794 cmd-pins {
1796 bias-pull-up;
1797 drive-strength = <2>;
1800 data-pins {
1802 bias-pull-up;
1803 drive-strength = <2>;
1806 rclk-pins {
1808 bias-pull-down;
1812 sdc2_state_on: sdc2-on-state {
1813 clk-pins {
1815 bias-disable;
1816 drive-strength = <16>;
1819 cmd-pins {
1821 bias-pull-up;
1822 drive-strength = <10>;
1825 data-pins {
1827 bias-pull-up;
1828 drive-strength = <10>;
1832 sdc2_state_off: sdc2-off-state {
1833 clk-pins {
1835 bias-disable;
1836 drive-strength = <2>;
1839 cmd-pins {
1841 bias-pull-up;
1842 drive-strength = <2>;
1845 data-pins {
1847 bias-pull-up;
1848 drive-strength = <2>;
1854 compatible = "qcom,rpm-stats";
1859 compatible = "qcom,spmi-pmic-arb";
1865 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1866 interrupt-names = "periph_irq";
1870 #address-cells = <2>;
1871 #size-cells = <0>;
1872 interrupt-controller;
1873 #interrupt-cells = <4>;
1877 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1878 compatible = "simple-pm-bus";
1879 #address-cells = <1>;
1880 #size-cells = <1>;
1884 compatible = "qcom,pcie-msm8996";
1886 power-domains = <&gcc PCIE0_GDSC>;
1887 bus-range = <0x00 0xff>;
1888 num-lanes = <1>;
1894 reg-names = "parf", "dbi", "elbi","config";
1897 phy-names = "pciephy";
1899 #address-cells = <3>;
1900 #size-cells = <2>;
1907 interrupt-names = "msi";
1908 #interrupt-cells = <1>;
1909 interrupt-map-mask = <0 0 0 0x7>;
1910 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1915 pinctrl-names = "default", "sleep";
1916 pinctrl-0 = <&pcie0_state_on>;
1917 pinctrl-1 = <&pcie0_state_off>;
1919 linux,pci-domain = <0>;
1927 clock-names = "pipe",
1935 compatible = "qcom,pcie-msm8996";
1936 power-domains = <&gcc PCIE1_GDSC>;
1937 bus-range = <0x00 0xff>;
1938 num-lanes = <1>;
1947 reg-names = "parf", "dbi", "elbi","config";
1950 phy-names = "pciephy";
1952 #address-cells = <3>;
1953 #size-cells = <2>;
1960 interrupt-names = "msi";
1961 #interrupt-cells = <1>;
1962 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1968 pinctrl-names = "default", "sleep";
1969 pinctrl-0 = <&pcie1_state_on>;
1970 pinctrl-1 = <&pcie1_state_off>;
1972 linux,pci-domain = <1>;
1980 clock-names = "pipe",
1988 compatible = "qcom,pcie-msm8996";
1989 power-domains = <&gcc PCIE2_GDSC>;
1990 bus-range = <0x00 0xff>;
1991 num-lanes = <1>;
1998 reg-names = "parf", "dbi", "elbi","config";
2001 phy-names = "pciephy";
2003 #address-cells = <3>;
2004 #size-cells = <2>;
2011 interrupt-names = "msi";
2012 #interrupt-cells = <1>;
2013 interrupt-map-mask = <0 0 0 0x7>;
2014 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2019 pinctrl-names = "default", "sleep";
2020 pinctrl-0 = <&pcie2_state_on>;
2021 pinctrl-1 = <&pcie2_state_off>;
2023 linux,pci-domain = <2>;
2030 clock-names = "pipe",
2039 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2040 "jedec,ufs-2.0";
2045 phy-names = "ufsphy";
2047 power-domains = <&gcc UFS_GDSC>;
2049 clock-names =
2073 freq-table-hz =
2088 interconnect-names = "ufs-ddr", "cpu-ufs";
2090 lanes-per-direction = <1>;
2091 #reset-cells = <1>;
2096 compatible = "qcom,msm8996-qmp-ufs-phy";
2100 clock-names = "ref";
2103 reset-names = "ufsphy";
2105 #clock-cells = <1>;
2106 #phy-cells = <0>;
2112 compatible = "qcom,msm8996-camss";
2127 reg-names = "csiphy0",
2151 interrupt-names = "csiphy0",
2161 power-domains = <&mmcc VFE0_GDSC>,
2199 clock-names = "top_ahb",
2241 #address-cells = <1>;
2242 #size-cells = <0>;
2247 compatible = "qcom,msm8996-cci";
2248 #address-cells = <1>;
2249 #size-cells = <0>;
2252 power-domains = <&mmcc CAMSS_GDSC>;
2257 clock-names = "camss_top_ahb",
2261 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2263 assigned-clock-rates = <80000000>, <37500000>;
2264 pinctrl-names = "default";
2265 pinctrl-0 = <&cci0_default &cci1_default>;
2268 cci_i2c0: i2c-bus@0 {
2270 clock-frequency = <400000>;
2271 #address-cells = <1>;
2272 #size-cells = <0>;
2275 cci_i2c1: i2c-bus@1 {
2277 clock-frequency = <400000>;
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2284 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2287 #global-interrupts = <1>;
2291 #iommu-cells = <1>;
2295 clock-names = "bus", "iface";
2297 power-domains = <&mmcc GPU_GDSC>;
2300 venus: video-codec@c00000 {
2301 compatible = "qcom,msm8996-venus";
2304 power-domains = <&mmcc VENUS_GDSC>;
2309 clock-names = "core", "iface", "bus", "mbus";
2312 interconnect-names = "video-mem", "cpu-cfg";
2333 memory-region = <&venus_mem>;
2336 video-decoder {
2337 compatible = "venus-decoder";
2339 clock-names = "core";
2340 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2343 video-encoder {
2344 compatible = "venus-encoder";
2346 clock-names = "core";
2347 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2352 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2355 #global-interrupts = <1>;
2359 #iommu-cells = <1>;
2362 clock-names = "bus", "iface";
2364 power-domains = <&mmcc MDSS_GDSC>;
2368 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2370 #global-interrupts = <1>;
2379 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2382 clock-names = "bus", "iface";
2383 #iommu-cells = <1>;
2388 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2391 #global-interrupts = <1>;
2395 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2398 clock-names = "bus", "iface";
2399 #iommu-cells = <1>;
2403 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2405 #iommu-cells = <1>;
2406 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2408 #global-interrupts = <1>;
2425 clock-names = "bus", "iface";
2429 compatible = "qcom,msm8996-slpi-pil";
2432 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2437 interrupt-names = "wdog",
2441 "stop-ack";
2444 clock-names = "xo";
2446 memory-region = <&slpi_mem>;
2448 qcom,smem-states = <&slpi_smp2p_out 0>;
2449 qcom,smem-state-names = "stop";
2451 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2452 power-domain-names = "ssc_cx";
2456 smd-edge {
2461 qcom,smd-edge = <3>;
2462 qcom,remote-pid = <3>;
2467 compatible = "qcom,msm8996-mss-pil";
2470 reg-names = "qdsp6", "rmb";
2472 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2478 interrupt-names = "wdog", "fatal", "ready",
2479 "handover", "stop-ack",
2480 "shutdown-ack";
2490 clock-names = "iface",
2500 reset-names = "mss_restart";
2502 power-domains = <&rpmpd MSM8996_VDDCX>,
2504 power-domain-names = "cx", "mx";
2506 qcom,smem-states = <&mpss_smp2p_out 0>;
2507 qcom,smem-state-names = "stop";
2509 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2514 memory-region = <&mba_mem>;
2518 memory-region = <&mpss_mem>;
2522 memory-region = <&mdata_mem>;
2525 smd-edge {
2530 qcom,smd-edge = <0>;
2531 qcom,remote-pid = <1>;
2536 compatible = "arm,coresight-stm", "arm,primecell";
2539 reg-names = "stm-base", "stm-stimulus-base";
2542 clock-names = "apb_pclk", "atclk";
2544 out-ports {
2547 remote-endpoint =
2555 compatible = "arm,coresight-tpiu", "arm,primecell";
2559 clock-names = "apb_pclk", "atclk";
2561 in-ports {
2564 remote-endpoint =
2572 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2576 clock-names = "apb_pclk", "atclk";
2578 in-ports {
2579 #address-cells = <1>;
2580 #size-cells = <0>;
2585 remote-endpoint =
2591 out-ports {
2594 remote-endpoint =
2602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2606 clock-names = "apb_pclk", "atclk";
2608 in-ports {
2609 #address-cells = <1>;
2610 #size-cells = <0>;
2615 remote-endpoint =
2621 out-ports {
2624 remote-endpoint =
2632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2636 clock-names = "apb_pclk", "atclk";
2638 in-ports {
2641 remote-endpoint =
2647 out-ports {
2650 remote-endpoint =
2658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2662 clock-names = "apb_pclk", "atclk";
2664 in-ports {
2665 #address-cells = <1>;
2666 #size-cells = <0>;
2671 remote-endpoint =
2679 remote-endpoint =
2687 remote-endpoint =
2693 out-ports {
2696 remote-endpoint =
2704 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2708 clock-names = "apb_pclk", "atclk";
2710 in-ports {
2713 remote-endpoint =
2719 out-ports {
2720 #address-cells = <1>;
2721 #size-cells = <0>;
2726 remote-endpoint =
2734 remote-endpoint =
2742 compatible = "arm,coresight-tmc", "arm,primecell";
2746 clock-names = "apb_pclk", "atclk";
2748 in-ports {
2751 remote-endpoint =
2757 out-ports {
2760 remote-endpoint =
2768 compatible = "arm,coresight-tmc", "arm,primecell";
2772 clock-names = "apb_pclk", "atclk";
2773 arm,scatter-gather;
2775 in-ports {
2778 remote-endpoint =
2786 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2790 clock-names = "apb_pclk";
2796 compatible = "arm,coresight-etm4x", "arm,primecell";
2800 clock-names = "apb_pclk", "atclk";
2804 out-ports {
2807 remote-endpoint =
2815 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2819 clock-names = "apb_pclk";
2825 compatible = "arm,coresight-etm4x", "arm,primecell";
2829 clock-names = "apb_pclk", "atclk";
2833 out-ports {
2836 remote-endpoint =
2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2848 clock-names = "apb_pclk", "atclk";
2850 in-ports {
2851 #address-cells = <1>;
2852 #size-cells = <0>;
2857 remote-endpoint = <&etm0_out>;
2864 remote-endpoint = <&etm1_out>;
2869 out-ports {
2872 remote-endpoint =
2880 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2884 clock-names = "apb_pclk";
2890 compatible = "arm,coresight-etm4x", "arm,primecell";
2894 clock-names = "apb_pclk", "atclk";
2898 out-ports {
2901 remote-endpoint =
2909 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2913 clock-names = "apb_pclk";
2919 compatible = "arm,coresight-etm4x", "arm,primecell";
2923 clock-names = "apb_pclk", "atclk";
2927 out-ports {
2930 remote-endpoint =
2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2942 clock-names = "apb_pclk", "atclk";
2944 in-ports {
2945 #address-cells = <1>;
2946 #size-cells = <0>;
2951 remote-endpoint = <&etm2_out>;
2958 remote-endpoint = <&etm3_out>;
2963 out-ports {
2966 remote-endpoint =
2974 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2978 clock-names = "apb_pclk", "atclk";
2980 in-ports {
2981 #address-cells = <1>;
2982 #size-cells = <0>;
2987 remote-endpoint =
2995 remote-endpoint =
3001 out-ports {
3004 remote-endpoint =
3011 kryocc: clock-controller@6400000 {
3012 compatible = "qcom,msm8996-apcc";
3015 clock-names = "xo", "sys_apcs_aux";
3018 #clock-cells = <1>;
3022 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3024 #address-cells = <1>;
3025 #size-cells = <1>;
3030 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3037 clock-names = "cfg_noc",
3043 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3045 assigned-clock-rates = <19200000>, <120000000>;
3049 interconnect-names = "usb-ddr", "apps-usb";
3051 power-domains = <&gcc USB30_GDSC>;
3059 phy-names = "usb2-phy", "usb3-phy";
3060 snps,hird-threshold = /bits/ 8 <0>;
3063 snps,is-utmi-l1-suspend;
3064 tx-fifo-resize;
3069 compatible = "qcom,msm8996-qmp-usb3-phy";
3076 clock-names = "aux",
3080 clock-output-names = "usb3_phy_pipe_clk_src";
3081 #clock-cells = <0>;
3082 #phy-cells = <0>;
3086 reset-names = "phy",
3093 compatible = "qcom,msm8996-qusb2-phy";
3095 #phy-cells = <0>;
3099 clock-names = "cfg_ahb", "ref";
3102 nvmem-cells = <&qusb2p_hstx_trim>;
3107 compatible = "qcom,msm8996-qusb2-phy";
3109 #phy-cells = <0>;
3113 clock-names = "cfg_ahb", "ref";
3116 nvmem-cells = <&qusb2s_hstx_trim>;
3121 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3123 reg-names = "hc", "core";
3127 interrupt-names = "hc_irq", "pwr_irq";
3129 clock-names = "iface", "core", "xo";
3135 pinctrl-names = "default", "sleep";
3136 pinctrl-0 = <&sdc1_state_on>;
3137 pinctrl-1 = <&sdc1_state_off>;
3139 bus-width = <8>;
3140 non-removable;
3145 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3147 reg-names = "hc", "core";
3151 interrupt-names = "hc_irq", "pwr_irq";
3153 clock-names = "iface", "core", "xo";
3159 pinctrl-names = "default", "sleep";
3160 pinctrl-0 = <&sdc2_state_on>;
3161 pinctrl-1 = <&sdc2_state_off>;
3163 bus-width = <4>;
3167 blsp1_dma: dma-controller@7544000 {
3168 compatible = "qcom,bam-v1.7.0";
3172 clock-names = "bam_clk";
3173 qcom,controlled-remotely;
3174 #dma-cells = <1>;
3179 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3184 clock-names = "core", "iface";
3185 pinctrl-names = "default", "sleep";
3186 pinctrl-0 = <&blsp1_uart2_default>;
3187 pinctrl-1 = <&blsp1_uart2_sleep>;
3189 dma-names = "tx", "rx";
3194 compatible = "qcom,spi-qup-v2.2.1";
3199 clock-names = "core", "iface";
3200 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&blsp1_spi1_default>;
3202 pinctrl-1 = <&blsp1_spi1_sleep>;
3204 dma-names = "tx", "rx";
3205 #address-cells = <1>;
3206 #size-cells = <0>;
3211 compatible = "qcom,i2c-qup-v2.2.1";
3216 clock-names = "core", "iface";
3217 pinctrl-names = "default", "sleep";
3218 pinctrl-0 = <&blsp1_i2c3_default>;
3219 pinctrl-1 = <&blsp1_i2c3_sleep>;
3221 dma-names = "tx", "rx";
3222 #address-cells = <1>;
3223 #size-cells = <0>;
3228 compatible = "qcom,i2c-qup-v2.2.1";
3233 clock-names = "core", "iface";
3234 pinctrl-names = "default", "sleep";
3235 pinctrl-0 = <&blsp1_i2c6_default>;
3236 pinctrl-1 = <&blsp1_i2c6_sleep>;
3238 dma-names = "tx", "rx";
3239 #address-cells = <1>;
3240 #size-cells = <0>;
3244 blsp2_dma: dma-controller@7584000 {
3245 compatible = "qcom,bam-v1.7.0";
3249 clock-names = "bam_clk";
3250 qcom,controlled-remotely;
3251 #dma-cells = <1>;
3256 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3261 clock-names = "core", "iface";
3266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3271 clock-names = "core", "iface";
3276 compatible = "qcom,i2c-qup-v2.2.1";
3281 clock-names = "core", "iface";
3282 pinctrl-names = "default", "sleep";
3283 pinctrl-0 = <&blsp2_i2c1_default>;
3284 pinctrl-1 = <&blsp2_i2c1_sleep>;
3286 dma-names = "tx", "rx";
3287 #address-cells = <1>;
3288 #size-cells = <0>;
3293 compatible = "qcom,i2c-qup-v2.2.1";
3298 clock-names = "core", "iface";
3299 pinctrl-names = "default", "sleep";
3300 pinctrl-0 = <&blsp2_i2c2_default>;
3301 pinctrl-1 = <&blsp2_i2c2_sleep>;
3303 dma-names = "tx", "rx";
3304 #address-cells = <1>;
3305 #size-cells = <0>;
3310 compatible = "qcom,i2c-qup-v2.2.1";
3315 clock-names = "core", "iface";
3316 clock-frequency = <400000>;
3317 pinctrl-names = "default", "sleep";
3318 pinctrl-0 = <&blsp2_i2c3_default>;
3319 pinctrl-1 = <&blsp2_i2c3_sleep>;
3321 dma-names = "tx", "rx";
3322 #address-cells = <1>;
3323 #size-cells = <0>;
3328 compatible = "qcom,i2c-qup-v2.2.1";
3333 clock-names = "core", "iface";
3334 pinctrl-names = "default";
3335 pinctrl-0 = <&blsp2_i2c5_default>;
3337 dma-names = "tx", "rx";
3338 #address-cells = <1>;
3339 #size-cells = <0>;
3344 compatible = "qcom,i2c-qup-v2.2.1";
3349 clock-names = "core", "iface";
3350 pinctrl-names = "default", "sleep";
3351 pinctrl-0 = <&blsp2_i2c6_default>;
3352 pinctrl-1 = <&blsp2_i2c6_sleep>;
3354 dma-names = "tx", "rx";
3355 #address-cells = <1>;
3356 #size-cells = <0>;
3361 compatible = "qcom,spi-qup-v2.2.1";
3366 clock-names = "core", "iface";
3367 pinctrl-names = "default", "sleep";
3368 pinctrl-0 = <&blsp2_spi6_default>;
3369 pinctrl-1 = <&blsp2_spi6_sleep>;
3371 dma-names = "tx", "rx";
3372 #address-cells = <1>;
3373 #size-cells = <0>;
3378 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3380 #address-cells = <1>;
3381 #size-cells = <1>;
3385 interrupt-names = "hs_phy_irq";
3392 clock-names = "cfg_noc",
3398 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3400 assigned-clock-rates = <19200000>, <60000000>;
3402 power-domains = <&gcc USB30_GDSC>;
3403 qcom,select-utmi-as-pipe-clk;
3411 phy-names = "usb2-phy";
3412 maximum-speed = "high-speed";
3418 slimbam: dma-controller@9184000 {
3419 compatible = "qcom,bam-v1.7.0";
3420 qcom,controlled-remotely;
3422 num-channels = <31>;
3424 #dma-cells = <1>;
3426 qcom,num-ees = <2>;
3429 slim_msm: slim-ngd@91c0000 {
3430 compatible = "qcom,slim-ngd-v1.5.0";
3434 dma-names = "rx", "tx";
3435 #address-cells = <1>;
3436 #size-cells = <0>;
3442 compatible = "qcom,msm8996-adsp-pil";
3445 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3450 interrupt-names = "wdog", "fatal", "ready",
3451 "handover", "stop-ack";
3454 clock-names = "xo";
3456 memory-region = <&adsp_mem>;
3458 qcom,smem-states = <&adsp_smp2p_out 0>;
3459 qcom,smem-state-names = "stop";
3461 power-domains = <&rpmpd MSM8996_VDDCX>;
3462 power-domain-names = "cx";
3466 smd-edge {
3471 qcom,smd-edge = <1>;
3472 qcom,remote-pid = <2>;
3475 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3476 compatible = "qcom,apr-v2";
3477 qcom,smd-channels = "apr_audio_svc";
3479 #address-cells = <1>;
3480 #size-cells = <0>;
3491 compatible = "qcom,q6afe-dais";
3492 #address-cells = <1>;
3493 #size-cells = <0>;
3494 #sound-dai-cells = <1>;
3505 compatible = "qcom,q6asm-dais";
3506 #address-cells = <1>;
3507 #size-cells = <0>;
3508 #sound-dai-cells = <1>;
3517 compatible = "qcom,q6adm-routing";
3518 #sound-dai-cells = <0>;
3526 compatible = "qcom,msm8996-apcs-hmss-global";
3529 #mbox-cells = <1>;
3530 #clock-cells = <0>;
3534 #address-cells = <1>;
3535 #size-cells = <1>;
3537 compatible = "arm,armv7-timer-mem";
3539 clock-frequency = <19200000>;
3542 frame-number = <0>;
3550 frame-number = <1>;
3557 frame-number = <2>;
3564 frame-number = <3>;
3571 frame-number = <4>;
3578 frame-number = <5>;
3585 frame-number = <6>;
3597 cbf: clock-controller@9a11000 {
3598 compatible = "qcom,msm8996-cbf";
3601 #clock-cells = <0>;
3602 #interconnect-cells = <1>;
3605 intc: interrupt-controller@9bc0000 {
3606 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3607 #interrupt-cells = <3>;
3608 interrupt-controller;
3609 #redistributor-regions = <1>;
3610 redistributor-stride = <0x0 0x40000>;
3620 thermal-zones {
3621 cpu0-thermal {
3622 polling-delay-passive = <250>;
3623 polling-delay = <1000>;
3625 thermal-sensors = <&tsens0 3>;
3628 cpu0_alert0: trip-point0 {
3634 cpu0_crit: cpu-crit {
3642 cpu1-thermal {
3643 polling-delay-passive = <250>;
3644 polling-delay = <1000>;
3646 thermal-sensors = <&tsens0 5>;
3649 cpu1_alert0: trip-point0 {
3655 cpu1_crit: cpu-crit {
3663 cpu2-thermal {
3664 polling-delay-passive = <250>;
3665 polling-delay = <1000>;
3667 thermal-sensors = <&tsens0 8>;
3670 cpu2_alert0: trip-point0 {
3676 cpu2_crit: cpu-crit {
3684 cpu3-thermal {
3685 polling-delay-passive = <250>;
3686 polling-delay = <1000>;
3688 thermal-sensors = <&tsens0 10>;
3691 cpu3_alert0: trip-point0 {
3697 cpu3_crit: cpu-crit {
3705 gpu-top-thermal {
3706 polling-delay-passive = <250>;
3707 polling-delay = <1000>;
3709 thermal-sensors = <&tsens1 6>;
3712 gpu1_alert0: trip-point0 {
3719 cooling-maps {
3722 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3727 gpu-bottom-thermal {
3728 polling-delay-passive = <250>;
3729 polling-delay = <1000>;
3731 thermal-sensors = <&tsens1 7>;
3734 gpu2_alert0: trip-point0 {
3741 cooling-maps {
3744 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3749 m4m-thermal {
3750 polling-delay-passive = <250>;
3751 polling-delay = <1000>;
3753 thermal-sensors = <&tsens0 1>;
3756 m4m_alert0: trip-point0 {
3764 l3-or-venus-thermal {
3765 polling-delay-passive = <250>;
3766 polling-delay = <1000>;
3768 thermal-sensors = <&tsens0 2>;
3771 l3_or_venus_alert0: trip-point0 {
3779 cluster0-l2-thermal {
3780 polling-delay-passive = <250>;
3781 polling-delay = <1000>;
3783 thermal-sensors = <&tsens0 7>;
3786 cluster0_l2_alert0: trip-point0 {
3794 cluster1-l2-thermal {
3795 polling-delay-passive = <250>;
3796 polling-delay = <1000>;
3798 thermal-sensors = <&tsens0 12>;
3801 cluster1_l2_alert0: trip-point0 {
3809 camera-thermal {
3810 polling-delay-passive = <250>;
3811 polling-delay = <1000>;
3813 thermal-sensors = <&tsens1 1>;
3816 camera_alert0: trip-point0 {
3824 q6-dsp-thermal {
3825 polling-delay-passive = <250>;
3826 polling-delay = <1000>;
3828 thermal-sensors = <&tsens1 2>;
3831 q6_dsp_alert0: trip-point0 {
3839 mem-thermal {
3840 polling-delay-passive = <250>;
3841 polling-delay = <1000>;
3843 thermal-sensors = <&tsens1 3>;
3846 mem_alert0: trip-point0 {
3854 modemtx-thermal {
3855 polling-delay-passive = <250>;
3856 polling-delay = <1000>;
3858 thermal-sensors = <&tsens1 4>;
3861 modemtx_alert0: trip-point0 {
3871 compatible = "arm,armv8-timer";