Lines Matching +full:0 +full:x00a30c00
29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
53 clocks = <&kryocc 0>;
68 reg = <0x0 0x1>;
72 clocks = <&kryocc 0>;
82 reg = <0x0 0x100>;
101 reg = <0x0 0x101>;
137 CPU_SLEEP_0: cpu-sleep-0 {
140 arm,psci-suspend-param = <0x00000004>;
156 opp-supported-hw = <0xf>;
162 opp-supported-hw = <0xf>;
168 opp-supported-hw = <0xf>;
174 opp-supported-hw = <0xf>;
180 opp-supported-hw = <0xf>;
186 opp-supported-hw = <0xf>;
192 opp-supported-hw = <0xf>;
198 opp-supported-hw = <0xf>;
204 opp-supported-hw = <0xf>;
210 opp-supported-hw = <0xf>;
216 opp-supported-hw = <0xf>;
222 opp-supported-hw = <0xf>;
228 opp-supported-hw = <0xd>;
234 opp-supported-hw = <0x2>;
240 opp-supported-hw = <0xd>;
246 opp-supported-hw = <0x9>;
252 opp-supported-hw = <0x04>;
258 opp-supported-hw = <0x9>;
272 opp-supported-hw = <0xf>;
278 opp-supported-hw = <0xf>;
284 opp-supported-hw = <0xf>;
290 opp-supported-hw = <0xf>;
296 opp-supported-hw = <0xf>;
302 opp-supported-hw = <0xf>;
308 opp-supported-hw = <0xf>;
314 opp-supported-hw = <0xf>;
320 opp-supported-hw = <0xf>;
326 opp-supported-hw = <0xf>;
332 opp-supported-hw = <0xf>;
338 opp-supported-hw = <0xf>;
344 opp-supported-hw = <0xf>;
350 opp-supported-hw = <0xf>;
356 opp-supported-hw = <0xf>;
362 opp-supported-hw = <0xf>;
368 opp-supported-hw = <0xf>;
374 opp-supported-hw = <0xf>;
380 opp-supported-hw = <0xf>;
386 opp-supported-hw = <0xf>;
392 opp-supported-hw = <0xe>;
398 opp-supported-hw = <0x1>;
404 opp-supported-hw = <0x4>;
410 opp-supported-hw = <0x1>;
416 opp-supported-hw = <0x1>;
422 opp-supported-hw = <0x1>;
428 opp-supported-hw = <0x1>;
437 qcom,dload-mode = <&tcsr_2 0x13000>;
444 reg = <0x0 0x80000000 0x0 0x0>;
472 mboxes = <&apcs_glb 0>;
528 reg = <0x0 0x85800000 0x0 0x600000>;
533 reg = <0x0 0x85e00000 0x0 0x200000>;
538 reg = <0x0 0x86000000 0x0 0x200000>;
543 reg = <0x0 0x86200000 0x0 0x2600000>;
550 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
559 reg = <0x0 0x88800000 0x0 0x6200000>;
564 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
569 reg = <0x0 0x90500000 0x0 0xa00000>;
575 reg = <0x0 0x90f00000 0x0 0x100000>;
580 reg = <0x0 0x91000000 0x0 0x500000>;
585 reg = <0x0 0x91500000 0x0 0x200000>;
590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>;
610 qcom,local-pid = <0>;
634 qcom,local-pid = <0>;
658 qcom,local-pid = <0>;
674 soc: soc@0 {
677 ranges = <0 0 0 0xffffffff>;
682 reg = <0x00034000 0x488>;
685 ranges = <0x0 0x00034000 0x4000>;
700 reg = <0x1000 0x130>,
701 <0x1200 0x200>,
702 <0x1400 0x1dc>;
709 #clock-cells = <0>;
712 #phy-cells = <0>;
716 reg = <0x2000 0x130>,
717 <0x2200 0x200>,
718 <0x2400 0x1dc>;
725 #clock-cells = <0>;
728 #phy-cells = <0>;
732 reg = <0x3000 0x130>,
733 <0x3200 0x200>,
734 <0x3400 0x1dc>;
741 #clock-cells = <0>;
744 #phy-cells = <0>;
750 reg = <0x00068000 0x6000>;
755 reg = <0x00074000 0x8ff>;
760 reg = <0x24e 0x2>;
765 reg = <0x24f 0x1>;
770 reg = <0x133 0x1>;
777 reg = <0x00083000 0x1000>;
787 reg = <0x00300000 0x90000>;
796 <&ufsphy 0>,
813 reg = <0x00408000 0x5a000>;
819 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x1000>; /* SROT */
830 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x1000>; /* SROT */
841 reg = <0x00644000 0x24000>;
846 qcom,ee = <0>;
852 reg = <0x0067a000 0x6000>;
863 reg = <0x00500000 0x1000>;
869 reg = <0x00524000 0x1c000>;
875 reg = <0x00543000 0x6000>;
888 reg = <0x00562000 0x5000>;
894 reg = <0x00583000 0x7000>;
903 reg = <0x005a4000 0x1c000>;
911 reg = <0x005c0000 0x3000>;
917 reg = <0x00740000 0x20000>;
923 reg = <0x00760000 0x20000>;
928 reg = <0x007a0000 0x18000>;
936 reg = <0x008c0000 0x40000>;
941 <&mdss_dsi0_phy 0>,
943 <&mdss_dsi1_phy 0>,
968 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x1040>,
970 <0x009b8000 0x1040>;
993 reg = <0x00901000 0x90000>;
997 interrupts = <0>;
1010 iommus = <&mdp_smmu 0>;
1024 #size-cells = <0>;
1026 port@0 {
1027 reg = <0>;
1052 reg = <0x00994000 0x400>;
1073 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1079 #size-cells = <0>;
1083 #size-cells = <0>;
1085 port@0 {
1086 reg = <0>;
1102 reg = <0x00994400 0x100>,
1103 <0x00994500 0x300>,
1104 <0x00994800 0x188>;
1110 #phy-cells = <0>;
1120 reg = <0x00996000 0x400>;
1141 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1147 #size-cells = <0>;
1151 #size-cells = <0>;
1153 port@0 {
1154 reg = <0>;
1170 reg = <0x00996400 0x100>,
1171 <0x00996500 0x300>,
1172 <0x00996800 0x188>;
1178 #phy-cells = <0>;
1187 reg = <0x009a0000 0x50c>,
1188 <0x00070000 0x6158>,
1189 <0x009e0000 0xfff>;
1216 #size-cells = <0>;
1218 port@0 {
1219 reg = <0>;
1228 #phy-cells = <0>;
1230 reg = <0x009a0600 0x1c4>,
1231 <0x009a0a00 0x124>,
1232 <0x009a0c00 0x124>,
1233 <0x009a0e00 0x124>,
1234 <0x009a1000 0x124>,
1235 <0x009a1200 0x0c8>;
1250 #clock-cells = <0>;
1259 reg = <0x00b00000 0x3f000>;
1280 iommus = <&adreno_smmu 0>;
1295 * 624Mhz is only available on speed bins 0 and 3.
1296 * 560Mhz is only available on speed bins 0, 2 and 3.
1301 opp-supported-hw = <0x09>;
1305 opp-supported-hw = <0x0d>;
1309 opp-supported-hw = <0xff>;
1313 opp-supported-hw = <0xff>;
1317 opp-supported-hw = <0xff>;
1321 opp-supported-hw = <0xff>;
1325 opp-supported-hw = <0xff>;
1336 reg = <0x01010000 0x300000>;
1339 gpio-ranges = <&tlmm 0 0 150>;
1855 reg = <0x00290000 0x10000>;
1860 reg = <0x0400f000 0x1000>,
1861 <0x04400000 0x800000>,
1862 <0x04c00000 0x800000>,
1863 <0x05800000 0x200000>,
1864 <0x0400a000 0x002100>;
1868 qcom,ee = <0>;
1869 qcom,channel = <0>;
1871 #size-cells = <0>;
1876 bus@0 {
1881 ranges = <0x0 0x0 0xffffffff>;
1887 bus-range = <0x00 0xff>;
1890 reg = <0x00600000 0x2000>,
1891 <0x0c000000 0xf1d>,
1892 <0x0c000f20 0xa8>,
1893 <0x0c100000 0x100000>;
1901 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1902 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1909 interrupt-map-mask = <0 0 0 0x7>;
1910 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1911 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1912 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1913 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 pinctrl-0 = <&pcie0_state_on>;
1919 linux,pci-domain = <0>;
1937 bus-range = <0x00 0xff>;
1942 reg = <0x00608000 0x2000>,
1943 <0x0d000000 0xf1d>,
1944 <0x0d000f20 0xa8>,
1945 <0x0d100000 0x100000>;
1954 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1955 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1962 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1969 pinctrl-0 = <&pcie1_state_on>;
1990 bus-range = <0x00 0xff>;
1993 reg = <0x00610000 0x2000>,
1994 <0x0e000000 0xf1d>,
1995 <0x0e000f20 0xa8>,
1996 <0x0e100000 0x100000>;
2005 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2006 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2013 interrupt-map-mask = <0 0 0 0x7>;
2014 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2015 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2016 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2017 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2020 pinctrl-0 = <&pcie2_state_on>;
2041 reg = <0x00624000 0x2500>;
2075 <0 0>,
2076 <0 0>,
2077 <0 0>,
2078 <0 0>,
2080 <0 0>,
2081 <0 0>,
2082 <0 0>,
2083 <0 0>,
2084 <0 0>;
2097 reg = <0x00627000 0x1000>;
2102 resets = <&ufshc 0>;
2106 #phy-cells = <0>;
2113 reg = <0x00a34000 0x1000>,
2114 <0x00a00030 0x4>,
2115 <0x00a35000 0x1000>,
2116 <0x00a00038 0x4>,
2117 <0x00a36000 0x1000>,
2118 <0x00a00040 0x4>,
2119 <0x00a30000 0x100>,
2120 <0x00a30400 0x100>,
2121 <0x00a30800 0x100>,
2122 <0x00a30c00 0x100>,
2123 <0x00a31000 0x500>,
2124 <0x00a00020 0x10>,
2125 <0x00a10000 0x1000>,
2126 <0x00a14000 0x1000>;
2235 iommus = <&vfe_smmu 0>,
2242 #size-cells = <0>;
2249 #size-cells = <0>;
2250 reg = <0xa0c000 0x1000>;
2265 pinctrl-0 = <&cci0_default &cci1_default>;
2268 cci_i2c0: i2c-bus@0 {
2269 reg = <0>;
2272 #size-cells = <0>;
2279 #size-cells = <0>;
2285 reg = <0x00b40000 0x10000>;
2302 reg = <0x00c00000 0xff000>;
2313 iommus = <&venus_smmu 0x00>,
2314 <&venus_smmu 0x01>,
2315 <&venus_smmu 0x0a>,
2316 <&venus_smmu 0x07>,
2317 <&venus_smmu 0x0e>,
2318 <&venus_smmu 0x0f>,
2319 <&venus_smmu 0x08>,
2320 <&venus_smmu 0x09>,
2321 <&venus_smmu 0x0b>,
2322 <&venus_smmu 0x0c>,
2323 <&venus_smmu 0x0d>,
2324 <&venus_smmu 0x10>,
2325 <&venus_smmu 0x11>,
2326 <&venus_smmu 0x21>,
2327 <&venus_smmu 0x28>,
2328 <&venus_smmu 0x29>,
2329 <&venus_smmu 0x2b>,
2330 <&venus_smmu 0x2c>,
2331 <&venus_smmu 0x2d>,
2332 <&venus_smmu 0x31>;
2353 reg = <0x00d00000 0x10000>;
2369 reg = <0x00d40000 0x20000>;
2389 reg = <0x00da0000 0x10000>;
2404 reg = <0x01600000 0x20000>;
2430 reg = <0x01c00000 0x4000>;
2432 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2433 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2448 qcom,smem-states = <&slpi_smp2p_out 0>;
2468 reg = <0x2080000 0x100>,
2469 <0x2180000 0x020>;
2472 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2473 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2506 qcom,smem-states = <&mpss_smp2p_out 0>;
2509 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2530 qcom,smd-edge = <0>;
2537 reg = <0x3002000 0x1000>,
2538 <0x8280000 0x180000>;
2556 reg = <0x3020000 0x1000>;
2573 reg = <0x3021000 0x1000>;
2580 #size-cells = <0>;
2603 reg = <0x3022000 0x1000>;
2610 #size-cells = <0>;
2633 reg = <0x3023000 0x1000>;
2659 reg = <0x3025000 0x1000>;
2666 #size-cells = <0>;
2668 port@0 {
2669 reg = <0>;
2705 reg = <0x3026000 0x1000>;
2721 #size-cells = <0>;
2723 port@0 {
2724 reg = <0>;
2743 reg = <0x3027000 0x1000>;
2769 reg = <0x3028000 0x1000>;
2787 reg = <0x3810000 0x1000>;
2797 reg = <0x3840000 0x1000>;
2816 reg = <0x3910000 0x1000>;
2826 reg = <0x3940000 0x1000>;
2843 funnel@39b0000 { /* APSS Funnel 0 */
2845 reg = <0x39b0000 0x1000>;
2852 #size-cells = <0>;
2854 port@0 {
2855 reg = <0>;
2881 reg = <0x3a10000 0x1000>;
2891 reg = <0x3a40000 0x1000>;
2910 reg = <0x3b10000 0x1000>;
2920 reg = <0x3b40000 0x1000>;
2939 reg = <0x3bb0000 0x1000>;
2946 #size-cells = <0>;
2948 port@0 {
2949 reg = <0>;
2975 reg = <0x3bc0000 0x1000>;
2982 #size-cells = <0>;
2984 port@0 {
2985 reg = <0>;
3013 reg = <0x06400000 0x90000>;
3023 reg = <0x06af8800 0x400>;
3056 reg = <0x06a00000 0xcc00>;
3060 snps,hird-threshold = /bits/ 8 <0>;
3070 reg = <0x07410000 0x1000>;
3081 #clock-cells = <0>;
3082 #phy-cells = <0>;
3094 reg = <0x07411000 0x180>;
3095 #phy-cells = <0>;
3108 reg = <0x07412000 0x180>;
3109 #phy-cells = <0>;
3122 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3136 pinctrl-0 = <&sdc1_state_on>;
3146 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3160 pinctrl-0 = <&sdc2_state_on>;
3169 reg = <0x07544000 0x2b000>;
3175 qcom,ee = <0>;
3180 reg = <0x07570000 0x1000>;
3186 pinctrl-0 = <&blsp1_uart2_default>;
3195 reg = <0x07575000 0x600>;
3201 pinctrl-0 = <&blsp1_spi1_default>;
3206 #size-cells = <0>;
3212 reg = <0x07577000 0x1000>;
3218 pinctrl-0 = <&blsp1_i2c3_default>;
3223 #size-cells = <0>;
3229 reg = <0x757a000 0x1000>;
3235 pinctrl-0 = <&blsp1_i2c6_default>;
3240 #size-cells = <0>;
3246 reg = <0x07584000 0x2b000>;
3252 qcom,ee = <0>;
3257 reg = <0x075b0000 0x1000>;
3267 reg = <0x075b1000 0x1000>;
3277 reg = <0x075b5000 0x1000>;
3283 pinctrl-0 = <&blsp2_i2c1_default>;
3288 #size-cells = <0>;
3294 reg = <0x075b6000 0x1000>;
3300 pinctrl-0 = <&blsp2_i2c2_default>;
3305 #size-cells = <0>;
3311 reg = <0x075b7000 0x1000>;
3318 pinctrl-0 = <&blsp2_i2c3_default>;
3323 #size-cells = <0>;
3329 reg = <0x75b9000 0x1000>;
3335 pinctrl-0 = <&blsp2_i2c5_default>;
3339 #size-cells = <0>;
3345 reg = <0x75ba000 0x1000>;
3351 pinctrl-0 = <&blsp2_i2c6_default>;
3356 #size-cells = <0>;
3362 reg = <0x075ba000 0x600>;
3368 pinctrl-0 = <&blsp2_spi6_default>;
3373 #size-cells = <0>;
3379 reg = <0x076f8800 0x400>;
3408 reg = <0x07600000 0xcc00>;
3421 reg = <0x09184000 0x32000>;
3431 reg = <0x091c0000 0x2c000>;
3436 #size-cells = <0>;
3443 reg = <0x09300000 0x80000>;
3445 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3446 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3458 qcom,smem-states = <&adsp_smp2p_out 0>;
3480 #size-cells = <0>;
3493 #size-cells = <0>;
3507 #size-cells = <0>;
3518 #sound-dai-cells = <0>;
3527 reg = <0x09820000 0x1000>;
3530 #clock-cells = <0>;
3538 reg = <0x09840000 0x1000>;
3542 frame-number = <0>;
3545 reg = <0x09850000 0x1000>,
3546 <0x09860000 0x1000>;
3552 reg = <0x09870000 0x1000>;
3559 reg = <0x09880000 0x1000>;
3566 reg = <0x09890000 0x1000>;
3573 reg = <0x098a0000 0x1000>;
3580 reg = <0x098b0000 0x1000>;
3587 reg = <0x098c0000 0x1000>;
3594 reg = <0x09a10000 0x1000>;
3599 reg = <0x09a11000 0x10000>;
3601 #clock-cells = <0>;
3610 redistributor-stride = <0x0 0x40000>;
3611 reg = <0x09bc0000 0x10000>,
3612 <0x09c00000 0x100000>;