Lines Matching +full:disable +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32768>;
38 clock-output-names = "sleep_clk";
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
52 L2_0: l2-cache {
54 cache-level = <2>;
55 cache-unified;
61 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 next-level-cache = <&L2_0>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 next-level-cache = <&L2_0>;
77 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
85 compatible = "arm,cortex-a57";
87 enable-method = "psci";
88 next-level-cache = <&L2_1>;
89 L2_1: l2-cache {
91 cache-level = <2>;
92 cache-unified;
98 compatible = "arm,cortex-a57";
100 enable-method = "psci";
101 next-level-cache = <&L2_1>;
106 compatible = "arm,cortex-a57";
108 enable-method = "psci";
109 next-level-cache = <&L2_1>;
114 compatible = "arm,cortex-a57";
116 enable-method = "psci";
117 next-level-cache = <&L2_1>;
120 cpu-map {
161 compatible = "qcom,scm-msm8994", "qcom,scm";
172 compatible = "arm,cortex-a53-pmu";
177 compatible = "arm,psci-0.2";
182 compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";
184 smd-edge {
187 qcom,smd-edge = <15>;
188 qcom,remote-pid = <6>;
190 rpm_requests: rpm-requests {
191 compatible = "qcom,rpm-msm8994";
192 qcom,smd-channels = "rpm_requests";
194 rpmcc: clock-controller {
195 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
196 #clock-cells = <1>;
199 rpmpd: power-controller {
200 compatible = "qcom,msm8994-rpmpd";
201 #power-domain-cells = <1>;
202 operating-points-v2 = <&rpmpd_opp_table>;
204 rpmpd_opp_table: opp-table {
205 compatible = "operating-points-v2";
208 opp-level = <1>;
211 opp-level = <2>;
214 opp-level = <3>;
217 opp-level = <4>;
220 opp-level = <5>;
223 opp-level = <6>;
231 reserved-memory {
232 #address-cells = <2>;
233 #size-cells = <2>;
238 no-map;
243 no-map;
248 no-map;
253 no-map;
258 no-map;
262 compatible = "qcom,rmtfs-mem";
264 no-map;
266 qcom,client-id = <1>;
271 no-map;
276 no-map;
281 no-map;
286 no-map;
292 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_ram>;
297 smp2p-lpass {
305 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>;
308 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells = <1>;
313 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "slave-kernel";
316 interrupt-controller;
317 #interrupt-cells = <2>;
321 smp2p-modem {
325 interrupt-parent = <&intc>;
330 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>;
333 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells = <1>;
338 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "slave-kernel";
341 interrupt-controller;
342 #interrupt-cells = <2>;
347 #address-cells = <1>;
348 #size-cells = <1>;
350 compatible = "simple-bus";
352 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm-qgic2";
354 interrupt-controller;
355 #interrupt-cells = <3>;
361 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
363 #mbox-cells = <1>;
367 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
372 timeout-sec = <10>;
376 #address-cells = <1>;
377 #size-cells = <1>;
379 compatible = "arm,armv7-timer-mem";
383 frame-number = <0>;
391 frame-number = <1>;
398 frame-number = <2>;
405 frame-number = <3>;
412 frame-number = <4>;
419 frame-number = <5>;
426 frame-number = <6>;
434 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
436 #address-cells = <1>;
437 #size-cells = <1>;
444 clock-names = "core",
449 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
451 assigned-clock-rates = <19200000>, <120000000>;
453 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pipe-clk;
462 maximum-speed = "high-speed";
468 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
470 reg-names = "hc", "core";
474 interrupt-names = "hc_irq", "pwr_irq";
479 clock-names = "iface", "core", "xo";
481 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
485 bus-width = <8>;
486 non-removable;
491 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
493 reg-names = "hc", "core";
497 interrupt-names = "hc_irq", "pwr_irq";
502 clock-names = "iface", "core", "xo";
504 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
508 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
509 bus-width = <4>;
513 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam-v1.7.0";
518 clock-names = "bam_clk";
519 #dma-cells = <1>;
521 qcom,controlled-remotely;
522 num-channels = <24>;
523 qcom,num-ees = <4>;
527 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
530 clock-names = "core", "iface";
533 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_uart2_sleep>;
540 compatible = "qcom,i2c-qup-v2.2.1";
545 clock-names = "core", "iface";
546 clock-frequency = <400000>;
548 dma-names = "tx", "rx";
549 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>;
553 #size-cells = <0>;
558 compatible = "qcom,spi-qup-v2.2.1";
563 clock-names = "core", "iface";
565 dma-names = "tx", "rx";
566 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>;
570 #size-cells = <0>;
575 compatible = "qcom,i2c-qup-v2.2.1";
580 clock-names = "core", "iface";
581 clock-frequency = <400000>;
583 dma-names = "tx", "rx";
584 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>;
588 #size-cells = <0>;
595 compatible = "qcom,i2c-qup-v2.2.1";
600 clock-names = "core", "iface";
601 clock-frequency = <400000>;
603 dma-names = "tx", "rx";
604 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>;
608 #size-cells = <0>;
613 compatible = "qcom,i2c-qup-v2.2.1";
618 clock-names = "core", "iface";
619 clock-frequency = <400000>;
621 dma-names = "tx", "rx";
622 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>;
626 #size-cells = <0>;
631 compatible = "qcom,i2c-qup-v2.2.1";
636 clock-names = "core", "iface";
637 clock-frequency = <400000>;
639 dma-names = "tx", "rx";
640 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>;
644 #size-cells = <0>;
648 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam-v1.7.0";
653 clock-names = "bam_clk";
654 #dma-cells = <1>;
656 qcom,controlled-remotely;
657 num-channels = <24>;
658 qcom,num-ees = <4>;
662 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
665 clock-names = "core", "iface";
669 dma-names = "tx", "rx";
670 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_uart2_sleep>;
677 compatible = "qcom,i2c-qup-v2.2.1";
682 clock-names = "core", "iface";
683 clock-frequency = <400000>;
685 dma-names = "tx", "rx";
686 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>;
690 #size-cells = <0>;
695 compatible = "qcom,spi-qup-v2.2.1";
700 clock-names = "core", "iface";
702 dma-names = "tx", "rx";
703 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>;
707 #size-cells = <0>;
712 compatible = "qcom,i2c-qup-v2.2.1";
717 clock-names = "core", "iface";
718 clock-frequency = <355000>;
720 dma-names = "tx", "rx";
721 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>;
725 #size-cells = <0>;
729 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>;
732 #reset-cells = <1>;
733 #power-domain-cells = <1>;
736 clock-names = "xo", "sleep";
741 compatible = "qcom,rpm-msg-ram";
751 compatible = "qcom,spmi-pmic-arb";
755 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "periph_irq";
760 #address-cells = <2>;
761 #size-cells = <0>;
762 interrupt-controller;
763 #interrupt-cells = <4>;
767 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
769 #hwlock-cells = <1>;
773 compatible = "qcom,msm8994-pinctrl";
776 gpio-controller;
777 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>;
779 interrupt-controller;
780 #interrupt-cells = <2>;
782 blsp1_uart2_default: blsp1-uart2-default-state {
785 drive-strength = <16>;
786 bias-disable;
789 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
792 drive-strength = <2>;
793 bias-pull-down;
796 blsp2_uart2_default: blsp2-uart2-default-state {
799 drive-strength = <16>;
800 bias-disable;
803 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
806 drive-strength = <2>;
807 bias-disable;
810 i2c1_default: i2c1-default-state {
813 drive-strength = <2>;
814 bias-disable;
817 i2c1_sleep: i2c1-sleep-state {
820 drive-strength = <2>;
821 bias-disable;
824 i2c2_default: i2c2-default-state {
827 drive-strength = <2>;
828 bias-disable;
831 i2c2_sleep: i2c2-sleep-state {
834 drive-strength = <2>;
835 bias-disable;
838 i2c4_default: i2c4-default-state {
841 drive-strength = <2>;
842 bias-disable;
845 i2c4_sleep: i2c4-sleep-state {
848 drive-strength = <2>;
849 bias-pull-down;
852 i2c5_default: i2c5-default-state {
855 drive-strength = <2>;
856 bias-disable;
859 i2c5_sleep: i2c5-sleep-state {
862 drive-strength = <2>;
863 bias-disable;
866 i2c6_default: i2c6-default-state {
869 drive-strength = <2>;
870 bias-disable;
873 i2c6_sleep: i2c6-sleep-state {
876 drive-strength = <2>;
877 bias-disable;
880 i2c7_default: i2c7-default-state {
883 drive-strength = <2>;
884 bias-disable;
887 i2c7_sleep: i2c7-sleep-state {
890 drive-strength = <2>;
891 bias-disable;
894 blsp2_spi10_default: blsp2-spi10-default-state {
895 default-pins {
898 drive-strength = <10>;
899 bias-pull-down;
902 cs-pins {
905 drive-strength = <2>;
906 bias-disable;
910 blsp2_spi10_sleep: blsp2-spi10-sleep-state {
913 drive-strength = <2>;
914 bias-disable;
917 i2c11_default: i2c11-default-state {
920 drive-strength = <2>;
921 bias-disable;
924 i2c11_sleep: i2c11-sleep-state {
927 drive-strength = <2>;
928 bias-disable;
931 blsp1_spi1_default: blsp1-spi1-default-state {
932 default-pins {
935 drive-strength = <10>;
936 bias-pull-down;
939 cs-pins {
942 drive-strength = <2>;
943 bias-disable;
947 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
950 drive-strength = <2>;
951 bias-disable;
954 sdc1_clk_on: clk-on-state {
956 bias-disable;
957 drive-strength = <16>;
960 sdc1_clk_off: clk-off-state {
962 bias-disable;
963 drive-strength = <2>;
966 sdc1_cmd_on: cmd-on-state {
968 bias-pull-up;
969 drive-strength = <8>;
972 sdc1_cmd_off: cmd-off-state {
974 bias-pull-up;
975 drive-strength = <2>;
978 sdc1_data_on: data-on-state {
980 bias-pull-up;
981 drive-strength = <8>;
984 sdc1_data_off: data-off-state {
986 bias-pull-up;
987 drive-strength = <2>;
990 sdc1_rclk_on: rclk-on-state {
992 bias-pull-down;
995 sdc1_rclk_off: rclk-off-state {
997 bias-pull-down;
1000 sdc2_clk_on: sdc2-clk-on-state {
1002 bias-disable;
1003 drive-strength = <10>;
1006 sdc2_clk_off: sdc2-clk-off-state {
1008 bias-disable;
1009 drive-strength = <2>;
1012 sdc2_cmd_on: sdc2-cmd-on-state {
1014 bias-pull-up;
1015 drive-strength = <10>;
1018 sdc2_cmd_off: sdc2-cmd-off-state {
1020 bias-pull-up;
1021 drive-strength = <2>;
1024 sdc2_data_on: sdc2-data-on-state {
1026 bias-pull-up;
1027 drive-strength = <10>;
1030 sdc2_data_off: sdc2-data-off-state {
1032 bias-pull-up;
1033 drive-strength = <2>;
1037 mmcc: clock-controller@fd8c0000 {
1038 compatible = "qcom,mmcc-msm8994";
1040 #clock-cells = <1>;
1041 #reset-cells = <1>;
1042 #power-domain-cells = <1>;
1044 clock-names = "xo",
1063 assigned-clocks = <&mmcc MMPLL0_PLL>,
1068 assigned-clock-rates = <800000000>,
1076 compatible = "qcom,msm8974-ocmem";
1079 reg-names = "ctrl", "mem";
1083 clock-names = "core", "iface";
1085 #address-cells = <1>;
1086 #size-cells = <1>;
1088 gmu_sram: gmu-sram@0 {
1095 compatible = "arm,armv8-timer";
1102 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr";
1106 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <3600000>;
1109 regulator-always-on;