Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 cpu-idle-states = <&little_cpu_sleep_0>;
40 capacity-dmips-mhz = <573>;
41 next-level-cache = <&l2_0>;
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 cpu-idle-states = <&little_cpu_sleep_0>;
51 capacity-dmips-mhz = <573>;
52 next-level-cache = <&l2_0>;
53 #cooling-cells = <2>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 cpu-idle-states = <&little_cpu_sleep_0>;
62 capacity-dmips-mhz = <573>;
63 next-level-cache = <&l2_0>;
64 #cooling-cells = <2>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&little_cpu_sleep_0>;
73 capacity-dmips-mhz = <573>;
74 next-level-cache = <&l2_0>;
75 #cooling-cells = <2>;
80 compatible = "arm,cortex-a72";
82 enable-method = "psci";
83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
84 capacity-dmips-mhz = <1024>;
85 next-level-cache = <&l2_1>;
86 #cooling-cells = <2>;
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
95 capacity-dmips-mhz = <1024>;
96 next-level-cache = <&l2_1>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a72";
104 enable-method = "psci";
105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a72";
115 enable-method = "psci";
116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
117 capacity-dmips-mhz = <1024>;
118 next-level-cache = <&l2_1>;
119 #cooling-cells = <2>;
122 cpu-map {
160 idle-states {
161 entry-method = "psci";
163 little_cpu_sleep_0: cpu-sleep-0-0 {
164 compatible = "arm,idle-state";
165 idle-state-name = "little-power-collapse";
166 arm,psci-suspend-param = <0x40000003>;
167 entry-latency-us = <181>;
168 exit-latency-us = <149>;
169 min-residency-us = <703>;
170 local-timer-stop;
173 big_cpu_sleep_0: cpu-sleep-1-0 {
174 compatible = "arm,idle-state";
175 idle-state-name = "big-retention";
176 arm,psci-suspend-param = <0x00000002>;
177 entry-latency-us = <142>;
178 exit-latency-us = <99>;
179 min-residency-us = <242>;
182 big_cpu_sleep_1: cpu-sleep-1-1 {
183 compatible = "arm,idle-state";
184 idle-state-name = "big-power-collapse";
185 arm,psci-suspend-param = <0x40000003>;
186 entry-latency-us = <158>;
187 exit-latency-us = <144>;
188 min-residency-us = <863>;
189 local-timer-stop;
193 l2_0: l2-cache0 {
195 cache-level = <2>;
196 cache-unified;
199 l2_1: l2-cache1 {
201 cache-level = <2>;
202 cache-unified;
208 compatible = "qcom,scm-msm8976", "qcom,scm";
212 clock-names = "core", "bus", "iface";
213 #reset-cells = <1>;
215 qcom,dload-mode = <&tcsr 0x6100>;
226 compatible = "arm,armv8-pmuv3";
231 compatible = "arm,psci-1.0";
236 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
238 smd-edge {
241 qcom,smd-edge = <15>;
243 rpm_requests: rpm-requests {
244 compatible = "qcom,rpm-msm8976";
245 qcom,smd-channels = "rpm_requests";
247 rpmcc: clock-controller {
248 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
250 clock-names = "xo";
251 #clock-cells = <1>;
254 rpmpd: power-controller {
255 compatible = "qcom,msm8976-rpmpd";
256 #power-domain-cells = <1>;
257 operating-points-v2 = <&rpmpd_opp_table>;
259 rpmpd_opp_table: opp-table {
260 compatible = "operating-points-v2";
263 opp-level = <RPM_SMD_LEVEL_RETENTION>;
267 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
271 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
275 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
279 opp-level = <RPM_SMD_LEVEL_SVS>;
283 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
287 opp-level = <RPM_SMD_LEVEL_NOM>;
291 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
295 opp-level = <RPM_SMD_LEVEL_TURBO>;
299 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
303 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
311 reserved-memory {
312 #address-cells = <2>;
313 #size-cells = <2>;
316 ext-region@85b00000 {
318 no-map;
324 no-map;
327 qcom,rpm-msg-ram = <&rpm_msg_ram>;
332 no-map;
337 no-map;
342 no-map;
347 no-map;
352 no-map;
355 tz-apps@8dd00000 {
357 no-map;
361 smp2p-hexagon {
366 qcom,local-pid = <0>;
367 qcom,remote-pid = <2>;
370 adsp_smp2p_out: master-kernel {
371 qcom,entry-name = "master-kernel";
373 #qcom,smem-state-cells = <1>;
376 adsp_smp2p_in: slave-kernel {
377 qcom,entry-name = "slave-kernel";
379 interrupt-controller;
380 #interrupt-cells = <2>;
384 smp2p-modem {
389 qcom,local-pid = <0>;
390 qcom,remote-pid = <1>;
393 modem_smp2p_out: master-kernel {
394 qcom,entry-name = "master-kernel";
396 #qcom,smem-state-cells = <1>;
399 modem_smp2p_in: slave-kernel {
400 qcom,entry-name = "slave-kernel";
402 interrupt-controller;
403 #interrupt-cells = <2>;
407 smp2p-wcnss {
412 qcom,local-pid = <0>;
413 qcom,remote-pid = <4>;
416 wcnss_smp2p_out: master-kernel {
417 qcom,entry-name = "master-kernel";
419 #qcom,smem-state-cells = <1>;
422 wcnss_smp2p_in: slave-kernel {
423 qcom,entry-name = "slave-kernel";
425 interrupt-controller;
426 #interrupt-cells = <2>;
433 #address-cells = <1>;
434 #size-cells = <0>;
436 qcom,ipc-1 = <&apcs 8 13>;
437 qcom,ipc-2 = <&apcs 8 9>;
438 qcom,ipc-3 = <&apcs 8 19>;
442 #qcom,smem-state-cells = <1>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
463 #address-cells = <1>;
464 #size-cells = <1>;
466 compatible = "simple-bus";
472 clock-names = "core";
476 compatible = "qcom,rpm-msg-ram";
481 compatible = "qcom,usb-hs-28nm-femtophy";
483 #phy-cells = <0>;
487 clock-names = "ref", "ahb", "sleep";
490 reset-names = "phy", "por";
495 compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
497 #address-cells = <1>;
498 #size-cells = <1>;
505 tsens_s0_p1: s0-p1@219 {
510 tsens_s0_p2: s0-p2@219 {
515 tsens_s1_p1: s1-p1@21a {
520 tsens_s1_p2: s1-p2@21b {
525 tsens_s2_p1: s2-p1@21c {
530 tsens_s2_p2: s2-p2@21c {
535 tsens_s3_p1: s3-p1@21d {
540 tsens_s3_p2: s3-p2@21e {
550 tsens_s4_p1: s4-p1@221 {
555 tsens_s4_p2: s4-p2@221 {
560 tsens_s5_p1: s5-p1@222 {
565 tsens_s5_p2: s5-p2@223 {
570 tsens_s6_p1: s6-p1@224 {
575 tsens_s6_p2: s6-p2@224 {
580 tsens_s7_p1: s7-p1@225 {
585 tsens_s7_p2: s7-p2@226 {
595 tsens_s8_p1: s8-p1@228 {
600 tsens_s8_p2: s8-p2@229 {
605 tsens_s9_p1: s9-p1@229 {
610 tsens_s9_p2: s9-p2@22a {
615 tsens_s10_p1: s10-p1@22b {
620 tsens_s10_p2: s10-p2@22c {
626 tsens: thermal-sensor@4a9000 {
627 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
631 interrupt-names = "uplow";
632 nvmem-cells = <&tsens_mode>,
645 nvmem-cell-names = "mode",
659 #thermal-sensor-cells = <1>;
663 compatible = "qcom,msm8976-pinctrl";
666 #gpio-cells = <2>;
667 gpio-controller;
668 gpio-ranges = <&tlmm 0 0 145>;
669 interrupt-controller;
670 #interrupt-cells = <2>;
672 spi1_default: spi0-default-state {
673 spi-pins {
676 drive-strength = <12>;
677 bias-disable;
680 cs-pins {
683 drive-strength = <2>;
684 bias-disable;
688 spi1_sleep: spi0-sleep-state {
689 spi-pins {
692 drive-strength = <2>;
693 bias-pull-down;
696 cs-pins {
699 drive-strength = <2>;
700 bias-disable;
704 blsp1_i2c2_default: blsp1-i2c2-default-state {
707 drive-strength = <2>;
708 bias-disable;
711 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
714 drive-strength = <2>;
715 bias-disable;
718 blsp1_i2c4_default: blsp1-i2c4-default-state {
721 drive-strength = <2>;
722 bias-disable;
725 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
728 drive-strength = <2>;
729 bias-disable;
732 blsp2_uart2_active: blsp2-uart2-active-state {
735 drive-strength = <4>;
736 bias-disable;
739 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
742 drive-strength = <2>;
743 bias-disable;
747 blsp2_i2c2_default: blsp2-i2c2-default-state {
750 drive-strength = <2>;
751 bias-disable;
754 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
757 drive-strength = <2>;
758 bias-disable;
761 blsp2_i2c4_default: blsp2-i2c4-default-state {
764 drive-strength = <2>;
765 bias-disable;
768 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
771 drive-strength = <2>;
772 bias-disable;
776 gcc: clock-controller@1800000 {
777 compatible = "qcom,gcc-msm8976";
779 #clock-cells = <1>;
780 #reset-cells = <1>;
781 #power-domain-cells = <1>;
783 assigned-clocks = <&gcc GPLL3>;
784 assigned-clock-rates = <1100000000>;
792 clock-names = "xo",
801 compatible = "qcom,tcsr-mutex";
803 #hwlock-cells = <1>;
807 compatible = "qcom,msm8976-tcsr", "syscon";
812 compatible = "qcom,spmi-pmic-arb";
818 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
820 interrupt-names = "periph_irq";
824 #address-cells = <2>;
825 #size-cells = <0>;
826 interrupt-controller;
827 #interrupt-cells = <4>;
831 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
833 reg-names = "hc", "core";
837 interrupt-names = "hc_irq", "pwr_irq";
842 clock-names = "iface", "core", "xo";
847 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
849 reg-names = "hc", "core";
853 interrupt-names = "hc_irq", "pwr_irq";
858 clock-names = "iface", "core", "xo";
862 blsp1_dma: dma-controller@7884000 {
863 compatible = "qcom,bam-v1.7.0";
867 clock-names = "bam_clk";
868 #dma-cells = <1>;
873 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
877 clock-names = "core", "iface";
879 dma-names = "tx", "rx";
884 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
888 clock-names = "core", "iface";
890 dma-names = "tx", "rx";
895 compatible = "qcom,spi-qup-v2.2.1";
899 clock-names = "core", "iface";
901 dma-names = "tx", "rx";
902 pinctrl-names = "default", "sleep";
903 pinctrl-0 = <&spi1_default>;
904 pinctrl-1 = <&spi1_sleep>;
905 #address-cells = <1>;
906 #size-cells = <0>;
911 compatible = "qcom,i2c-qup-v2.2.1";
915 clock-names = "core", "iface";
916 clock-frequency = <400000>;
918 dma-names = "tx", "rx";
919 pinctrl-names = "default", "sleep";
920 pinctrl-0 = <&blsp1_i2c2_default>;
921 pinctrl-1 = <&blsp1_i2c2_default>;
922 #address-cells = <1>;
923 #size-cells = <0>;
928 compatible = "qcom,i2c-qup-v2.2.1";
932 clock-names = "core", "iface";
933 clock-frequency = <400000>;
935 dma-names = "tx", "rx";
936 pinctrl-names = "default", "sleep";
937 pinctrl-0 = <&blsp1_i2c4_default>;
938 pinctrl-1 = <&blsp1_i2c4_sleep>;
939 #address-cells = <1>;
940 #size-cells = <0>;
945 compatible = "qcom,ci-hdrc";
951 clock-names = "iface", "core";
952 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
953 assigned-clock-rates = <80000000>;
955 reset-names = "core";
956 ahb-burst-config = <0>;
959 phy-names = "usb-phy";
962 #reset-cells = <1>;
966 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
968 reg-names = "hc", "core";
972 interrupt-names = "hc_irq", "pwr_irq";
977 clock-names = "iface", "core", "xo";
982 blsp2_dma: dma-controller@7ac4000 {
983 compatible = "qcom,bam-v1.7.0";
987 clock-names = "bam_clk";
988 #dma-cells = <1>;
993 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
997 clock-names = "core", "iface";
999 dma-names = "tx", "rx";
1004 compatible = "qcom,i2c-qup-v2.2.1";
1008 clock-names = "core", "iface";
1009 clock-frequency = <400000>;
1011 dma-names = "tx", "rx";
1012 pinctrl-names = "default", "sleep";
1013 pinctrl-0 = <&blsp2_i2c2_default>;
1014 pinctrl-1 = <&blsp2_i2c2_sleep>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1021 compatible = "qcom,i2c-qup-v2.2.1";
1025 clock-names = "core", "iface";
1026 clock-frequency = <400000>;
1028 dma-names = "tx", "rx";
1029 pinctrl-names = "default", "sleep";
1030 pinctrl-0 = <&blsp2_i2c4_default>;
1031 pinctrl-1 = <&blsp2_i2c4_sleep>;
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1037 intc: interrupt-controller@b000000 {
1038 compatible = "qcom,msm-qgic2";
1040 interrupt-controller;
1041 #interrupt-cells = <3>;
1045 compatible = "qcom,msm8976-apcs-kpss-global",
1046 "qcom,msm8994-apcs-kpss-global", "syscon";
1048 #mbox-cells = <1>;
1052 compatible = "arm,armv7-timer-mem";
1054 #address-cells = <1>;
1055 #size-cells = <1>;
1057 clock-frequency = <19200000>;
1063 frame-number = <0>;
1069 frame-number = <1>;
1076 frame-number = <2>;
1083 frame-number = <3>;
1090 frame-number = <4>;
1097 frame-number = <5>;
1104 frame-number = <6>;
1110 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
1112 #address-cells = <1>;
1113 #size-cells = <1>;
1117 pil-reloc@94c {
1118 compatible = "qcom,pil-reloc-info";
1124 thermal-zones {
1125 aoss0-thermal {
1126 polling-delay-passive = <250>;
1127 polling-delay = <1000>;
1129 thermal-sensors = <&tsens 0>;
1132 aoss0_alert0: trip-point0 {
1140 modem-thermal {
1141 polling-delay-passive = <250>;
1142 polling-delay = <1000>;
1144 thermal-sensors = <&tsens 1>;
1146 modem_alert0: trip-point0 {
1154 qdsp-thermal {
1155 polling-delay-passive = <250>;
1156 polling-delay = <1000>;
1158 thermal-sensors = <&tsens 2>;
1160 qdsp_alert0: trip-point0 {
1168 cam-isp-thermal {
1169 polling-delay-passive = <250>;
1170 polling-delay = <1000>;
1172 thermal-sensors = <&tsens 3>;
1174 cam_isp_alert0: trip-point0 {
1182 cpu4-thermal {
1183 polling-delay-passive = <250>;
1184 polling-delay = <1000>;
1185 thermal-sensors = <&tsens 4>;
1188 cpu4_alert0: trip-point0 {
1193 cpu4_alert1: trip-point1 {
1198 cpu4_crit: cpu-crit {
1206 cpu5-thermal {
1207 polling-delay-passive = <250>;
1208 polling-delay = <1000>;
1209 thermal-sensors = <&tsens 5>;
1212 cpu5_alert0: trip-point0 {
1217 cpu5_alert1: trip-point1 {
1222 cpu5_crit: cpu-crit {
1230 cpu6-thermal {
1231 polling-delay-passive = <250>;
1232 polling-delay = <1000>;
1233 thermal-sensors = <&tsens 6>;
1236 cpu6_alert0: trip-point0 {
1241 cpu6_alert1: trip-point1 {
1246 cpu6_crit: cpu-crit {
1254 cpu7-thermal {
1255 polling-delay-passive = <250>;
1256 polling-delay = <1000>;
1257 thermal-sensors = <&tsens 7>;
1260 cpu7_alert0: trip-point0 {
1265 cpu7_alert1: trip-point1 {
1270 cpu7_crit: cpu-crit {
1278 big-l2-thermal {
1279 polling-delay-passive = <250>;
1280 polling-delay = <1000>;
1281 thermal-sensors = <&tsens 8>;
1284 l2_alert0: trip-point0 {
1289 l2_alert1: trip-point1 {
1294 l2_crit: l2-crit {
1302 cpu0-thermal {
1303 polling-delay-passive = <250>;
1304 polling-delay = <1000>;
1305 thermal-sensors = <&tsens 9>;
1308 cpu0_alert0: trip-point0 {
1313 cpu0_alert1: trip-point1 {
1318 cpu0_crit: cpu-crit {
1326 gpu-thermal {
1327 polling-delay-passive = <250>;
1328 polling-delay = <1000>;
1329 thermal-sensors = <&tsens 10>;
1332 gpu_alert0: trip-point0 {
1337 gpu_alert1: trip-point1 {
1342 gpu_crit: gpu-crit {
1352 compatible = "arm,armv8-timer";
1357 clock-frequency = <19200000>;