Lines Matching +full:0 +full:x16000
25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
104 reg = <0x102>;
114 reg = <0x103>;
153 L2_0: l2-cache-0 {
180 reg = <0 0x10000000 0 0>;
198 qcom,ipc = <&apcs 8 0>;
268 reg = <0x0 0x81800000 0x0 0x2000>;
273 reg = <0x0 0x85b00000 0x0 0x800000>;
279 reg = <0x0 0x86300000 0x0 0x100000>;
286 reg = <0x0 0x86400000 0x0 0x400000>;
291 reg = <0x0 0x86c00000 0x0 0x6a00000>;
296 reg = <0x0 0x8d600000 0x0 0x1100000>;
301 reg = <0x0 0x8e700000 0x0 0x700000>;
306 reg = <0 0x90000000 0 0x1000>;
311 reg = <0x0 0x90001000 0x0 0x13ff000>;
316 reg = <0x0 0x91400000 0x0 0x700000>;
321 reg = <0x0 0x92000000 0x0 0x100000>;
327 reg = <0x0 0xf2d00000 0x0 0x180000>;
342 qcom,local-pid = <0>;
366 qcom,local-pid = <0>;
391 qcom,local-pid = <0>;
412 #size-cells = <0>;
417 apps_smsm: apps@0 {
418 reg = <0>;
440 soc: soc@0 {
443 ranges = <0 0 0 0xffffffff>;
448 reg = <0x00060000 0x8000>;
453 reg = <0x00079000 0x180>;
454 #phy-cells = <0>;
469 reg = <0x000e3000 0x1000>;
476 reg = <0x004a9000 0x1000>, /* TM */
477 <0x004a8000 0x1000>; /* SROT */
487 reg = <0x004ab000 0x4>;
492 reg = <0x01000000 0x300000>;
495 gpio-ranges = <&tlmm 0 0 142>;
805 reg = <0x01800000 0x80000>;
812 <&mdss_dsi0_phy 0>,
814 <&mdss_dsi1_phy 0>;
825 reg = <0x01905000 0x20000>;
831 reg = <0x01937000 0x30000>;
836 reg = <0x0193f044 0x4>;
842 reg = <0x01a00000 0x1000>,
843 <0x01ab0000 0x1040>;
870 reg = <0x01a01000 0x89000>;
874 interrupts = <0>;
887 iommus = <&apps_iommu 0x15>;
891 #size-cells = <0>;
893 port@0 {
894 reg = <0>;
911 reg = <0x01a94000 0x400>;
919 assigned-clock-parents = <&mdss_dsi0_phy 0>,
938 #size-cells = <0>;
944 #size-cells = <0>;
946 port@0 {
947 reg = <0>;
963 reg = <0x01a94400 0x100>,
964 <0x01a94500 0x300>,
965 <0x01a94800 0x188>;
971 #phy-cells = <0>;
981 reg = <0x01a96000 0x400>;
989 assigned-clock-parents = <&mdss_dsi1_phy 0>,
1011 #size-cells = <0>;
1013 port@0 {
1014 reg = <0>;
1030 reg = <0x01a96400 0x100>,
1031 <0x01a96500 0x300>,
1032 <0x01a96800 0x188>;
1038 #phy-cells = <0>;
1049 ranges = <0 0x01e20000 0x20000>;
1064 reg = <0x14000 0x1000>;
1071 reg = <0x15000 0x1000>;
1078 reg = <0x16000 0x1000>;
1085 reg = <0x0200f000 0x1000>,
1086 <0x02400000 0x800000>,
1087 <0x02c00000 0x800000>,
1088 <0x03800000 0x200000>,
1089 <0x0200a000 0x2100>;
1093 qcom,ee = <0>;
1094 qcom,channel = <0>;
1099 #size-cells = <0>;
1104 reg = <0x04080000 0x100>,
1105 <0x04020000 0x040>;
1109 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1127 qcom,smem-states = <&smp2p_modem_out 0>;
1133 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1148 qcom,smd-edge = <0>;
1158 reg = <0x070f8800 0x400>;
1190 reg = <0x07000000 0xcc00>;
1199 snps,hird-threshold = /bits/ 8 <0x00>;
1208 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1224 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1268 reg = <0x07864900 0x500>, <0x07864000 0x800>;
1284 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1323 reg = <0x07884000 0x1f000>;
1329 qcom,ee = <0>;
1336 reg = <0x078af000 0x200>;
1347 reg = <0x078b5000 0x600>;
1356 pinctrl-0 = <&i2c_1_default>;
1360 #size-cells = <0>;
1367 reg = <0x078b6000 0x600>;
1376 pinctrl-0 = <&i2c_2_default>;
1380 #size-cells = <0>;
1387 reg = <0x078b7000 0x600>;
1396 pinctrl-0 = <&i2c_3_default>;
1400 #size-cells = <0>;
1407 reg = <0x078b7000 0x600>;
1416 pinctrl-0 = <&spi_3_default>;
1420 #size-cells = <0>;
1427 reg = <0x078b8000 0x600>;
1436 pinctrl-0 = <&i2c_4_default>;
1440 #size-cells = <0>;
1447 reg = <0x07ac4000 0x1f000>;
1453 qcom,ee = <0>;
1460 reg = <0x07af5000 0x600>;
1469 pinctrl-0 = <&i2c_5_default>;
1473 #size-cells = <0>;
1480 reg = <0x07af5000 0x600>;
1489 pinctrl-0 = <&spi_5_default>;
1493 #size-cells = <0>;
1500 reg = <0x07af6000 0x600>;
1509 pinctrl-0 = <&i2c_6_default>;
1513 #size-cells = <0>;
1520 reg = <0x07af6000 0x600>;
1529 pinctrl-0 = <&spi_6_default>;
1533 #size-cells = <0>;
1540 reg = <0x07af7000 0x600>;
1549 pinctrl-0 = <&i2c_7_default>;
1553 #size-cells = <0>;
1560 reg = <0x07af8000 0x600>;
1569 pinctrl-0 = <&i2c_8_default>;
1573 #size-cells = <0>;
1580 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1586 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>,
1596 qcom,smem-states = <&smp2p_wcnss_out 0>;
1600 pinctrl-0 = <&wcnss_pin_a>;
1648 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1653 reg = <0x0b011000 0x1000>;
1659 reg = <0x0b120000 0x1000>;
1665 frame-number = <0>;
1668 reg = <0x0b121000 0x1000>,
1669 <0x0b122000 0x1000>;
1675 reg = <0x0b123000 0x1000>;
1682 reg = <0x0b124000 0x1000>;
1689 reg = <0x0b125000 0x1000>;
1696 reg = <0x0b126000 0x1000>;
1703 reg = <0x0b127000 0x1000>;
1710 reg = <0x0b128000 0x1000>;
1717 reg = <0x0c200000 0x100>;
1719 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1720 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1734 qcom,smem-states = <&smp2p_adsp_out 0>;
1752 #size-cells = <0>;
1765 #size-cells = <0>;
1770 qcom,sd-lines = <0 1>;
1774 qcom,sd-lines = <0 1>;
1778 qcom,sd-lines = <0>;
1794 #size-cells = <0>;
1797 dai@0 {
1798 reg = <0>;
1822 #sound-dai-cells = <0>;