Lines Matching +full:spin +full:- +full:up
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&intc>;
20 * Stock LK wants address-cells/size-cells = 2
22 * hence the disparity between top-level and /soc below.
24 #address-cells = <2>;
25 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <19200000>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32768>;
42 #address-cells = <1>;
43 #size-cells = <0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "spin-table";
50 next-level-cache = <&L2_1>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
55 #cooling-cells = <2>;
56 L2_1: l2-cache {
58 cache-level = <2>;
59 cache-unified;
64 compatible = "arm,cortex-a53";
66 enable-method = "spin-table";
68 next-level-cache = <&L2_1>;
71 cpu-idle-states = <&CPU_SLEEP_0>;
73 #cooling-cells = <2>;
77 compatible = "arm,cortex-a53";
79 enable-method = "spin-table";
81 next-level-cache = <&L2_1>;
84 cpu-idle-states = <&CPU_SLEEP_0>;
86 #cooling-cells = <2>;
90 compatible = "arm,cortex-a53";
92 enable-method = "spin-table";
94 next-level-cache = <&L2_1>;
97 cpu-idle-states = <&CPU_SLEEP_0>;
99 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 enable-method = "spin-table";
109 cpu-idle-states = <&CPU_SLEEP_0>;
111 #cooling-cells = <2>;
112 next-level-cache = <&L2_0>;
113 L2_0: l2-cache {
115 cache-level = <2>;
116 cache-unified;
121 compatible = "arm,cortex-a53";
123 enable-method = "spin-table";
125 next-level-cache = <&L2_0>;
128 cpu-idle-states = <&CPU_SLEEP_0>;
130 #cooling-cells = <2>;
134 compatible = "arm,cortex-a53";
136 enable-method = "spin-table";
138 next-level-cache = <&L2_0>;
141 cpu-idle-states = <&CPU_SLEEP_0>;
143 #cooling-cells = <2>;
147 compatible = "arm,cortex-a53";
149 enable-method = "spin-table";
151 next-level-cache = <&L2_0>;
154 cpu-idle-states = <&CPU_SLEEP_0>;
156 #cooling-cells = <2>;
159 idle-states {
160 CPU_SLEEP_0: cpu-sleep-0 {
161 compatible = "arm,idle-state";
162 entry-latency-us = <130>;
163 exit-latency-us = <150>;
164 min-residency-us = <2000>;
165 local-timer-stop;
172 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz.
176 * The enable method used here is spin-table which presupposes use
178 * spin-table, the downstream non-psci/non-spin-table method that
181 cpu-map {
224 compatible = "qcom,scm-msm8916", "qcom,scm";
228 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>;
231 qcom,dload-mode = <&tcsr 0x6100>;
242 compatible = "arm,cortex-a53-pmu";
247 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
249 smd-edge {
252 qcom,smd-edge = <15>;
254 rpm_requests: rpm-requests {
255 compatible = "qcom,rpm-msm8936";
256 qcom,smd-channels = "rpm_requests";
258 rpmcc: clock-controller {
259 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
260 #clock-cells = <1>;
261 clock-names = "xo";
265 rpmpd: power-controller {
266 compatible = "qcom,msm8939-rpmpd";
267 #power-domain-cells = <1>;
268 operating-points-v2 = <&rpmpd_opp_table>;
270 rpmpd_opp_table: opp-table {
271 compatible = "operating-points-v2";
274 opp-level = <1>;
278 opp-level = <2>;
282 opp-level = <3>;
286 opp-level = <4>;
290 opp-level = <5>;
294 opp-level = <6>;
302 reserved-memory {
303 #address-cells = <2>;
304 #size-cells = <2>;
307 tz-apps@86000000 {
309 no-map;
315 no-map;
318 qcom,rpm-msg-ram = <&rpm_msg_ram>;
323 no-map;
328 no-map;
333 no-map;
337 compatible = "qcom,rmtfs-mem";
339 no-map;
341 qcom,client-id = <1>;
346 no-map;
355 * define reliable alloc-ranges.
358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
361 no-map;
368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
369 no-map;
376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
377 no-map;
384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
385 no-map;
390 smp2p-hexagon {
398 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>;
401 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "master-kernel";
404 #qcom,smem-state-cells = <1>;
407 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "slave-kernel";
410 interrupt-controller;
411 #interrupt-cells = <2>;
415 smp2p-wcnss {
423 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>;
426 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "slave-kernel";
429 interrupt-controller;
430 #interrupt-cells = <2>;
433 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "master-kernel";
436 #qcom,smem-state-cells = <1>;
443 #address-cells = <1>;
444 #size-cells = <0>;
446 qcom,ipc-1 = <&apcs1_mbox 8 13>;
447 qcom,ipc-3 = <&apcs1_mbox 8 19>;
452 #qcom,smem-state-cells = <1>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
473 compatible = "simple-bus";
474 #address-cells = <1>;
475 #size-cells = <1>;
482 clock-names = "core";
486 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
488 #address-cells = <1>;
489 #size-cells = <1>;
496 tsens_s6_p1: s6-p1@a1 {
501 tsens_s6_p2: s6-p2@a1 {
506 tsens_s7_p1: s7-p1@a2 {
511 tsens_s7_p2: s7-p2@a3 {
516 tsens_s8_p1: s8-p1@a4 {
521 tsens_s8_p2: s8-p2@a4 {
526 tsens_s9_p1: s9-p1@a5 {
531 tsens_s9_p2: s9-p2@a6 {
546 tsens_s0_p1: s0-p1@d0 {
551 tsens_s0_p2: s0-p1@d1 {
556 tsens_s1_p1: s1-p1@d1 {
561 tsens_s1_p2: s1-p2@d2 {
566 tsens_s2_p1: s2-p1@d3 {
571 tsens_s2_p2: s2-p2@d4 {
576 tsens_s3_p1: s3-p1@d4 {
581 tsens_s3_p2: s3-p2@d5 {
586 tsens_s5_p1: s5-p1@d6 {
591 tsens_s5_p2: s5-p2@d7 {
598 compatible = "qcom,rpm-msg-ram";
603 compatible = "qcom,msm8939-bimc";
605 #interconnect-cells = <1>;
608 tsens: thermal-sensor@4a9000 {
609 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
612 nvmem-cells = <&tsens_mode>,
623 nvmem-cell-names = "mode",
636 interrupt-names = "uplow";
637 #thermal-sensor-cells = <1>;
646 compatible = "qcom,msm8939-pcnoc";
648 #interconnect-cells = <1>;
652 compatible = "qcom,msm8939-snoc";
654 #interconnect-cells = <1>;
656 snoc_mm: interconnect-snoc {
657 compatible = "qcom,msm8939-snoc-mm";
658 #interconnect-cells = <1>;
663 compatible = "qcom,msm8916-pinctrl";
666 gpio-controller;
667 gpio-ranges = <&tlmm 0 0 122>;
668 #gpio-cells = <2>;
669 interrupt-controller;
670 #interrupt-cells = <2>;
672 blsp_i2c1_default: blsp-i2c1-default-state {
675 drive-strength = <2>;
676 bias-disable;
679 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
682 drive-strength = <2>;
683 bias-disable;
686 blsp_i2c2_default: blsp-i2c2-default-state {
689 drive-strength = <2>;
690 bias-disable;
693 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
696 drive-strength = <2>;
697 bias-disable;
700 blsp_i2c3_default: blsp-i2c3-default-state {
703 drive-strength = <2>;
704 bias-disable;
707 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
710 drive-strength = <2>;
711 bias-disable;
714 blsp_i2c4_default: blsp-i2c4-default-state {
717 drive-strength = <2>;
718 bias-disable;
721 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
724 drive-strength = <2>;
725 bias-disable;
728 blsp_i2c5_default: blsp-i2c5-default-state {
731 drive-strength = <2>;
732 bias-disable;
735 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
738 drive-strength = <2>;
739 bias-disable;
742 blsp_i2c6_default: blsp-i2c6-default-state {
745 drive-strength = <2>;
746 bias-disable;
749 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
752 drive-strength = <2>;
753 bias-disable;
756 blsp_spi1_default: blsp-spi1-default-state {
757 spi-pins {
760 drive-strength = <12>;
761 bias-disable;
764 cs-pins {
767 drive-strength = <16>;
768 bias-disable;
769 output-high;
773 blsp_spi1_sleep: blsp-spi1-sleep-state {
776 drive-strength = <2>;
777 bias-pull-down;
780 blsp_spi2_default: blsp-spi2-default-state {
781 spi-pins {
784 drive-strength = <12>;
785 bias-disable;
788 cs-pins {
791 drive-strength = <16>;
792 bias-disable;
793 output-high;
797 blsp_spi2_sleep: blsp-spi2-sleep-state {
800 drive-strength = <2>;
801 bias-pull-down;
804 blsp_spi3_default: blsp-spi3-default-state {
805 spi-pins {
808 drive-strength = <12>;
809 bias-disable;
812 cs-pins {
815 drive-strength = <16>;
816 bias-disable;
817 output-high;
821 blsp_spi3_sleep: blsp-spi3-sleep-state {
824 drive-strength = <2>;
825 bias-pull-down;
828 blsp_spi4_default: blsp-spi4-default-state {
829 spi-pins {
832 drive-strength = <12>;
833 bias-disable;
836 cs-pins {
839 drive-strength = <16>;
840 bias-disable;
841 output-high;
845 blsp_spi4_sleep: blsp-spi4-sleep-state {
848 drive-strength = <2>;
849 bias-pull-down;
852 blsp_spi5_default: blsp-spi5-default-state {
853 spi-pins {
856 drive-strength = <12>;
857 bias-disable;
860 cs-pins {
863 drive-strength = <16>;
864 bias-disable;
865 output-high;
869 blsp_spi5_sleep: blsp-spi5-sleep-state {
872 drive-strength = <2>;
873 bias-pull-down;
876 blsp_spi6_default: blsp-spi6-default-state {
877 spi-pins {
880 drive-strength = <12>;
881 bias-disable;
884 cs-pins {
887 drive-strength = <16>;
888 bias-disable;
889 output-high;
893 blsp_spi6_sleep: blsp-spi6-sleep-state {
896 drive-strength = <2>;
897 bias-pull-down;
900 blsp_uart1_default: blsp-uart1-default-state {
903 drive-strength = <16>;
904 bias-disable;
907 blsp_uart1_sleep: blsp-uart1-sleep-state {
910 drive-strength = <2>;
911 bias-pull-down;
914 blsp_uart2_default: blsp-uart2-default-state {
917 drive-strength = <16>;
918 bias-disable;
921 blsp_uart2_sleep: blsp-uart2-sleep-state {
924 drive-strength = <2>;
925 bias-pull-down;
928 camera_front_default: camera-front-default-state {
929 pwdn-pins {
932 drive-strength = <16>;
933 bias-disable;
936 rst-pins {
939 drive-strength = <16>;
940 bias-disable;
943 mclk1-pins {
946 drive-strength = <16>;
947 bias-disable;
951 camera_rear_default: camera-rear-default-state {
952 pwdn-pins {
955 drive-strength = <16>;
956 bias-disable;
959 rst-pins {
962 drive-strength = <16>;
963 bias-disable;
966 mclk0-pins {
969 drive-strength = <16>;
970 bias-disable;
974 cci0_default: cci0-default-state {
977 drive-strength = <16>;
978 bias-disable;
981 cdc_dmic_default: cdc-dmic-default-state {
982 clk-pins {
985 drive-strength = <8>;
988 data-pins {
991 drive-strength = <8>;
995 cdc_dmic_sleep: cdc-dmic-sleep-state {
996 clk-pins {
999 drive-strength = <2>;
1000 bias-disable;
1003 data-pins {
1006 drive-strength = <2>;
1007 bias-disable;
1011 cdc_pdm_default: cdc-pdm-default-state {
1015 drive-strength = <8>;
1016 bias-disable;
1019 cdc_pdm_sleep: cdc-pdm-sleep-state {
1023 drive-strength = <2>;
1024 bias-pull-down;
1027 pri_mi2s_default: mi2s-pri-default-state {
1030 drive-strength = <8>;
1031 bias-disable;
1034 pri_mi2s_sleep: mi2s-pri-sleep-state {
1037 drive-strength = <2>;
1038 bias-disable;
1041 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1044 drive-strength = <8>;
1045 bias-disable;
1048 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1051 drive-strength = <2>;
1052 bias-disable;
1055 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1058 drive-strength = <8>;
1059 bias-disable;
1062 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1065 drive-strength = <2>;
1066 bias-disable;
1069 sec_mi2s_default: mi2s-sec-default-state {
1072 drive-strength = <8>;
1073 bias-disable;
1076 sec_mi2s_sleep: mi2s-sec-sleep-state {
1079 drive-strength = <2>;
1080 bias-disable;
1083 sdc1_default: sdc1-default-state {
1084 clk-pins {
1086 bias-disable;
1087 drive-strength = <16>;
1090 cmd-pins {
1092 bias-pull-up;
1093 drive-strength = <10>;
1096 data-pins {
1098 bias-pull-up;
1099 drive-strength = <10>;
1103 sdc1_sleep: sdc1-sleep-state {
1104 clk-pins {
1106 bias-disable;
1107 drive-strength = <2>;
1110 cmd-pins {
1112 bias-pull-up;
1113 drive-strength = <2>;
1116 data-pins {
1118 bias-pull-up;
1119 drive-strength = <2>;
1123 sdc2_default: sdc2-default-state {
1124 clk-pins {
1126 bias-disable;
1127 drive-strength = <16>;
1130 cmd-pins {
1132 bias-pull-up;
1133 drive-strength = <10>;
1136 data-pins {
1138 bias-pull-up;
1139 drive-strength = <10>;
1143 sdc2_sleep: sdc2-sleep-state {
1144 clk-pins {
1146 bias-disable;
1147 drive-strength = <2>;
1150 cmd-pins {
1152 bias-pull-up;
1153 drive-strength = <2>;
1156 data-pins {
1158 bias-pull-up;
1159 drive-strength = <2>;
1163 wcss_wlan_default: wcss-wlan-default-state {
1166 drive-strength = <6>;
1167 bias-pull-up;
1171 gcc: clock-controller@1800000 {
1172 compatible = "qcom,gcc-msm8939";
1181 clock-names = "xo",
1188 #clock-cells = <1>;
1189 #reset-cells = <1>;
1190 #power-domain-cells = <1>;
1194 compatible = "qcom,tcsr-mutex";
1196 #hwlock-cells = <1>;
1200 compatible = "qcom,tcsr-msm8916", "syscon";
1204 mdss: display-subsystem@1a00000 {
1208 reg-names = "mdss_phys", "vbif_phys";
1211 interrupt-controller;
1216 clock-names = "iface",
1220 power-domains = <&gcc MDSS_GDSC>;
1222 #address-cells = <1>;
1223 #size-cells = <1>;
1224 #interrupt-cells = <1>;
1229 mdss_mdp: display-controller@1a01000 {
1232 reg-names = "mdp_phys";
1234 interrupt-parent = <&mdss>;
1241 clock-names = "iface",
1250 interconnect-names = "mdp0-mem", "mdp1-mem";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 remote-endpoint = <&mdss_dsi0_in>;
1266 remote-endpoint = <&mdss_dsi1_in>;
1273 compatible = "qcom,msm8916-dsi-ctrl",
1274 "qcom,mdss-dsi-ctrl";
1276 reg-names = "dsi_ctrl";
1278 interrupt-parent = <&mdss>;
1287 clock-names = "mdp_core",
1293 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1295 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1311 remote-endpoint = <&mdss_mdp_intf1_out>;
1324 compatible = "qcom,dsi-phy-28nm-lp";
1328 reg-names = "dsi_pll",
1334 clock-names = "iface", "ref";
1336 #clock-cells = <1>;
1337 #phy-cells = <0>;
1342 compatible = "qcom,msm8916-dsi-ctrl",
1343 "qcom,mdss-dsi-ctrl";
1345 reg-names = "dsi_ctrl";
1347 interrupt-parent = <&mdss>;
1356 clock-names = "mdp_core",
1362 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1364 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1370 #address-cells = <1>;
1371 #size-cells = <0>;
1376 remote-endpoint = <&mdss_mdp_intf2_out>;
1389 compatible = "qcom,dsi-phy-28nm-lp";
1393 reg-names = "dsi_pll",
1399 clock-names = "iface", "ref";
1401 #clock-cells = <1>;
1402 #phy-cells = <0>;
1408 compatible = "qcom,adreno-405.0", "qcom,adreno";
1410 reg-names = "kgsl_3d0_reg_memory";
1412 interrupt-names = "kgsl_3d0_irq";
1413 clock-names = "core",
1427 power-domains = <&gcc OXILI_GDSC>;
1428 operating-points-v2 = <&opp_table>;
1432 opp_table: opp-table {
1433 compatible = "operating-points-v2";
1435 opp-550000000 {
1436 opp-hz = /bits/ 64 <550000000>;
1439 opp-465000000 {
1440 opp-hz = /bits/ 64 <465000000>;
1443 opp-400000000 {
1444 opp-hz = /bits/ 64 <400000000>;
1447 opp-220000000 {
1448 opp-hz = /bits/ 64 <220000000>;
1451 opp-19200000 {
1452 opp-hz = /bits/ 64 <19200000>;
1458 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1463 clock-names = "iface", "bus";
1464 #address-cells = <1>;
1465 #size-cells = <1>;
1466 #iommu-cells = <1>;
1467 qcom,iommu-secure-id = <17>;
1470 iommu-ctx@4000 {
1471 compatible = "qcom,msm-iommu-v1-ns";
1477 iommu-ctx@5000 {
1478 compatible = "qcom,msm-iommu-v1-sec";
1485 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1490 clock-names = "iface", "bus", "tbu";
1491 #address-cells = <1>;
1492 #size-cells = <1>;
1493 #iommu-cells = <1>;
1494 qcom,iommu-secure-id = <18>;
1497 iommu-ctx@1000 {
1498 compatible = "qcom,msm-iommu-v1-ns";
1504 iommu-ctx@2000 {
1505 compatible = "qcom,msm-iommu-v1-ns";
1512 compatible = "qcom,spmi-pmic-arb";
1518 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1519 interrupt-names = "periph_irq";
1523 #address-cells = <2>;
1524 #size-cells = <0>;
1525 interrupt-controller;
1526 #interrupt-cells = <4>;
1529 bam_dmux_dma: dma-controller@4044000 {
1530 compatible = "qcom,bam-v1.7.0";
1533 #dma-cells = <1>;
1536 num-channels = <6>;
1537 qcom,num-ees = <1>;
1538 qcom,powered-remotely;
1544 compatible = "qcom,msm8916-mss-pil";
1546 reg-names = "qdsp6", "rmb";
1547 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1552 interrupt-names = "wdog",
1556 "stop-ack";
1561 clock-names = "iface",
1565 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1567 power-domain-names = "cx", "mx";
1568 qcom,smem-states = <&hexagon_smp2p_out 0>;
1569 qcom,smem-state-names = "stop";
1571 reset-names = "mss_restart";
1572 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1575 bam_dmux: bam-dmux {
1576 compatible = "qcom,bam-dmux";
1578 interrupt-parent = <&hexagon_smsm>;
1580 interrupt-names = "pc", "pc-ack";
1582 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1583 qcom,smem-state-names = "pc", "pc-ack";
1586 dma-names = "tx", "rx";
1592 memory-region = <&mba_mem>;
1596 memory-region = <&mpss_mem>;
1599 smd-edge {
1602 qcom,smd-edge = <0>;
1604 qcom,remote-pid = <1>;
1609 compatible = "qcom,apr-v2";
1610 qcom,smd-channels = "apr_audio_svc";
1612 #address-cells = <1>;
1613 #size-cells = <0>;
1626 compatible = "qcom,q6afe-dais";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1629 #sound-dai-cells = <1>;
1638 compatible = "qcom,q6asm-dais";
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1641 #sound-dai-cells = <1>;
1650 compatible = "qcom,q6adm-routing";
1651 #sound-dai-cells = <0>;
1659 compatible = "qcom,apq8016-sbc-sndcard";
1662 reg-names = "mic-iomux", "spkr-iomux";
1666 lpass: audio-controller@7708000 {
1667 compatible = "qcom,apq8016-lpass-cpu";
1669 reg-names = "lpass-lpaif";
1671 interrupt-names = "lpass-irq-lpaif";
1679 clock-names = "ahbix-clk",
1680 "mi2s-bit-clk0",
1681 "mi2s-bit-clk1",
1682 "mi2s-bit-clk2",
1683 "mi2s-bit-clk3",
1684 "pcnoc-mport-clk",
1685 "pcnoc-sway-clk";
1686 #sound-dai-cells = <1>;
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1692 lpass_codec: audio-codec@771c000 {
1693 compatible = "qcom,msm8916-wcd-digital-codec";
1697 clock-names = "ahbix-clk", "mclk";
1698 #sound-dai-cells = <1>;
1703 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1705 reg-names = "hc", "core";
1709 interrupt-names = "hc_irq", "pwr_irq";
1713 clock-names = "iface", "core", "xo";
1715 pinctrl-0 = <&sdc1_default>;
1716 pinctrl-1 = <&sdc1_sleep>;
1717 pinctrl-names = "default", "sleep";
1718 mmc-ddr-1_8v;
1719 bus-width = <8>;
1720 non-removable;
1725 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1727 reg-names = "hc", "core";
1731 interrupt-names = "hc_irq", "pwr_irq";
1735 clock-names = "iface", "core", "xo";
1737 pinctrl-0 = <&sdc2_default>;
1738 pinctrl-1 = <&sdc2_sleep>;
1739 pinctrl-names = "default", "sleep";
1740 bus-width = <4>;
1744 blsp_dma: dma-controller@7884000 {
1745 compatible = "qcom,bam-v1.7.0";
1749 clock-names = "bam_clk";
1750 #dma-cells = <1>;
1752 qcom,controlled-remotely;
1756 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1760 clock-names = "core", "iface";
1762 dma-names = "tx", "rx";
1763 pinctrl-0 = <&blsp_uart1_default>;
1764 pinctrl-1 = <&blsp_uart1_sleep>;
1765 pinctrl-names = "default", "sleep";
1770 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1774 clock-names = "core", "iface";
1776 dma-names = "tx", "rx";
1777 pinctrl-0 = <&blsp_uart2_default>;
1778 pinctrl-1 = <&blsp_uart2_sleep>;
1779 pinctrl-names = "default", "sleep";
1784 compatible = "qcom,i2c-qup-v2.2.1";
1789 clock-names = "core", "iface";
1791 dma-names = "tx", "rx";
1792 pinctrl-0 = <&blsp_i2c1_default>;
1793 pinctrl-1 = <&blsp_i2c1_sleep>;
1794 pinctrl-names = "default", "sleep";
1795 #address-cells = <1>;
1796 #size-cells = <0>;
1801 compatible = "qcom,spi-qup-v2.2.1";
1806 clock-names = "core", "iface";
1808 dma-names = "tx", "rx";
1809 pinctrl-0 = <&blsp_spi1_default>;
1810 pinctrl-1 = <&blsp_spi1_sleep>;
1811 pinctrl-names = "default", "sleep";
1812 #address-cells = <1>;
1813 #size-cells = <0>;
1818 compatible = "qcom,i2c-qup-v2.2.1";
1823 clock-names = "core", "iface";
1825 dma-names = "tx", "rx";
1826 pinctrl-0 = <&blsp_i2c2_default>;
1827 pinctrl-1 = <&blsp_i2c2_sleep>;
1828 pinctrl-names = "default", "sleep";
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1835 compatible = "qcom,spi-qup-v2.2.1";
1840 clock-names = "core", "iface";
1842 dma-names = "tx", "rx";
1843 pinctrl-0 = <&blsp_spi2_default>;
1844 pinctrl-1 = <&blsp_spi2_sleep>;
1845 pinctrl-names = "default", "sleep";
1846 #address-cells = <1>;
1847 #size-cells = <0>;
1852 compatible = "qcom,i2c-qup-v2.2.1";
1857 clock-names = "core", "iface";
1859 dma-names = "tx", "rx";
1860 pinctrl-0 = <&blsp_i2c3_default>;
1861 pinctrl-1 = <&blsp_i2c3_sleep>;
1862 pinctrl-names = "default", "sleep";
1863 #address-cells = <1>;
1864 #size-cells = <0>;
1869 compatible = "qcom,spi-qup-v2.2.1";
1874 clock-names = "core", "iface";
1876 dma-names = "tx", "rx";
1877 pinctrl-0 = <&blsp_spi3_default>;
1878 pinctrl-1 = <&blsp_spi3_sleep>;
1879 pinctrl-names = "default", "sleep";
1880 #address-cells = <1>;
1881 #size-cells = <0>;
1886 compatible = "qcom,i2c-qup-v2.2.1";
1891 clock-names = "core", "iface";
1893 dma-names = "tx", "rx";
1894 pinctrl-0 = <&blsp_i2c4_default>;
1895 pinctrl-1 = <&blsp_i2c4_sleep>;
1896 pinctrl-names = "default", "sleep";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1903 compatible = "qcom,spi-qup-v2.2.1";
1908 clock-names = "core", "iface";
1910 dma-names = "tx", "rx";
1911 pinctrl-0 = <&blsp_spi4_default>;
1912 pinctrl-1 = <&blsp_spi4_sleep>;
1913 pinctrl-names = "default", "sleep";
1914 #address-cells = <1>;
1915 #size-cells = <0>;
1920 compatible = "qcom,i2c-qup-v2.2.1";
1925 clock-names = "core", "iface";
1927 dma-names = "tx", "rx";
1928 pinctrl-0 = <&blsp_i2c5_default>;
1929 pinctrl-1 = <&blsp_i2c5_sleep>;
1930 pinctrl-names = "default", "sleep";
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1937 compatible = "qcom,spi-qup-v2.2.1";
1942 clock-names = "core", "iface";
1944 dma-names = "tx", "rx";
1945 pinctrl-0 = <&blsp_spi5_default>;
1946 pinctrl-1 = <&blsp_spi5_sleep>;
1947 pinctrl-names = "default", "sleep";
1948 #address-cells = <1>;
1949 #size-cells = <0>;
1954 compatible = "qcom,i2c-qup-v2.2.1";
1959 clock-names = "core", "iface";
1961 dma-names = "tx", "rx";
1962 pinctrl-0 = <&blsp_i2c6_default>;
1963 pinctrl-1 = <&blsp_i2c6_sleep>;
1964 pinctrl-names = "default", "sleep";
1965 #address-cells = <1>;
1966 #size-cells = <0>;
1971 compatible = "qcom,spi-qup-v2.2.1";
1976 clock-names = "core", "iface";
1978 dma-names = "tx", "rx";
1979 pinctrl-0 = <&blsp_spi6_default>;
1980 pinctrl-1 = <&blsp_spi6_sleep>;
1981 pinctrl-names = "default", "sleep";
1982 #address-cells = <1>;
1983 #size-cells = <0>;
1988 compatible = "qcom,ci-hdrc";
1995 clock-names = "iface", "core";
1996 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1997 assigned-clock-rates = <80000000>;
1999 reset-names = "core";
2000 #reset-cells = <1>;
2003 adp-disable;
2004 hnp-disable;
2005 srp-disable;
2006 ahb-burst-config = <0>;
2007 phy-names = "usb-phy";
2013 compatible = "qcom,usb-hs-phy-msm8916",
2014 "qcom,usb-hs-phy";
2017 clock-names = "ref", "sleep";
2019 reset-names = "phy", "por";
2020 #phy-cells = <0>;
2021 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2030 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2031 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2036 interrupt-names = "wdog",
2040 "stop-ack";
2044 reg-names = "ccu", "dxe", "pmu";
2046 memory-region = <&wcnss_mem>;
2048 power-domains = <&rpmpd MSM8939_VDDCX>,
2050 power-domain-names = "cx", "mx";
2052 qcom,smem-states = <&wcnss_smp2p_out 0>;
2053 qcom,smem-state-names = "stop";
2055 pinctrl-names = "default";
2056 pinctrl-0 = <&wcss_wlan_default>;
2061 /* Separate chip, compatible is board-specific */
2063 clock-names = "xo";
2066 smd-edge {
2069 qcom,smd-edge = <6>;
2070 qcom,remote-pid = <4>;
2076 qcom,smd-channels = "WCNSS_CTRL";
2081 compatible = "qcom,wcnss-bt";
2085 compatible = "qcom,wcnss-wlan";
2089 interrupt-names = "tx", "rx";
2091 qcom,smem-states = <&apps_smsm 10>,
2093 qcom,smem-state-names = "tx-enable",
2094 "tx-rings-empty";
2100 intc: interrupt-controller@b000000 {
2101 compatible = "qcom,msm-qgic2";
2104 interrupt-controller;
2105 #interrupt-cells = <3>;
2110 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2113 clock-names = "pll", "aux", "ref";
2114 #clock-cells = <0>;
2115 assigned-clocks = <&apcs2>;
2116 assigned-clock-rates = <297600000>;
2117 #mbox-cells = <1>;
2121 compatible = "qcom,msm8939-a53pll";
2123 #clock-cells = <0>;
2126 acc0: clock-controller@b088000 {
2127 compatible = "qcom,kpss-acc-v2";
2131 saw0: power-manager@b089000 {
2132 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2136 acc1: clock-controller@b098000 {
2137 compatible = "qcom,kpss-acc-v2";
2141 saw1: power-manager@b099000 {
2142 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2146 acc2: clock-controller@b0a8000 {
2147 compatible = "qcom,kpss-acc-v2";
2151 saw2: power-manager@b0a9000 {
2152 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2156 acc3: clock-controller@b0b8000 {
2157 compatible = "qcom,kpss-acc-v2";
2161 saw3: power-manager@b0b9000 {
2162 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2167 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2170 clock-names = "pll", "aux", "ref";
2171 #clock-cells = <0>;
2172 #mbox-cells = <1>;
2176 compatible = "qcom,msm8939-a53pll";
2178 #clock-cells = <0>;
2182 compatible = "arm,armv7-timer-mem";
2184 #address-cells = <1>;
2185 #size-cells = <1>;
2188 clock-frequency = <19200000>;
2195 frame-number = <0>;
2201 frame-number = <1>;
2208 frame-number = <2>;
2215 frame-number = <3>;
2222 frame-number = <4>;
2229 frame-number = <5>;
2236 frame-number = <6>;
2241 acc4: clock-controller@b188000 {
2242 compatible = "qcom,kpss-acc-v2";
2246 saw4: power-manager@b189000 {
2247 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2251 acc5: clock-controller@b198000 {
2252 compatible = "qcom,kpss-acc-v2";
2256 saw5: power-manager@b199000 {
2257 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2261 acc6: clock-controller@b1a8000 {
2262 compatible = "qcom,kpss-acc-v2";
2266 saw6: power-manager@b1a9000 {
2267 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2271 acc7: clock-controller@b1b8000 {
2272 compatible = "qcom,kpss-acc-v2";
2276 saw7: power-manager@b1b9000 {
2277 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2282 compatible = "qcom,msm8939-a53pll";
2284 #clock-cells = <0>;
2288 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2291 clock-names = "pll", "aux", "ref";
2292 #clock-cells = <0>;
2293 #mbox-cells = <1>;
2297 thermal_zones: thermal-zones {
2298 cpu0-thermal {
2299 polling-delay-passive = <250>;
2300 polling-delay = <1000>;
2302 thermal-sensors = <&tsens 5>;
2318 cooling-maps {
2321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2329 cpu1-thermal {
2330 polling-delay-passive = <250>;
2331 polling-delay = <1000>;
2333 thermal-sensors = <&tsens 6>;
2349 cooling-maps {
2352 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2360 cpu2-thermal {
2361 polling-delay-passive = <250>;
2362 polling-delay = <1000>;
2364 thermal-sensors = <&tsens 7>;
2380 cooling-maps {
2383 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2391 cpu3-thermal {
2392 polling-delay-passive = <250>;
2393 polling-delay = <1000>;
2395 thermal-sensors = <&tsens 8>;
2411 cooling-maps {
2414 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2422 cpu4567-thermal {
2423 polling-delay-passive = <250>;
2424 polling-delay = <1000>;
2426 thermal-sensors = <&tsens 9>;
2442 cooling-maps {
2445 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2453 gpu-thermal {
2454 polling-delay-passive = <250>;
2455 polling-delay = <1000>;
2457 thermal-sensors = <&tsens 3>;
2460 gpu_alert0: trip-point0 {
2474 modem1-thermal {
2475 polling-delay-passive = <250>;
2476 polling-delay = <1000>;
2478 thermal-sensors = <&tsens 0>;
2481 modem1_alert0: trip-point0 {
2489 modem2-thermal {
2490 polling-delay-passive = <250>;
2491 polling-delay = <1000>;
2493 thermal-sensors = <&tsens 2>;
2496 modem2_alert0: trip-point0 {
2504 camera-thermal {
2505 polling-delay-passive = <250>;
2506 polling-delay = <1000>;
2508 thermal-sensors = <&tsens 1>;
2511 cam_alert0: trip-point0 {
2521 compatible = "arm,armv8-timer";