Lines Matching +full:0 +full:x0a204000
30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
49 reg = <0x100>;
67 reg = <0x101>;
80 reg = <0x102>;
93 reg = <0x103>;
102 CPU4: cpu@0 {
106 reg = <0x0>;
124 reg = <0x1>;
137 reg = <0x2>;
150 reg = <0x3>;
160 CPU_SLEEP_0: cpu-sleep-0 {
202 /* Boot CPU is cluster 1 core 0 */
231 qcom,dload-mode = <&tcsr 0x6100>;
238 reg = <0x0 0x80000000 0x0 0x0>;
251 qcom,ipc = <&apcs1_mbox 8 0>;
308 reg = <0x0 0x86000000 0x0 0x300000>;
314 reg = <0x0 0x86300000 0x0 0x100000>;
322 reg = <0x0 0x86400000 0x0 0x100000>;
327 reg = <0x0 0x86500000 0x0 0x180000>;
332 reg = <0x0 0x86680000 0x0 0x80000>;
338 reg = <0x0 0x86700000 0x0 0xe0000>;
345 reg = <0x0 0x867e0000 0x0 0x20000>;
357 * alignment = <0x0 0x400000>;
358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
366 size = <0x0 0x600000>;
367 alignment = <0x0 0x100000>;
368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
374 size = <0x0 0x500000>;
375 alignment = <0x0 0x100000>;
376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
382 size = <0x0 0x100000>;
383 alignment = <0x0 0x100000>;
384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
398 qcom,local-pid = <0>;
423 qcom,local-pid = <0>;
444 #size-cells = <0>;
449 apps_smsm: apps@0 {
450 reg = <0>;
472 soc: soc@0 {
476 ranges = <0 0 0 0xffffffff>;
480 reg = <0x00022000 0x200>;
487 reg = <0x0005c000 0x1000>;
492 reg = <0xa0 0x1>;
493 bits = <0 8>;
497 reg = <0xa1 0x1>;
498 bits = <0 6>;
502 reg = <0xa1 0x2>;
507 reg = <0xa2 0x2>;
512 reg = <0xa3 0x1>;
517 reg = <0xa4 0x1>;
518 bits = <0 6>;
522 reg = <0xa4 0x2>;
527 reg = <0xa5 0x2>;
532 reg = <0xa6 0x1>;
537 reg = <0xa7 0x1>;
538 bits = <0 8>;
542 reg = <0xd0 0x1>;
543 bits = <0 3>;
547 reg = <0xd0 0x2>;
552 reg = <0xd1 0x1>;
557 reg = <0xd1 0x2>;
562 reg = <0xd2 0x2>;
567 reg = <0xd3 0x2>;
572 reg = <0xd4 0x1>;
577 reg = <0xd4 0x2>;
582 reg = <0xd5 0x2>;
587 reg = <0xd6 0x2>;
592 reg = <0xd7 0x1>;
599 reg = <0x00060000 0x8000>;
604 reg = <0x00400000 0x62000>;
610 reg = <0x004a9000 0x1000>, /* TM */
611 <0x004a8000 0x1000>; /* SROT */
642 reg = <0x004ab000 0x4>;
647 reg = <0x00500000 0x11000>;
653 reg = <0x00580000 0x14080>;
664 reg = <0x01000000 0x300000>;
667 gpio-ranges = <&tlmm 0 0 122>;
1173 reg = <0x01800000 0x80000>;
1177 <&mdss_dsi0_phy 0>,
1178 <0>,
1179 <0>,
1180 <0>;
1195 reg = <0x01905000 0x20000>;
1201 reg = <0x01937000 0x30000>;
1206 reg = <0x01a00000 0x1000>,
1207 <0x01ac8000 0x3000>;
1231 reg = <0x01a01000 0x89000>;
1235 interrupts = <0>;
1254 #size-cells = <0>;
1256 port@0 {
1257 reg = <0>;
1275 reg = <0x01a98000 0x25c>;
1295 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1302 #size-cells = <0>;
1306 #size-cells = <0>;
1308 port@0 {
1309 reg = <0>;
1325 reg = <0x01a98300 0xd4>,
1326 <0x01a98500 0x280>,
1327 <0x01a98780 0x30>;
1337 #phy-cells = <0>;
1344 reg = <0x01aa0000 0x25c>;
1364 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1371 #size-cells = <0>;
1373 port@0 {
1374 reg = <0>;
1390 reg = <0x01aa0300 0xd4>,
1391 <0x01aa0500 0x280>,
1392 <0x01aa0780 0x30>;
1402 #phy-cells = <0>;
1409 reg = <0x01c00000 0x10000>;
1459 reg = <0x01ef0000 0x3000>;
1460 ranges = <0 0x01e20000 0x20000>;
1472 reg = <0x4000 0x1000>;
1479 reg = <0x5000 0x1000>;
1486 ranges = <0 0x1f08000 0x10000>;
1499 reg = <0x1000 0x1000>;
1506 reg = <0x2000 0x1000>;
1513 reg = <0x0200f000 0x001000>,
1514 <0x02400000 0x400000>,
1515 <0x02c00000 0x400000>,
1516 <0x03800000 0x200000>,
1517 <0x0200a000 0x002100>;
1521 qcom,ee = <0>;
1522 qcom,channel = <0>;
1524 #size-cells = <0>;
1531 reg = <0x04044000 0x19000>;
1534 qcom,ee = <0>;
1545 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1548 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1568 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 resets = <&scm 0>;
1572 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1602 qcom,smd-edge = <0>;
1613 #size-cells = <0>;
1628 #size-cells = <0>;
1640 #size-cells = <0>;
1651 #sound-dai-cells = <0>;
1660 reg = <0x07702000 0x4>,
1661 <0x07702004 0x4>;
1668 reg = <0x07708000 0x10000>;
1688 #size-cells = <0>;
1694 reg = <0x0771c000 0x400>;
1704 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1715 pinctrl-0 = <&sdc1_default>;
1726 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1737 pinctrl-0 = <&sdc2_default>;
1746 reg = <0x07884000 0x23000>;
1751 qcom,ee = <0>;
1757 reg = <0x078af000 0x200>;
1761 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1763 pinctrl-0 = <&blsp_uart1_default>;
1771 reg = <0x078b0000 0x200>;
1777 pinctrl-0 = <&blsp_uart2_default>;
1785 reg = <0x078b5000 0x500>;
1792 pinctrl-0 = <&blsp_i2c1_default>;
1796 #size-cells = <0>;
1802 reg = <0x078b5000 0x500>;
1809 pinctrl-0 = <&blsp_spi1_default>;
1813 #size-cells = <0>;
1819 reg = <0x078b6000 0x500>;
1826 pinctrl-0 = <&blsp_i2c2_default>;
1830 #size-cells = <0>;
1836 reg = <0x078b6000 0x500>;
1843 pinctrl-0 = <&blsp_spi2_default>;
1847 #size-cells = <0>;
1853 reg = <0x078b7000 0x500>;
1860 pinctrl-0 = <&blsp_i2c3_default>;
1864 #size-cells = <0>;
1870 reg = <0x078b7000 0x500>;
1877 pinctrl-0 = <&blsp_spi3_default>;
1881 #size-cells = <0>;
1887 reg = <0x078b8000 0x500>;
1894 pinctrl-0 = <&blsp_i2c4_default>;
1898 #size-cells = <0>;
1904 reg = <0x078b8000 0x500>;
1911 pinctrl-0 = <&blsp_spi4_default>;
1915 #size-cells = <0>;
1921 reg = <0x078b9000 0x500>;
1928 pinctrl-0 = <&blsp_i2c5_default>;
1932 #size-cells = <0>;
1938 reg = <0x078b9000 0x500>;
1945 pinctrl-0 = <&blsp_spi5_default>;
1949 #size-cells = <0>;
1955 reg = <0x078ba000 0x500>;
1962 pinctrl-0 = <&blsp_i2c6_default>;
1966 #size-cells = <0>;
1972 reg = <0x078ba000 0x500>;
1979 pinctrl-0 = <&blsp_spi6_default>;
1983 #size-cells = <0>;
1989 reg = <0x078d9000 0x200>,
1990 <0x078d9200 0x200>;
2006 ahb-burst-config = <0>;
2018 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2020 #phy-cells = <0>;
2021 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2022 <0x1 0x6b>,
2023 <0x2 0x24>,
2024 <0x3 0x13>;
2032 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2041 reg = <0x0a204000 0x2000>,
2042 <0x0a202000 0x1000>,
2043 <0x0a21b000 0x3000>;
2052 qcom,smem-states = <&wcnss_smp2p_out 0>;
2056 pinctrl-0 = <&wcss_wlan_default>;
2102 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2103 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2106 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2111 reg = <0x0b011000 0x1000>;
2114 #clock-cells = <0>;
2122 reg = <0x0b016000 0x40>;
2123 #clock-cells = <0>;
2128 reg = <0x0b088000 0x1000>;
2132 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2133 reg = <0x0b089000 0x1000>;
2138 reg = <0x0b098000 0x1000>;
2142 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2143 reg = <0x0b099000 0x1000>;
2148 reg = <0x0b0a8000 0x1000>;
2152 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2153 reg = <0x0b0a9000 0x1000>;
2158 reg = <0x0b0b8000 0x1000>;
2162 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2163 reg = <0x0b0b9000 0x1000>;
2168 reg = <0x0b111000 0x1000>;
2171 #clock-cells = <0>;
2177 reg = <0x0b116000 0x40>;
2178 #clock-cells = <0>;
2183 reg = <0x0b120000 0x1000>;
2191 reg = <0x0b121000 0x1000>,
2192 <0x0b122000 0x1000>;
2195 frame-number = <0>;
2199 reg = <0x0b123000 0x1000>;
2206 reg = <0x0b124000 0x1000>;
2213 reg = <0x0b125000 0x1000>;
2220 reg = <0x0b126000 0x1000>;
2227 reg = <0x0b127000 0x1000>;
2234 reg = <0x0b128000 0x1000>;
2243 reg = <0x0b188000 0x1000>;
2247 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2248 reg = <0x0b189000 0x1000>;
2253 reg = <0x0b198000 0x1000>;
2257 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2258 reg = <0x0b199000 0x1000>;
2263 reg = <0x0b1a8000 0x1000>;
2267 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2268 reg = <0x0b1a9000 0x1000>;
2273 reg = <0x0b1b8000 0x1000>;
2277 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2278 reg = <0x0b1b9000 0x1000>;
2283 reg = <0x0b1d0000 0x40>;
2284 #clock-cells = <0>;
2289 reg = <0x0b1d1000 0x1000>;
2292 #clock-cells = <0>;
2313 hysteresis = <0>;
2478 thermal-sensors = <&tsens 0>;