Lines Matching +full:0 +full:x0b116000
24 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #size-cells = <0>;
37 CPU0: cpu@0 {
40 reg = <0x0>;
53 reg = <0x1>;
66 reg = <0x2>;
79 reg = <0x3>;
99 qcom,dload-mode = <&tcsr 0x6100>;
106 reg = <0x0 0x40000000 0x0 0x0>;
117 opp-supported-hw = <0xf>;
124 opp-supported-hw = <0xf>;
131 opp-supported-hw = <0xf>;
138 opp-supported-hw = <0x7>;
145 opp-supported-hw = <0x7>;
152 opp-supported-hw = <0x5>;
159 opp-supported-hw = <0x1>;
181 mboxes = <&apcs_glb 0>;
196 reg = <0x0 0x4a100000 0x0 0x400000>;
201 reg = <0x0 0x4a500000 0x0 0x100000>;
206 reg = <0x0 0x4a600000 0x0 0x400000>;
212 reg = <0x0 0x4aa00000 0x0 0x100000>;
218 soc: soc@0 {
222 ranges = <0 0 0 0xffffffff>;
226 reg = <0x00060000 0x6000>;
231 reg = <0x000e3000 0x1000>;
238 reg = <0x00090000 0x64>;
240 #size-cells = <0>;
248 reg = <0x000a4000 0x5a1>;
253 reg = <0x15 0x2>;
260 reg = <0x00704000 0x20000>;
269 reg = <0x0073a000 0x6000>;
280 reg = <0x004a9000 0x1000>,
281 <0x004a8000 0x1000>;
290 reg = <0x01000000 0x300000>;
294 gpio-ranges = <&tlmm 0 0 65>;
308 reg = <0x01800000 0x80000>;
311 <0>,
312 <0>,
313 <0>,
314 <0>,
315 <0>,
316 <0>;
324 reg = <0x01905000 0x20000>;
330 reg = <0x01937000 0x21000>;
335 reg = <0x07804000 0x1000>,
336 <0x07805000 0x1000>,
337 <0x07808000 0x2000>;
356 reg = <0x07884000 0x2b000>;
361 qcom,ee = <0>;
366 reg = <0x078af000 0x200>;
376 reg = <0x078b0000 0x200>;
386 reg = <0x078b1000 0x200>;
396 reg = <0x078b2000 0x200>;
406 reg = <0x078b3000 0x200>;
416 reg = <0x078b4000 0x200>;
426 reg = <0x078b5000 0x600>;
428 #size-cells = <0>;
440 reg = <0x078b6000 0x600>;
442 #size-cells = <0>;
456 reg = <0x078b6000 0x600>;
458 #size-cells = <0>;
470 reg = <0x078b7000 0x600>;
472 #size-cells = <0>;
486 reg = <0x078b7000 0x600>;
488 #size-cells = <0>;
500 reg = <0x078b8000 0x600>;
502 #size-cells = <0>;
516 reg = <0x078b8000 0x600>;
518 #size-cells = <0>;
531 reg = <0x078b9000 0x600>;
533 #size-cells = <0>;
547 reg = <0x078b9000 0x600>;
549 #size-cells = <0>;
561 reg = <0x0007b000 0x180>;
562 #phy-cells = <0>;
575 reg = <0x0007d000 0xa00>;
576 #phy-cells = <0>;
592 #clock-cells = <0>;
600 reg = <0x08af8800 0x400>;
630 reg = <0x8a00000 0xcd00>;
638 snps,hird-threshold = /bits/ 8 <0x0>;
646 reg = <0x0b000000 0x1000>, /* GICD */
647 <0x0b002000 0x2000>, /* GICC */
648 <0x0b001000 0x1000>, /* GICH */
649 <0x0b004000 0x2000>; /* GICV */
655 ranges = <0 0x0b00c000 0x3000>;
657 v2m0: v2m@0 {
659 reg = <0x00000000 0xffd>;
665 reg = <0x00001000 0xffd>;
671 reg = <0x00002000 0xffd>;
678 reg = <0x0b017000 0x1000>;
687 reg = <0x0b111000 0x1000>;
696 reg = <0x0b116000 0x40>;
697 #clock-cells = <0>;
704 reg = <0x0b120000 0x1000>;
710 reg = <0x0b121000 0x1000>,
711 <0x0b122000 0x1000>;
712 frame-number = <0>;
718 reg = <0x0b123000 0x1000>;
725 reg = <0x0b124000 0x1000>;
732 reg = <0x0b125000 0x1000>;
739 reg = <0x0b126000 0x1000>;
746 reg = <0x0b127000 0x1000>;
753 reg = <0x0b128000 0x1000>;
774 ubi-0-thermal {