Lines Matching +full:0 +full:x0b116000
21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
101 reg = <0x0 0x4ab00000 0x0 0x100000>;
108 reg = <0x0 0x4ac00000 0x0 0x400000>;
116 qcom,dload-mode = <&tcsr 0x6100>;
120 soc: soc@0 {
123 ranges = <0 0 0 0xffffffff>;
128 reg = <0x00058000 0x1000>;
139 #clock-cells = <0>;
140 #phy-cells = <0>;
152 reg = <0x00059000 0x180>;
153 #phy-cells = <0>;
165 reg = <0x00078000 0x1000>;
176 #clock-cells = <0>;
177 #phy-cells = <0>;
189 reg = <0x00079000 0x180>;
190 #phy-cells = <0>;
202 reg = <0x00084000 0x1000>;
212 #clock-cells = <0>;
214 #phy-cells = <0>;
225 reg = <0x0008e000 0x1000>;
235 #clock-cells = <0>;
237 #phy-cells = <0>;
248 reg = <0x00090000 0x64>;
250 #size-cells = <0>;
260 reg = <0x000a4000 0x2000>;
267 reg = <0x000e3000 0x1000>;
275 reg = <0x4a9000 0x1000>, /* TM */
276 <0x4a8000 0x1000>; /* SROT */
285 reg = <0x00704000 0x20000>;
297 reg = <0x0073a000 0x6000>;
309 reg = <0x01000000 0x300000>;
312 gpio-ranges = <&tlmm 0 0 70>;
324 i2c_0_pins: i2c-0-state {
331 spi_0_pins: spi-0-state {
359 reg = <0x01800000 0x80000>;
375 reg = <0x01905000 0x20000>;
381 reg = <0x01937000 0x21000>;
386 reg = <0x0200f000 0x001000>,
387 <0x02400000 0x800000>,
388 <0x02c00000 0x800000>,
389 <0x03800000 0x200000>,
390 <0x0200a000 0x000700>;
394 qcom,ee = <0>;
395 qcom,channel = <0>;
397 #size-cells = <0>;
404 reg = <0x7824900 0x500>, <0x7824000 0x800>;
427 reg = <0x07884000 0x2b000>;
432 qcom,ee = <0>;
437 reg = <0x078af000 0x200>;
447 reg = <0x078b1000 0x200>;
455 pinctrl-0 = <&hsuart_pins>;
462 reg = <0x078b3000 0x200>;
467 pinctrl-0 = <&serial_4_pins>;
475 #size-cells = <0>;
476 reg = <0x078b5000 0x600>;
483 pinctrl-0 = <&spi_0_pins>;
491 #size-cells = <0>;
492 reg = <0x078b6000 0x600>;
500 pinctrl-0 = <&i2c_0_pins>;
508 #size-cells = <0>;
509 reg = <0x078b7000 0x600>;
523 #size-cells = <0>;
524 reg = <0x78b8000 0x600>;
537 #size-cells = <0>;
538 reg = <0x78b9000 0x600>;
552 #size-cells = <0>;
553 reg = <0x78b9000 0x600>;
566 #size-cells = <0>;
567 reg = <0x078ba000 0x600>;
580 reg = <0x07984000 0x1a000>;
585 qcom,ee = <0>;
591 reg = <0x079b0000 0x10000>;
593 #size-cells = <0>;
598 dmas = <&qpic_bam 0>,
602 pinctrl-0 = <&qpic_pins>;
609 reg = <0x08af8800 0x400>;
637 reg = <0x8a00000 0xcd00>;
642 snps,hird-threshold = /bits/ 8 <0x0>;
651 reg = <0x08cf8800 0x400>;
679 reg = <0x8c00000 0xcd00>;
684 snps,hird-threshold = /bits/ 8 <0x0>;
697 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
698 ranges = <0 0xb00a000 0xffd>;
700 v2m@0 {
703 reg = <0x0 0xffd>;
709 reg = <0xb017000 0x1000>;
718 reg = <0x0b111000 0x1000>;
728 reg = <0x0b116000 0x40>;
729 #clock-cells = <0>;
739 reg = <0x0b120000 0x1000>;
742 frame-number = <0>;
745 reg = <0x0b121000 0x1000>,
746 <0x0b122000 0x1000>;
752 reg = <0x0b123000 0x1000>;
759 reg = <0x0b124000 0x1000>;
766 reg = <0x0b125000 0x1000>;
773 reg = <0x0b126000 0x1000>;
780 reg = <0x0b127000 0x1000>;
787 reg = <0x0b128000 0x1000>;
794 reg = <0x10000000 0xf1d>,
795 <0x10000f20 0xa8>,
796 <0x00088000 0x2000>,
797 <0x10100000 0x1000>;
801 bus-range = <0x00 0xff>;
810 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
811 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
816 interrupt-map-mask = <0 0 0 0x7>;
817 interrupt-map = <0 0 0 1 &intc 0 0 142
819 <0 0 0 2 &intc 0 0 143
821 <0 0 0 3 &intc 0 0 144
823 <0 0 0 4 &intc 0 0 145
855 reg = <0x20000000 0xf1d>,
856 <0x20000f20 0xa8>,
857 <0x20001000 0x1000>,
858 <0x00080000 0x4000>,
859 <0x20100000 0x1000>;
862 linux,pci-domain = <0>;
863 bus-range = <0x00 0xff>;
872 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
873 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
878 interrupt-map-mask = <0 0 0 0x7>;
879 interrupt-map = <0 0 0 1 &intc 0 0 75
881 <0 0 0 2 &intc 0 0 78
883 <0 0 0 3 &intc 0 0 79
885 <0 0 0 4 &intc 0 0 83
950 nss-0-crit {