Lines Matching +full:opp +full:- +full:1320000000
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
22 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
55 clock-names = "cpu";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
84 L2_0: l2-cache {
86 cache-level = <2>;
87 cache-unified;
93 compatible = "qcom,scm-ipq6018", "qcom,scm";
94 qcom,dload-mode = <&tcsr 0x6100>;
98 cpu_opp_table: opp-table-cpu {
99 compatible = "operating-points-v2-kryo-cpu";
100 nvmem-cells = <&cpu_speed_bin>;
101 opp-shared;
103 opp-864000000 {
104 opp-hz = /bits/ 64 <864000000>;
105 opp-microvolt = <725000>;
106 opp-supported-hw = <0xf>;
107 clock-latency-ns = <200000>;
110 opp-1056000000 {
111 opp-hz = /bits/ 64 <1056000000>;
112 opp-microvolt = <787500>;
113 opp-supported-hw = <0xf>;
114 clock-latency-ns = <200000>;
117 opp-1320000000 {
118 opp-hz = /bits/ 64 <1320000000>;
119 opp-microvolt = <862500>;
120 opp-supported-hw = <0x3>;
121 clock-latency-ns = <200000>;
124 opp-1440000000 {
125 opp-hz = /bits/ 64 <1440000000>;
126 opp-microvolt = <925000>;
127 opp-supported-hw = <0x3>;
128 clock-latency-ns = <200000>;
131 opp-1608000000 {
132 opp-hz = /bits/ 64 <1608000000>;
133 opp-microvolt = <987500>;
134 opp-supported-hw = <0x1>;
135 clock-latency-ns = <200000>;
138 opp-1800000000 {
139 opp-hz = /bits/ 64 <1800000000>;
140 opp-microvolt = <1062500>;
141 opp-supported-hw = <0x1>;
142 clock-latency-ns = <200000>;
147 compatible = "arm,cortex-a53-pmu";
152 compatible = "arm,psci-1.0";
157 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
159 glink-edge {
160 compatible = "qcom,glink-rpm";
162 qcom,rpm-msg-ram = <&rpm_msg_ram>;
165 rpm_requests: rpm-requests {
166 compatible = "qcom,rpm-ipq6018";
167 qcom,glink-channels = "rpm_requests";
170 compatible = "qcom,rpm-mp5496-regulators";
173 regulator-min-microvolt = <725000>;
174 regulator-max-microvolt = <1062500>;
175 regulator-always-on;
182 reserved-memory {
183 #address-cells = <2>;
184 #size-cells = <2>;
189 no-map;
194 no-map;
199 no-map;
204 no-map;
209 no-map;
214 no-map;
220 memory-region = <&smem_region>;
225 #address-cells = <2>;
226 #size-cells = <2>;
228 dma-ranges;
229 compatible = "simple-bus";
232 compatible = "qcom,ipq6018-qusb2-phy";
234 #phy-cells = <0>;
238 clock-names = "cfg_ahb", "ref";
245 compatible = "qcom,ipq6018-qmp-usb3-phy";
252 clock-names = "aux",
256 clock-output-names = "gcc_usb0_pipe_clk_src";
257 #clock-cells = <0>;
258 #phy-cells = <0>;
262 reset-names = "phy",
269 compatible = "qcom,ipq6018-qusb2-phy";
271 #phy-cells = <0>;
275 clock-names = "cfg_ahb", "ref";
282 compatible = "qcom,ipq6018-qmp-pcie-phy";
289 clock-names = "aux",
293 clock-output-names = "gcc_pcie0_pipe_clk_src";
294 #clock-cells = <0>;
296 #phy-cells = <0>;
300 reset-names = "phy",
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
310 clock-names = "gcc_mdio_ahb_clk";
315 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
317 #address-cells = <1>;
318 #size-cells = <1>;
320 cpu_speed_bin: cpu-speed-bin@135 {
327 compatible = "qcom,prng-ee";
330 clock-names = "core";
333 cryptobam: dma-controller@704000 {
334 compatible = "qcom,bam-v1.7.0";
338 clock-names = "bam_clk";
339 #dma-cells = <1>;
341 qcom,controlled-remotely;
345 compatible = "qcom,crypto-v5.1";
350 clock-names = "iface", "bus", "core";
352 dma-names = "rx", "tx";
356 compatible = "qcom,ipq6018-pinctrl";
359 gpio-controller;
360 #gpio-cells = <2>;
361 gpio-ranges = <&tlmm 0 0 80>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
365 serial_3_pins: serial3-state {
368 drive-strength = <8>;
369 bias-pull-down;
372 qpic_pins: qpic-state {
379 drive-strength = <8>;
380 bias-disable;
385 compatible = "qcom,gcc-ipq6018";
388 clock-names = "xo", "sleep_clk";
389 #clock-cells = <1>;
390 #reset-cells = <1>;
394 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
396 #hwlock-cells = <1>;
400 compatible = "qcom,tcsr-ipq6018", "syscon";
405 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
407 #address-cells = <2>;
408 #size-cells = <2>;
413 clock-names = "core",
417 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
419 assigned-clock-rates = <133330000>,
429 phy-names = "usb2-phy";
430 tx-fifo-resize;
431 snps,is-utmi-l1-suspend;
432 snps,hird-threshold = /bits/ 8 <0x0>;
439 blsp_dma: dma-controller@7884000 {
440 compatible = "qcom,bam-v1.7.0";
444 clock-names = "bam_clk";
445 #dma-cells = <1>;
450 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
455 clock-names = "core", "iface";
460 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
465 clock-names = "core", "iface";
470 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
475 clock-names = "core", "iface";
480 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
485 clock-names = "core", "iface";
490 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
495 clock-names = "core", "iface";
500 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
505 clock-names = "core", "iface";
510 compatible = "qcom,spi-qup-v2.2.1";
511 #address-cells = <1>;
512 #size-cells = <0>;
517 clock-names = "core", "iface";
519 dma-names = "tx", "rx";
524 compatible = "qcom,spi-qup-v2.2.1";
525 #address-cells = <1>;
526 #size-cells = <0>;
531 clock-names = "core", "iface";
533 dma-names = "tx", "rx";
538 compatible = "qcom,spi-qup-v2.2.1";
539 #address-cells = <1>;
540 #size-cells = <0>;
545 clock-names = "core", "iface";
547 dma-names = "tx", "rx";
552 compatible = "qcom,i2c-qup-v2.2.1";
553 #address-cells = <1>;
554 #size-cells = <0>;
559 clock-names = "core", "iface";
560 clock-frequency = <400000>;
562 dma-names = "tx", "rx";
567 compatible = "qcom,i2c-qup-v2.2.1";
568 #address-cells = <1>;
569 #size-cells = <0>;
574 clock-names = "core", "iface";
575 clock-frequency = <400000>;
577 dma-names = "tx", "rx";
581 qpic_bam: dma-controller@7984000 {
582 compatible = "qcom,bam-v1.7.0";
586 clock-names = "bam_clk";
587 #dma-cells = <1>;
592 qpic_nand: nand-controller@79b0000 {
593 compatible = "qcom,ipq6018-nand";
595 #address-cells = <1>;
596 #size-cells = <0>;
599 clock-names = "core", "aon";
604 dma-names = "tx", "rx", "cmd";
605 pinctrl-0 = <&qpic_pins>;
606 pinctrl-names = "default";
611 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
613 #address-cells = <2>;
614 #size-cells = <2>;
621 clock-names = "cfg_noc",
626 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
629 assigned-clock-rates = <133330000>,
641 phy-names = "usb2-phy", "usb3-phy";
643 clock-names = "ref";
644 tx-fifo-resize;
645 snps,is-utmi-l1-suspend;
646 snps,hird-threshold = /bits/ 8 <0x0>;
653 intc: interrupt-controller@b000000 {
654 compatible = "qcom,msm-qgic2";
655 #address-cells = <2>;
656 #size-cells = <2>;
657 interrupt-controller;
658 #interrupt-cells = <3>;
667 compatible = "arm,gic-v2m-frame";
668 msi-controller;
674 compatible = "qcom,kpss-wdt";
678 timeout-sec = <10>;
682 compatible = "qcom,ipq6018-apcs-apps-global";
684 #clock-cells = <1>;
686 clock-names = "pll", "xo", "gpll0";
687 #mbox-cells = <1>;
691 compatible = "qcom,ipq6018-a53pll";
693 #clock-cells = <0>;
695 clock-names = "xo";
699 #address-cells = <1>;
700 #size-cells = <1>;
702 compatible = "arm,armv7-timer-mem";
706 frame-number = <0>;
714 frame-number = <1>;
721 frame-number = <2>;
728 frame-number = <3>;
735 frame-number = <4>;
742 frame-number = <5>;
749 frame-number = <6>;
757 compatible = "qcom,ipq6018-wcss-pil";
760 reg-names = "qdsp6",
762 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
767 interrupt-names = "wdog",
771 "stop-ack";
777 reset-names = "wcss_aon_reset",
782 clock-names = "prng";
784 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
786 qcom,smem-states = <&wcss_smp2p_out 0>,
788 qcom,smem-state-names = "shutdown",
791 memory-region = <&q6_region>;
793 glink-edge {
796 qcom,remote-pid = <1>;
800 qcom,glink-channels = "IPCRTR";
806 compatible = "qcom,pcie-ipq6018";
812 reg-names = "dbi", "elbi", "atu", "parf", "config";
815 linux,pci-domain = <0>;
816 bus-range = <0x00 0xff>;
817 num-lanes = <1>;
818 max-link-speed = <3>;
819 #address-cells = <3>;
820 #size-cells = <2>;
823 phy-names = "pciephy";
829 interrupt-names = "msi";
831 #interrupt-cells = <1>;
832 interrupt-map-mask = <0 0 0 0x7>;
833 interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
843 clock-names = "iface",
857 reset-names = "pipe",
871 compatible = "arm,armv8-timer";
878 wcss: wcss-smp2p {
882 interrupt-parent = <&intc>;
887 qcom,local-pid = <0>;
888 qcom,remote-pid = <1>;
890 wcss_smp2p_out: master-kernel {
891 qcom,entry-name = "master-kernel";
892 #qcom,smem-state-cells = <1>;
895 wcss_smp2p_in: slave-kernel {
896 qcom,entry-name = "slave-kernel";
897 interrupt-controller;
898 #interrupt-cells = <2>;