Lines Matching +full:gcc +full:- +full:ipq5424
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ5424 device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
11 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
12 #include <dt-bindings/interconnect/qcom,ipq5424.h>
13 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&intc>;
21 sleep_clk: sleep-clk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
26 xo_board: xo-board-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a55";
40 enable-method = "psci";
41 next-level-cache = <&l2_0>;
42 l2_0: l2-cache {
44 cache-level = <2>;
45 cache-unified;
46 next-level-cache = <&l3_0>;
48 l3_0: l3-cache {
50 cache-level = <3>;
51 cache-unified;
58 compatible = "arm,cortex-a55";
59 enable-method = "psci";
61 next-level-cache = <&l2_100>;
63 l2_100: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
73 compatible = "arm,cortex-a55";
74 enable-method = "psci";
76 next-level-cache = <&l2_200>;
78 l2_200: l2-cache {
80 cache-level = <2>;
81 cache-unified;
82 next-level-cache = <&l3_0>;
88 compatible = "arm,cortex-a55";
89 enable-method = "psci";
91 next-level-cache = <&l2_300>;
93 l2_300: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&l3_0>;
104 compatible = "qcom,scm-ipq5424", "qcom,scm";
105 qcom,dload-mode = <&tcsr 0x25100>;
115 pmu-a55 {
116 compatible = "arm,cortex-a55-pmu";
120 pmu-dsu {
121 compatible = "arm,dsu-pmu";
127 compatible = "arm,psci-1.0";
131 reserved-memory {
132 #address-cells = <2>;
133 #size-cells = <2>;
138 no-map;
143 no-map;
149 no-map;
156 compatible = "simple-bus";
157 #address-cells = <2>;
158 #size-cells = <2>;
162 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
163 "qcom,ipq9574-qmp-gen3x1-pcie-phy";
165 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
166 <&gcc GCC_PCIE0_AHB_CLK>,
167 <&gcc GCC_PCIE0_PIPE_CLK>;
168 clock-names = "aux",
172 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
173 assigned-clock-rates = <20000000>;
175 resets = <&gcc GCC_PCIE0_PHY_BCR>,
176 <&gcc GCC_PCIE0PHY_PHY_BCR>;
177 reset-names = "phy",
180 #clock-cells = <0>;
181 clock-output-names = "gcc_pcie0_pipe_clk_src";
183 #phy-cells = <0>;
188 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
189 "qcom,ipq9574-qmp-gen3x1-pcie-phy";
191 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
192 <&gcc GCC_PCIE1_AHB_CLK>,
193 <&gcc GCC_PCIE1_PIPE_CLK>;
194 clock-names = "aux",
198 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
199 assigned-clock-rates = <20000000>;
201 resets = <&gcc GCC_PCIE1_PHY_BCR>,
202 <&gcc GCC_PCIE1PHY_PHY_BCR>;
203 reset-names = "phy",
206 #clock-cells = <0>;
207 clock-output-names = "gcc_pcie1_pipe_clk_src";
209 #phy-cells = <0>;
214 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
216 #address-cells = <1>;
217 #size-cells = <1>;
271 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
272 "qcom,ipq9574-qmp-gen3x2-pcie-phy";
274 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
275 <&gcc GCC_PCIE2_AHB_CLK>,
276 <&gcc GCC_PCIE2_PIPE_CLK>;
277 clock-names = "aux",
281 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
282 assigned-clock-rates = <20000000>;
284 resets = <&gcc GCC_PCIE2_PHY_BCR>,
285 <&gcc GCC_PCIE2PHY_PHY_BCR>;
286 reset-names = "phy",
289 #clock-cells = <0>;
290 clock-output-names = "gcc_pcie2_pipe_clk_src";
292 #phy-cells = <0>;
297 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
298 "qcom,ipq9574-qmp-gen3x2-pcie-phy";
300 clocks = <&gcc GCC_PCIE3_AUX_CLK>,
301 <&gcc GCC_PCIE3_AHB_CLK>,
302 <&gcc GCC_PCIE3_PIPE_CLK>;
303 clock-names = "aux",
307 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
308 assigned-clock-rates = <20000000>;
310 resets = <&gcc GCC_PCIE3_PHY_BCR>,
311 <&gcc GCC_PCIE3PHY_PHY_BCR>;
312 reset-names = "phy",
315 #clock-cells = <0>;
316 clock-output-names = "gcc_pcie3_pipe_clk_src";
318 #phy-cells = <0>;
322 tsens: thermal-sensor@4a9000 {
323 compatible = "qcom,ipq5424-tsens";
327 interrupt-names = "combined";
328 nvmem-cells = <&tsens_mode>,
338 nvmem-cell-names = "mode",
349 #thermal-sensor-cells = <1>;
353 compatible = "qcom,ipq5424-trng", "qcom,trng";
355 clocks = <&gcc GCC_PRNG_AHB_CLK>;
356 clock-names = "core";
359 system-cache-controller@800000 {
360 compatible = "qcom,ipq5424-llcc";
362 reg-names = "llcc0_base";
367 compatible = "qcom,ipq5424-tlmm";
370 gpio-controller;
371 #gpio-cells = <2>;
372 gpio-ranges = <&tlmm 0 0 50>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
376 uart1_pins: uart1-state {
379 drive-strength = <8>;
380 bias-pull-up;
384 gcc: clock-controller@1800000 { label
385 compatible = "qcom,ipq5424-gcc";
394 #clock-cells = <1>;
395 #reset-cells = <1>;
396 #interconnect-cells = <1>;
400 compatible = "qcom,tcsr-mutex";
402 #hwlock-cells = <1>;
406 compatible = "qcom,tcsr-ipq5424", "syscon";
411 compatible = "qcom,geni-se-qup";
414 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
415 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
416 clock-names = "m-ahb", "s-ahb";
417 #address-cells = <2>;
418 #size-cells = <2>;
421 compatible = "qcom,geni-debug-uart";
423 clocks = <&gcc GCC_QUPV3_UART1_CLK>;
424 clock-names = "se";
429 compatible = "qcom,geni-spi";
431 clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
432 clock-names = "se";
434 #address-cells = <1>;
435 #size-cells = <0>;
440 compatible = "qcom,geni-spi";
442 clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
443 clock-names = "se";
445 #address-cells = <1>;
446 #size-cells = <0>;
452 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
454 reg-names = "hc", "cqhci";
458 interrupt-names = "hc_irq", "pwr_irq";
460 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
461 <&gcc GCC_SDCC1_APPS_CLK>,
463 clock-names = "iface", "core", "xo";
465 supports-cqe;
470 intc: interrupt-controller@f200000 {
471 compatible = "arm,gic-v3";
474 #interrupt-cells = <0x3>;
475 interrupt-controller;
476 #redistributor-regions = <1>;
477 redistributor-stride = <0x0 0x20000>;
479 mbi-ranges = <672 128>;
480 msi-controller;
484 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
491 compatible = "qcom,ipq5424-qusb2-phy";
493 #phy-cells = <0>;
495 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
497 clock-names = "cfg_ahb", "ref";
499 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
504 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
506 #address-cells = <2>;
507 #size-cells = <2>;
510 clocks = <&gcc GCC_USB1_MASTER_CLK>,
511 <&gcc GCC_USB1_SLEEP_CLK>,
512 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
513 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
514 <&gcc GCC_CNOC_USB_CLK>;
516 clock-names = "core",
522 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
523 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
524 assigned-clock-rates = <200000000>,
527 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
531 interrupt-names = "pwr_event",
536 resets = <&gcc GCC_USB1_BCR>;
537 qcom,select-utmi-as-pipe-clk;
543 clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
544 clock-names = "ref";
547 phy-names = "usb2-phy";
548 tx-fifo-resize;
549 snps,is-utmi-l1-suspend;
550 snps,hird-threshold = /bits/ 8 <0x0>;
557 compatible = "qcom,ipq5424-qusb2-phy";
559 #phy-cells = <0>;
561 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
563 clock-names = "cfg_ahb", "ref";
565 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
570 compatible = "qcom,ipq5424-qmp-usb3-phy";
572 #phy-cells = <0>;
574 clocks = <&gcc GCC_USB0_AUX_CLK>,
576 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
577 <&gcc GCC_USB0_PIPE_CLK>;
578 clock-names = "aux",
583 resets = <&gcc GCC_USB0_PHY_BCR>,
584 <&gcc GCC_USB3PHY_0_PHY_BCR>;
585 reset-names = "phy",
588 #clock-cells = <0>;
589 clock-output-names = "usb0_pipe_clk";
595 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
598 #address-cells = <2>;
599 #size-cells = <2>;
602 clocks = <&gcc GCC_USB0_MASTER_CLK>,
603 <&gcc GCC_USB0_SLEEP_CLK>,
604 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
605 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
606 <&gcc GCC_CNOC_USB_CLK>;
608 clock-names = "core",
614 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
615 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
616 assigned-clock-rates = <200000000>,
619 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
623 interrupt-names = "pwr_event",
628 resets = <&gcc GCC_USB_BCR>;
634 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
635 clock-names = "ref";
638 phy-names = "usb2-phy", "usb3-phy";
639 tx-fifo-resize;
640 snps,is-utmi-l1-suspend;
641 snps,hird-threshold = /bits/ 8 <0x0>;
644 snps,dis-u1-entry-quirk;
645 snps,dis-u2-entry-quirk;
650 compatible = "arm,armv7-timer-mem";
653 #address-cells = <1>;
654 #size-cells = <1>;
661 frame-number = <0>;
667 frame-number = <1>;
675 frame-number = <2>;
682 frame-number = <3>;
689 frame-number = <4>;
696 frame-number = <5>;
703 frame-number = <6>;
709 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
716 reg-names = "dbi",
723 linux,pci-domain = <3>;
724 num-lanes = <2>;
725 #address-cells = <3>;
726 #size-cells = <2>;
731 msi-map = <0x0 &intc 0x0 0x1000>;
743 interrupt-names = "msi0",
753 #interrupt-cells = <1>;
754 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
755 interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>,
760 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
761 <&gcc GCC_PCIE3_AXI_S_CLK>,
762 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
763 <&gcc GCC_PCIE3_RCHNG_CLK>,
764 <&gcc GCC_PCIE3_AHB_CLK>,
765 <&gcc GCC_PCIE3_AUX_CLK>;
766 clock-names = "axi_m",
773 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>;
774 assigned-clock-rates = <100000000>;
776 resets = <&gcc GCC_PCIE3_PIPE_ARES>,
777 <&gcc GCC_PCIE3_CORE_STICKY_RESET>,
778 <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>,
779 <&gcc GCC_PCIE3_AXI_S_ARES>,
780 <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>,
781 <&gcc GCC_PCIE3_AXI_M_ARES>,
782 <&gcc GCC_PCIE3_AUX_ARES>,
783 <&gcc GCC_PCIE3_AHB_ARES>;
784 reset-names = "pipe",
794 phy-names = "pciephy";
795 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
796 <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
797 interconnect-names = "pcie-mem", "cpu-pcie";
804 bus-range = <0x01 0xff>;
806 #address-cells = <3>;
807 #size-cells = <2>;
813 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
820 reg-names = "dbi",
827 linux,pci-domain = <2>;
828 num-lanes = <2>;
829 #address-cells = <3>;
830 #size-cells = <2>;
835 msi-map = <0x0 &intc 0x0 0x1000>;
846 interrupt-names = "msi0",
856 #interrupt-cells = <1>;
857 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
858 interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>,
863 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
864 <&gcc GCC_PCIE2_AXI_S_CLK>,
865 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
866 <&gcc GCC_PCIE2_RCHNG_CLK>,
867 <&gcc GCC_PCIE2_AHB_CLK>,
868 <&gcc GCC_PCIE2_AUX_CLK>;
869 clock-names = "axi_m",
876 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>;
877 assigned-clock-rates = <100000000>;
879 resets = <&gcc GCC_PCIE2_PIPE_ARES>,
880 <&gcc GCC_PCIE2_CORE_STICKY_RESET>,
881 <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>,
882 <&gcc GCC_PCIE2_AXI_S_ARES>,
883 <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>,
884 <&gcc GCC_PCIE2_AXI_M_ARES>,
885 <&gcc GCC_PCIE2_AUX_ARES>,
886 <&gcc GCC_PCIE2_AHB_ARES>;
887 reset-names = "pipe",
897 phy-names = "pciephy";
898 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
899 <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>;
900 interconnect-names = "pcie-mem", "cpu-pcie";
907 bus-range = <0x01 0xff>;
909 #address-cells = <3>;
910 #size-cells = <2>;
916 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
923 reg-names = "dbi",
930 linux,pci-domain = <1>;
931 num-lanes = <1>;
932 #address-cells = <3>;
933 #size-cells = <2>;
938 msi-map = <0x0 &intc 0x0 0x1000>;
949 interrupt-names = "msi0",
959 #interrupt-cells = <1>;
960 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
961 interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>,
966 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
967 <&gcc GCC_PCIE1_AXI_S_CLK>,
968 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
969 <&gcc GCC_PCIE1_RCHNG_CLK>,
970 <&gcc GCC_PCIE1_AHB_CLK>,
971 <&gcc GCC_PCIE1_AUX_CLK>;
972 clock-names = "axi_m",
979 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>;
980 assigned-clock-rates = <100000000>;
982 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
983 <&gcc GCC_PCIE1_CORE_STICKY_RESET>,
984 <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>,
985 <&gcc GCC_PCIE1_AXI_S_ARES>,
986 <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>,
987 <&gcc GCC_PCIE1_AXI_M_ARES>,
988 <&gcc GCC_PCIE1_AUX_ARES>,
989 <&gcc GCC_PCIE1_AHB_ARES>;
990 reset-names = "pipe",
1000 phy-names = "pciephy";
1001 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
1002 <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>;
1003 interconnect-names = "pcie-mem", "cpu-pcie";
1010 bus-range = <0x01 0xff>;
1012 #address-cells = <3>;
1013 #size-cells = <2>;
1019 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
1026 reg-names = "dbi",
1033 linux,pci-domain = <0>;
1034 num-lanes = <1>;
1035 #address-cells = <3>;
1036 #size-cells = <2>;
1041 msi-map = <0x0 &intc 0x0 0x1000>;
1052 interrupt-names = "msi0",
1062 #interrupt-cells = <1>;
1063 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1064 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
1069 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
1070 <&gcc GCC_PCIE0_AXI_S_CLK>,
1071 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
1072 <&gcc GCC_PCIE0_RCHNG_CLK>,
1073 <&gcc GCC_PCIE0_AHB_CLK>,
1074 <&gcc GCC_PCIE0_AUX_CLK>;
1075 clock-names = "axi_m",
1082 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>;
1083 assigned-clock-rates = <100000000>;
1085 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
1086 <&gcc GCC_PCIE0_CORE_STICKY_RESET>,
1087 <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>,
1088 <&gcc GCC_PCIE0_AXI_S_ARES>,
1089 <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>,
1090 <&gcc GCC_PCIE0_AXI_M_ARES>,
1091 <&gcc GCC_PCIE0_AUX_ARES>,
1092 <&gcc GCC_PCIE0_AHB_ARES>;
1093 reset-names = "pipe",
1103 phy-names = "pciephy";
1104 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
1105 <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>;
1106 interconnect-names = "pcie-mem", "cpu-pcie";
1113 bus-range = <0x01 0xff>;
1115 #address-cells = <3>;
1116 #size-cells = <2>;
1122 thermal_zones: thermal-zones {
1123 cpu0-thermal {
1124 polling-delay-passive = <100>;
1125 thermal-sensors = <&tsens 14>;
1128 cpu-critical {
1134 cpu-passive {
1142 cpu1-thermal {
1143 polling-delay-passive = <100>;
1144 thermal-sensors = <&tsens 12>;
1147 cpu-critical {
1153 cpu-passive {
1161 cpu2-thermal {
1162 polling-delay-passive = <100>;
1163 thermal-sensors = <&tsens 11>;
1166 cpu-critical {
1172 cpu-passive {
1180 cpu3-thermal {
1181 polling-delay-passive = <100>;
1182 thermal-sensors = <&tsens 13>;
1185 cpu-critical {
1191 cpu-passive {
1199 wcss-tile2-thermal {
1200 thermal-sensors = <&tsens 9>;
1203 wcss-tile2-critical {
1211 wcss-tile3-thermal {
1212 thermal-sensors = <&tsens 10>;
1215 wcss-tile3-critical {
1223 top-glue-thermal {
1224 thermal-sensors = <&tsens 15>;
1227 top-glue-critical {
1237 compatible = "arm,armv8-timer";