Lines Matching +full:ipq6018 +full:- +full:a53pll
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
23 xo_board: xo-board-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 next-level-cache = <&L2_0>;
40 operating-points-v2 = <&cpu_opp_table>;
45 compatible = "arm,cortex-a53";
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
50 operating-points-v2 = <&cpu_opp_table>;
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 next-level-cache = <&L2_0>;
60 operating-points-v2 = <&cpu_opp_table>;
65 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 next-level-cache = <&L2_0>;
70 operating-points-v2 = <&cpu_opp_table>;
73 L2_0: l2-cache {
75 cache-level = <2>;
76 cache-unified;
82 compatible = "qcom,scm-ipq5332", "qcom,scm";
83 qcom,dload-mode = <&tcsr 0x6100>;
93 cpu_opp_table: opp-table-cpu {
94 compatible = "operating-points-v2-kryo-cpu";
95 opp-shared;
96 nvmem-cells = <&cpu_speed_bin>;
98 opp-1100000000 {
99 opp-hz = /bits/ 64 <1100000000>;
100 opp-supported-hw = <0x7>;
101 clock-latency-ns = <200000>;
104 opp-1500000000 {
105 opp-hz = /bits/ 64 <1500000000>;
106 opp-supported-hw = <0x3>;
107 clock-latency-ns = <200000>;
112 compatible = "arm,cortex-a53-pmu";
117 compatible = "arm,psci-1.0";
121 reserved-memory {
122 #address-cells = <2>;
123 #size-cells = <2>;
128 no-map;
133 no-map;
138 no-map;
144 no-map;
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
157 compatible = "qcom,ipq5332-usb-hsphy";
164 #phy-cells = <0>;
170 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
172 #address-cells = <1>;
173 #size-cells = <1>;
175 cpu_speed_bin: cpu-speed-bin@1d {
182 compatible = "qcom,prng-ee";
185 clock-names = "core";
189 compatible = "qcom,ipq5332-tlmm";
192 gpio-controller;
193 #gpio-cells = <2>;
194 gpio-ranges = <&tlmm 0 0 53>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
198 serial_0_pins: serial0-state {
201 drive-strength = <8>;
202 bias-pull-up;
206 gcc: clock-controller@1800000 {
207 compatible = "qcom,ipq5332-gcc";
209 #clock-cells = <1>;
210 #reset-cells = <1>;
211 #power-domain-cells = <1>;
220 compatible = "qcom,tcsr-mutex";
222 #hwlock-cells = <1>;
226 compatible = "qcom,tcsr-ipq5332", "syscon";
231 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
236 interrupt-names = "hc_irq", "pwr_irq";
241 clock-names = "iface", "core", "xo";
245 blsp_dma: dma-controller@7884000 {
246 compatible = "qcom,bam-v1.7.0";
250 clock-names = "bam_clk";
251 #dma-cells = <1>;
256 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
261 clock-names = "core", "iface";
266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
271 clock-names = "core", "iface";
273 dma-names = "tx", "rx";
278 compatible = "qcom,spi-qup-v2.2.1";
280 #address-cells = <1>;
281 #size-cells = <0>;
285 clock-names = "core", "iface";
287 dma-names = "tx", "rx";
292 compatible = "qcom,i2c-qup-v2.2.1";
294 #address-cells = <1>;
295 #size-cells = <0>;
299 clock-names = "core", "iface";
301 dma-names = "tx", "rx";
306 compatible = "qcom,spi-qup-v2.2.1";
308 #address-cells = <1>;
309 #size-cells = <0>;
313 clock-names = "core", "iface";
315 dma-names = "tx", "rx";
320 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
324 interrupt-names = "hs_phy_irq";
330 clock-names = "core",
337 qcom,select-utmi-as-pipe-clk;
339 #address-cells = <1>;
340 #size-cells = <1>;
349 clock-names = "ref";
351 phy-names = "usb2-phy";
353 tx-fifo-resize;
354 snps,is-utmi-l1-suspend;
355 snps,hird-threshold = /bits/ 8 <0x0>;
361 intc: interrupt-controller@b000000 {
362 compatible = "qcom,msm-qgic2";
368 interrupt-controller;
369 #interrupt-cells = <3>;
370 #address-cells = <1>;
371 #size-cells = <1>;
375 compatible = "arm,gic-v2m-frame";
377 msi-controller;
381 compatible = "arm,gic-v2m-frame";
383 msi-controller;
387 compatible = "arm,gic-v2m-frame";
389 msi-controller;
394 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
398 timeout-sec = <30>;
402 compatible = "qcom,ipq5332-apcs-apps-global",
403 "qcom,ipq6018-apcs-apps-global";
405 #clock-cells = <1>;
406 clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
407 clock-names = "pll", "xo", "gpll0";
408 #mbox-cells = <1>;
411 a53pll: clock@b116000 {
412 compatible = "qcom,ipq5332-a53pll";
414 #clock-cells = <0>;
416 clock-names = "xo";
420 compatible = "arm,armv7-timer-mem";
422 #address-cells = <1>;
423 #size-cells = <1>;
431 frame-number = <0>;
437 frame-number = <1>;
444 frame-number = <2>;
451 frame-number = <3>;
458 frame-number = <4>;
465 frame-number = <5>;
472 frame-number = <6>;
479 compatible = "arm,armv8-timer";