Lines Matching +full:0 +full:x4a800000
21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 reg = <0x2>;
67 reg = <0x3>;
84 qcom,dload-mode = <&tcsr 0x6100>;
91 reg = <0x0 0x40000000 0x0 0x0>;
101 opp-supported-hw = <0x7>;
107 opp-supported-hw = <0x3>;
128 reg = <0x0 0x4a100000 0x0 0x400000>;
133 reg = <0x0 0x4a500000 0x0 0x100000>;
138 reg = <0x0 0x4a600000 0x0 0x200000>;
144 reg = <0x0 0x4a800000 0x0 0x100000>;
151 soc@0 {
155 ranges = <0 0 0 0xffffffff>;
159 reg = <0x0007b000 0x12c>;
165 #phy-cells = <0>;
172 reg = <0x000a4000 0x721>;
177 reg = <0x1d 0x2>;
184 reg = <0x000e3000 0x1000>;
191 reg = <0x01000000 0x300000>;
195 gpio-ranges = <&tlmm 0 0 53>;
209 reg = <0x01800000 0x80000>;
215 <0>,
216 <0>,
217 <0>;
222 reg = <0x01905000 0x20000>;
228 reg = <0x01937000 0x21000>;
233 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
248 reg = <0x07884000 0x1d000>;
253 qcom,ee = <0>;
258 reg = <0x078af000 0x200>;
268 reg = <0x078b0000 0x200>;
280 reg = <0x078b5000 0x600>;
282 #size-cells = <0>;
294 reg = <0x078b6000 0x600>;
296 #size-cells = <0>;
308 reg = <0x078b7000 0x600>;
310 #size-cells = <0>;
322 reg = <0x08af8800 0x400>;
353 reg = <0x08a00000 0xe000>;
361 snps,hird-threshold = /bits/ 8 <0x0>;
369 reg = <0x0b000000 0x1000>, /* GICD */
370 <0x0b002000 0x1000>, /* GICC */
371 <0x0b001000 0x1000>, /* GICH */
372 <0x0b004000 0x1000>; /* GICV */
378 ranges = <0 0x0b00c000 0x3000>;
380 v2m0: v2m@0 {
382 reg = <0x00000000 0xffd>;
388 reg = <0x00001000 0xffd>;
394 reg = <0x00002000 0xffd>;
401 reg = <0x0b017000 0x1000>;
410 reg = <0x0b111000 0x1000>;
419 reg = <0x0b116000 0x40>;
420 #clock-cells = <0>;
427 reg = <0x0b120000 0x1000>;
433 reg = <0x0b121000 0x1000>,
434 <0x0b122000 0x1000>;
437 frame-number = <0>;
441 reg = <0x0b123000 0x1000>;
448 reg = <0x0b124000 0x1000>;
455 reg = <0x0b125000 0x1000>;
462 reg = <0x0b126000 0x1000>;
469 reg = <0x0b127000 0x1000>;
476 reg = <0x0b128000 0x1000>;