Lines Matching +full:0 +full:x0b116000
20 #clock-cells = <0>;
25 #clock-cells = <0>;
31 #size-cells = <0>;
33 CPU0: cpu@0 {
36 reg = <0x0>;
46 reg = <0x1>;
56 reg = <0x2>;
66 reg = <0x3>;
83 qcom,dload-mode = <&tcsr 0x6100>;
90 reg = <0x0 0x40000000 0x0 0x0>;
100 opp-supported-hw = <0x7>;
106 opp-supported-hw = <0x3>;
127 reg = <0x0 0x4a100000 0x0 0x400000>;
132 reg = <0x0 0x4a500000 0x0 0x100000>;
137 reg = <0x0 0x4a600000 0x0 0x200000>;
143 reg = <0x0 0x4a800000 0x0 0x100000>;
150 soc@0 {
154 ranges = <0 0 0 0xffffffff>;
158 reg = <0x0007b000 0x12c>;
164 #phy-cells = <0>;
171 reg = <0x000a4000 0x721>;
176 reg = <0x1d 0x2>;
183 reg = <0x000e3000 0x1000>;
190 reg = <0x01000000 0x300000>;
194 gpio-ranges = <&tlmm 0 0 53>;
208 reg = <0x01800000 0x80000>;
214 <0>,
215 <0>,
216 <0>;
221 reg = <0x01905000 0x20000>;
227 reg = <0x01937000 0x21000>;
232 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
247 reg = <0x07884000 0x1d000>;
252 qcom,ee = <0>;
257 reg = <0x078af000 0x200>;
267 reg = <0x078b0000 0x200>;
279 reg = <0x078b5000 0x600>;
281 #size-cells = <0>;
293 reg = <0x078b6000 0x600>;
295 #size-cells = <0>;
307 reg = <0x078b7000 0x600>;
309 #size-cells = <0>;
321 reg = <0x08af8800 0x400>;
347 reg = <0x08a00000 0xe000>;
355 snps,hird-threshold = /bits/ 8 <0x0>;
363 reg = <0x0b000000 0x1000>, /* GICD */
364 <0x0b002000 0x1000>, /* GICC */
365 <0x0b001000 0x1000>, /* GICH */
366 <0x0b004000 0x1000>; /* GICV */
372 ranges = <0 0x0b00c000 0x3000>;
374 v2m0: v2m@0 {
376 reg = <0x00000000 0xffd>;
382 reg = <0x00001000 0xffd>;
388 reg = <0x00002000 0xffd>;
395 reg = <0x0b017000 0x1000>;
404 reg = <0x0b111000 0x1000>;
413 reg = <0x0b116000 0x40>;
414 #clock-cells = <0>;
421 reg = <0x0b120000 0x1000>;
427 reg = <0x0b121000 0x1000>,
428 <0x0b122000 0x1000>;
431 frame-number = <0>;
435 reg = <0x0b123000 0x1000>;
442 reg = <0x0b124000 0x1000>;
449 reg = <0x0b125000 0x1000>;
456 reg = <0x0b126000 0x1000>;
463 reg = <0x0b127000 0x1000>;
470 reg = <0x0b128000 0x1000>;