Lines Matching +full:non +full:- +full:prefetchable
1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 #include <dt-bindings/clock/nvidia,tegra264.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/nvidia,tegra264.h>
7 #include <dt-bindings/reset/nvidia,tegra264.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
15 reserved-memory {
16 #address-cells = <2>;
17 #size-cells = <2>;
21 compatible = "nvidia,tegra264-bpmp-shmem";
23 no-map;
29 compatible = "simple-bus";
31 #address-cells = <2>;
32 #size-cells = <2>;
37 compatible = "nvidia,tegra234-misc";
43 compatible = "nvidia,tegra234-timer";
52 gpcdma: dma-controller@8400000 {
53 compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
87 #dma-cells = <1>;
89 dma-coherent;
90 dma-channel-mask = <0xfffffffe>;
95 compatible = "nvidia,tegra264-hsp";
106 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
109 #mbox-cells = <2>;
113 compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";
115 interrupt-parent = <&pmc>;
118 clock-names = "rtc";
123 compatible = "nvidia,tegra264-utc";
126 reg-names = "tx", "rx";
128 rx-threshold = <4>;
129 tx-threshold = <4>;
134 compatible = "nvidia,tegra264-utc";
137 reg-names = "tx", "rx";
139 rx-threshold = <4>;
140 tx-threshold = <4>;
145 compatible = "arm,sbsa-uart";
152 compatible = "nvidia,tegra264-pmc";
158 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
159 #interrupt-cells = <2>;
160 interrupt-controller;
166 compatible = "simple-bus";
168 #address-cells = <2>;
169 #size-cells = <2>;
172 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
173 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
176 compatible = "arm,smmu-v3";
180 interrupt-names = "eventq", "gerror";
183 #iommu-cells = <1>;
184 dma-coherent;
188 compatible = "arm,smmu-v3";
192 interrupt-names = "eventq", "gerror";
195 #iommu-cells = <1>;
196 dma-coherent;
199 mc: memory-controller@8020000 {
200 compatible = "nvidia,tegra264-mc";
218 reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",
230 #interconnect-cells = <1>;
232 #address-cells = <2>;
233 #size-cells = <2>;
236 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
238 emc: external-memory-controller@8800000 {
239 compatible = "nvidia,tegra264-emc";
244 clock-names = "emc";
246 #interconnect-cells = <0>;
252 compatible = "arm,smmu-v3";
256 interrupt-names = "eventq", "gerror";
259 #iommu-cells = <1>;
260 dma-coherent;
264 compatible = "arm,smmu-v3";
268 interrupt-names = "eventq", "gerror";
271 #iommu-cells = <1>;
272 dma-coherent;
275 gic: interrupt-controller@46000000 {
276 compatible = "arm,gic-v3";
279 interrupt-parent = <&gic>;
282 redistributor-stride = <0x0 0x40000>;
283 #redistributor-regions = <1>;
284 #interrupt-cells = <3>;
285 interrupt-controller;
287 #address-cells = <2>;
288 #size-cells = <2>;
292 its: msi-controller@40000 {
293 compatible = "arm,gic-v3-its";
295 #msi-cells = <1>;
296 msi-controller;
303 compatible = "simple-bus";
304 #address-cells = <2>;
305 #size-cells = <2>;
310 compatible = "arm,smmu-v3";
314 interrupt-names = "eventq", "gerror";
317 #iommu-cells = <1>;
318 dma-coherent;
324 compatible = "simple-bus";
325 #address-cells = <2>;
326 #size-cells = <2>;
328 …ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/…
329 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
333 #address-cells = <1>;
334 #size-cells = <0>;
342 enable-method = "psci";
344 i-cache-size = <65536>;
345 i-cache-line-size = <64>;
346 i-cache-sets = <256>;
347 d-cache-size = <65536>;
348 d-cache-line-size = <64>;
349 d-cache-sets = <256>;
358 enable-method = "psci";
360 i-cache-size = <65536>;
361 i-cache-line-size = <64>;
362 i-cache-sets = <256>;
363 d-cache-size = <65536>;
364 d-cache-line-size = <64>;
365 d-cache-sets = <256>;
370 compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
373 memory-region = <&shmem_bpmp>;
374 #clock-cells = <1>;
375 #reset-cells = <1>;
376 #power-domain-cells = <1>;
379 compatible = "nvidia,tegra186-bpmp-i2c";
380 nvidia,bpmp-bus-id = <5>;
381 #address-cells = <1>;
382 #size-cells = <0>;
386 compatible = "nvidia,tegra186-bpmp-thermal";
387 #thermal-sensor-cells = <1>;
392 compatible = "arm,armv8-pmuv3";
398 compatible = "arm,psci-1.0";
404 compatible = "arm,armv8-timer";