Lines Matching +full:tegra20 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "simple-bus";
22 #address-cells = <2>;
23 #size-cells = <2>;
27 compatible = "nvidia,tegra234-misc";
34 compatible = "nvidia,tegra234-timer";
56 compatible = "nvidia,tegra234-gpio";
57 reg-names = "security", "gpio";
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 #gpio-cells = <2>;
111 gpio-controller;
112 gpio-ranges = <&pinmux 0 0 164>;
116 compatible = "nvidia,tegra234-pinmux";
120 gpcdma: dma-controller@2600000 {
121 compatible = "nvidia,tegra234-gpcdma",
122 "nvidia,tegra186-gpcdma";
125 reset-names = "gpcdma";
158 #dma-cells = <1>;
160 dma-channel-mask = <0xfffffffe>;
161 dma-coherent;
165 compatible = "nvidia,tegra234-aconnect",
166 "nvidia,tegra210-aconnect";
169 clock-names = "ape", "apb2ape";
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
173 #address-cells = <2>;
174 #size-cells = <2>;
178 compatible = "nvidia,tegra234-ahub";
181 clock-names = "ahub";
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
184 assigned-clock-rates = <81600000>;
187 #address-cells = <2>;
188 #size-cells = <2>;
191 tegra_i2s1: i2s@2901000 {
192 compatible = "nvidia,tegra234-i2s",
193 "nvidia,tegra210-i2s";
197 clock-names = "i2s", "sync_input";
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
200 assigned-clock-rates = <1536000>;
201 sound-name-prefix = "I2S1";
205 tegra_i2s2: i2s@2901100 {
206 compatible = "nvidia,tegra234-i2s",
207 "nvidia,tegra210-i2s";
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S2";
219 tegra_i2s3: i2s@2901200 {
220 compatible = "nvidia,tegra234-i2s",
221 "nvidia,tegra210-i2s";
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S3";
233 tegra_i2s4: i2s@2901300 {
234 compatible = "nvidia,tegra234-i2s",
235 "nvidia,tegra210-i2s";
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S4";
247 tegra_i2s5: i2s@2901400 {
248 compatible = "nvidia,tegra234-i2s",
249 "nvidia,tegra210-i2s";
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S5";
261 tegra_i2s6: i2s@2901500 {
262 compatible = "nvidia,tegra234-i2s",
263 "nvidia,tegra210-i2s";
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S6";
276 compatible = "nvidia,tegra234-sfc",
277 "nvidia,tegra210-sfc";
279 sound-name-prefix = "SFC1";
284 compatible = "nvidia,tegra234-sfc",
285 "nvidia,tegra210-sfc";
287 sound-name-prefix = "SFC2";
292 compatible = "nvidia,tegra234-sfc",
293 "nvidia,tegra210-sfc";
295 sound-name-prefix = "SFC3";
300 compatible = "nvidia,tegra234-sfc",
301 "nvidia,tegra210-sfc";
303 sound-name-prefix = "SFC4";
308 compatible = "nvidia,tegra234-amx",
309 "nvidia,tegra194-amx";
311 sound-name-prefix = "AMX1";
316 compatible = "nvidia,tegra234-amx",
317 "nvidia,tegra194-amx";
319 sound-name-prefix = "AMX2";
324 compatible = "nvidia,tegra234-amx",
325 "nvidia,tegra194-amx";
327 sound-name-prefix = "AMX3";
332 compatible = "nvidia,tegra234-amx",
333 "nvidia,tegra194-amx";
335 sound-name-prefix = "AMX4";
340 compatible = "nvidia,tegra234-adx",
341 "nvidia,tegra210-adx";
343 sound-name-prefix = "ADX1";
348 compatible = "nvidia,tegra234-adx",
349 "nvidia,tegra210-adx";
351 sound-name-prefix = "ADX2";
356 compatible = "nvidia,tegra234-adx",
357 "nvidia,tegra210-adx";
359 sound-name-prefix = "ADX3";
364 compatible = "nvidia,tegra234-adx",
365 "nvidia,tegra210-adx";
367 sound-name-prefix = "ADX4";
373 compatible = "nvidia,tegra234-dmic",
374 "nvidia,tegra210-dmic";
377 clock-names = "dmic";
378 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
380 assigned-clock-rates = <3072000>;
381 sound-name-prefix = "DMIC1";
386 compatible = "nvidia,tegra234-dmic",
387 "nvidia,tegra210-dmic";
390 clock-names = "dmic";
391 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
393 assigned-clock-rates = <3072000>;
394 sound-name-prefix = "DMIC2";
399 compatible = "nvidia,tegra234-dmic",
400 "nvidia,tegra210-dmic";
403 clock-names = "dmic";
404 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
405 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
406 assigned-clock-rates = <3072000>;
407 sound-name-prefix = "DMIC3";
412 compatible = "nvidia,tegra234-dmic",
413 "nvidia,tegra210-dmic";
416 clock-names = "dmic";
417 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
418 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
419 assigned-clock-rates = <3072000>;
420 sound-name-prefix = "DMIC4";
425 compatible = "nvidia,tegra234-dspk",
426 "nvidia,tegra186-dspk";
429 clock-names = "dspk";
430 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
431 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
432 assigned-clock-rates = <12288000>;
433 sound-name-prefix = "DSPK1";
438 compatible = "nvidia,tegra234-dspk",
439 "nvidia,tegra186-dspk";
442 clock-names = "dspk";
443 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
444 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
445 assigned-clock-rates = <12288000>;
446 sound-name-prefix = "DSPK2";
450 tegra_ope1: processing-engine@2908000 {
451 compatible = "nvidia,tegra234-ope",
452 "nvidia,tegra210-ope";
454 sound-name-prefix = "OPE1";
457 #address-cells = <2>;
458 #size-cells = <2>;
462 compatible = "nvidia,tegra234-peq",
463 "nvidia,tegra210-peq";
467 dynamic-range-compressor@2908200 {
468 compatible = "nvidia,tegra234-mbdrc",
469 "nvidia,tegra210-mbdrc";
475 compatible = "nvidia,tegra234-mvc",
476 "nvidia,tegra210-mvc";
478 sound-name-prefix = "MVC1";
483 compatible = "nvidia,tegra234-mvc",
484 "nvidia,tegra210-mvc";
486 sound-name-prefix = "MVC2";
491 compatible = "nvidia,tegra234-amixer",
492 "nvidia,tegra210-amixer";
494 sound-name-prefix = "MIXER1";
499 compatible = "nvidia,tegra234-admaif",
500 "nvidia,tegra186-admaif";
522 dma-names = "rx1", "tx1",
544 interconnect-names = "dma-mem", "write";
550 compatible = "nvidia,tegra234-asrc",
551 "nvidia,tegra186-asrc";
553 sound-name-prefix = "ASRC1";
558 adma: dma-controller@2930000 {
559 compatible = "nvidia,tegra234-adma",
560 "nvidia,tegra186-adma";
562 interrupt-parent = <&agic>;
595 #dma-cells = <1>;
597 clock-names = "d_audio";
601 agic: interrupt-controller@2a40000 {
602 compatible = "nvidia,tegra234-agic",
603 "nvidia,tegra210-agic";
604 #interrupt-cells = <3>;
605 interrupt-controller;
612 clock-names = "clk";
617 mc: memory-controller@2c00000 {
618 compatible = "nvidia,tegra234-mc";
619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
637 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
641 #interconnect-cells = <1>;
644 #address-cells = <2>;
645 #size-cells = <2>;
665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
667 emc: external-memory-controller@2c60000 {
668 compatible = "nvidia,tegra234-emc";
673 clock-names = "emc";
676 #interconnect-cells = <0>;
683 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
692 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
698 dma-names = "rx", "tx";
703 compatible = "nvidia,tegra194-i2c";
707 #address-cells = <1>;
708 #size-cells = <0>;
709 clock-frequency = <400000>;
712 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
713 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
714 clock-names = "div-clk", "parent";
716 reset-names = "i2c";
718 dma-names = "rx", "tx";
722 compatible = "nvidia,tegra194-i2c";
725 #address-cells = <1>;
726 #size-cells = <0>;
728 clock-frequency = <400000>;
731 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
732 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
733 clock-names = "div-clk", "parent";
735 reset-names = "i2c";
737 dma-names = "rx", "tx";
741 compatible = "nvidia,tegra194-i2c";
744 #address-cells = <1>;
745 #size-cells = <0>;
747 clock-frequency = <100000>;
750 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
751 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
752 clock-names = "div-clk", "parent";
754 reset-names = "i2c";
756 dma-names = "rx", "tx";
760 compatible = "nvidia,tegra194-i2c";
763 #address-cells = <1>;
764 #size-cells = <0>;
766 clock-frequency = <100000>;
769 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
770 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
771 clock-names = "div-clk", "parent";
773 reset-names = "i2c";
775 dma-names = "rx", "tx";
779 compatible = "nvidia,tegra194-i2c";
782 #address-cells = <1>;
783 #size-cells = <0>;
785 clock-frequency = <100000>;
788 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
789 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
790 clock-names = "div-clk", "parent";
792 reset-names = "i2c";
794 dma-names = "rx", "tx";
798 compatible = "arm,sbsa-uart";
805 compatible = "nvidia,tegra194-i2c";
808 #address-cells = <1>;
809 #size-cells = <0>;
811 clock-frequency = <100000>;
814 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
815 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
816 clock-names = "div-clk", "parent";
818 reset-names = "i2c";
820 dma-names = "rx", "tx";
824 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
827 #address-cells = <1>;
828 #size-cells = <0>;
830 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
831 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
832 clock-names = "spi";
835 reset-names = "spi";
837 dma-names = "rx", "tx";
838 dma-coherent;
843 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
846 #address-cells = <1>;
847 #size-cells = <0>;
849 clock-names = "spi";
851 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
852 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
854 reset-names = "spi";
856 dma-names = "rx", "tx";
857 dma-coherent;
862 compatible = "nvidia,tegra234-qspi";
865 #address-cells = <1>;
866 #size-cells = <0>;
869 clock-names = "qspi", "qspi_out";
875 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
879 reset-names = "pwm";
881 #pwm-cells = <2>;
885 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
889 reset-names = "pwm";
891 #pwm-cells = <2>;
895 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
899 reset-names = "pwm";
901 #pwm-cells = <2>;
905 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
909 reset-names = "pwm";
911 #pwm-cells = <2>;
915 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
919 reset-names = "pwm";
921 #pwm-cells = <2>;
925 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
929 reset-names = "pwm";
931 #pwm-cells = <2>;
935 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
939 reset-names = "pwm";
941 #pwm-cells = <2>;
945 compatible = "nvidia,tegra234-qspi";
948 #address-cells = <1>;
949 #size-cells = <0>;
952 clock-names = "qspi", "qspi_out";
958 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
963 clock-names = "sdhci", "tmclk";
964 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
966 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
969 reset-names = "sdhci";
972 interconnect-names = "dma-mem", "write";
974 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
975 pinctrl-0 = <&sdmmc1_3v3>;
976 pinctrl-1 = <&sdmmc1_1v8>;
977 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
978 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
979 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
980 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
981 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
982 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
983 nvidia,default-tap = <14>;
984 nvidia,default-trim = <0x8>;
985 sd-uhs-sdr25;
986 sd-uhs-sdr50;
987 sd-uhs-ddr50;
988 sd-uhs-sdr104;
993 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
998 clock-names = "sdhci", "tmclk";
999 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
1001 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
1003 reset-names = "sdhci";
1006 interconnect-names = "dma-mem", "write";
1008 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1009 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1010 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1011 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1012 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1013 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1014 nvidia,default-tap = <0x8>;
1015 nvidia,default-trim = <0x14>;
1016 nvidia,dqs-trim = <40>;
1017 supports-cqe;
1022 compatible = "nvidia,tegra234-hda";
1027 clock-names = "hda", "hda2codec_2x";
1030 reset-names = "hda", "hda2codec_2x";
1031 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
1034 interconnect-names = "dma-mem", "write";
1040 compatible = "nvidia,tegra234-xusb-padctl";
1043 reg-names = "padctl", "ao";
1047 reset-names = "padctl";
1054 clock-names = "trk";
1057 usb2-0 {
1060 #phy-cells = <0>;
1063 usb2-1 {
1066 #phy-cells = <0>;
1069 usb2-2 {
1072 #phy-cells = <0>;
1075 usb2-3 {
1078 #phy-cells = <0>;
1085 usb3-0 {
1088 #phy-cells = <0>;
1091 usb3-1 {
1094 #phy-cells = <0>;
1097 usb3-2 {
1100 #phy-cells = <0>;
1103 usb3-3 {
1106 #phy-cells = <0>;
1113 usb2-0 {
1117 usb2-1 {
1121 usb2-2 {
1125 usb2-3 {
1129 usb3-0 {
1133 usb3-1 {
1137 usb3-2 {
1141 usb3-3 {
1148 compatible = "nvidia,tegra234-xudc";
1151 reg-names = "base", "fpci";
1157 clock-names = "dev", "ss", "ss_src", "fs_src";
1160 interconnect-names = "dma-mem", "write";
1162 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1164 power-domain-names = "dev", "ss";
1165 nvidia,xusb-padctl = <&xusb_padctl>;
1166 dma-coherent;
1171 compatible = "nvidia,tegra234-xusb";
1175 reg-names = "hcd", "fpci", "bar2";
1189 clock-names = "xusb_host", "xusb_falcon_src",
1195 interconnect-names = "dma-mem", "write";
1198 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1200 power-domain-names = "xusb_host", "xusb_ss";
1202 nvidia,xusb-padctl = <&xusb_padctl>;
1203 dma-coherent;
1208 compatible = "nvidia,tegra234-efuse";
1211 clock-names = "fuse";
1214 hte_lic: hardware-timestamp@3aa0000 {
1215 compatible = "nvidia,tegra234-gte-lic";
1218 nvidia,int-threshold = <1>;
1219 #timestamp-cells = <1>;
1223 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1234 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1237 #mbox-cells = <2>;
1241 compatible = "nvidia,tegra234-p2u";
1243 reg-names = "ctl";
1245 #phy-cells = <0>;
1249 compatible = "nvidia,tegra234-p2u";
1251 reg-names = "ctl";
1253 #phy-cells = <0>;
1257 compatible = "nvidia,tegra234-p2u";
1259 reg-names = "ctl";
1261 #phy-cells = <0>;
1265 compatible = "nvidia,tegra234-p2u";
1267 reg-names = "ctl";
1269 #phy-cells = <0>;
1273 compatible = "nvidia,tegra234-p2u";
1275 reg-names = "ctl";
1277 #phy-cells = <0>;
1281 compatible = "nvidia,tegra234-p2u";
1283 reg-names = "ctl";
1285 #phy-cells = <0>;
1289 compatible = "nvidia,tegra234-p2u";
1291 reg-names = "ctl";
1293 #phy-cells = <0>;
1297 compatible = "nvidia,tegra234-p2u";
1299 reg-names = "ctl";
1301 #phy-cells = <0>;
1305 compatible = "nvidia,tegra234-p2u";
1307 reg-names = "ctl";
1309 #phy-cells = <0>;
1313 compatible = "nvidia,tegra234-p2u";
1315 reg-names = "ctl";
1317 #phy-cells = <0>;
1321 compatible = "nvidia,tegra234-p2u";
1323 reg-names = "ctl";
1325 #phy-cells = <0>;
1329 compatible = "nvidia,tegra234-p2u";
1331 reg-names = "ctl";
1333 #phy-cells = <0>;
1337 compatible = "nvidia,tegra234-p2u";
1339 reg-names = "ctl";
1341 #phy-cells = <0>;
1345 compatible = "nvidia,tegra234-p2u";
1347 reg-names = "ctl";
1349 #phy-cells = <0>;
1353 compatible = "nvidia,tegra234-p2u";
1355 reg-names = "ctl";
1357 #phy-cells = <0>;
1361 compatible = "nvidia,tegra234-p2u";
1363 reg-names = "ctl";
1365 #phy-cells = <0>;
1369 compatible = "nvidia,tegra234-p2u";
1371 reg-names = "ctl";
1373 #phy-cells = <0>;
1377 compatible = "nvidia,tegra234-p2u";
1379 reg-names = "ctl";
1381 #phy-cells = <0>;
1385 compatible = "nvidia,tegra234-p2u";
1387 reg-names = "ctl";
1389 #phy-cells = <0>;
1393 compatible = "nvidia,tegra234-p2u";
1395 reg-names = "ctl";
1397 #phy-cells = <0>;
1401 compatible = "nvidia,tegra234-p2u";
1403 reg-names = "ctl";
1405 #phy-cells = <0>;
1409 compatible = "nvidia,tegra234-p2u";
1411 reg-names = "ctl";
1413 #phy-cells = <0>;
1417 compatible = "nvidia,tegra234-p2u";
1419 reg-names = "ctl";
1421 #phy-cells = <0>;
1425 compatible = "nvidia,tegra234-p2u";
1427 reg-names = "ctl";
1429 #phy-cells = <0>;
1433 compatible = "nvidia,tegra234-mgbe";
1437 reg-names = "hypervisor", "mac", "xpcs";
1439 interrupt-names = "common";
1452 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1453 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1454 "rx-pcs", "tx-pcs";
1457 reset-names = "mac", "pcs";
1460 interconnect-names = "dma-mem", "write";
1462 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1467 compatible = "nvidia,tegra234-mgbe";
1471 reg-names = "hypervisor", "mac", "xpcs";
1473 interrupt-names = "common";
1486 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1487 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1488 "rx-pcs", "tx-pcs";
1491 reset-names = "mac", "pcs";
1494 interconnect-names = "dma-mem", "write";
1496 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1501 compatible = "nvidia,tegra234-mgbe";
1505 reg-names = "hypervisor", "mac", "xpcs";
1507 interrupt-names = "common";
1520 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1521 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1522 "rx-pcs", "tx-pcs";
1525 reset-names = "mac", "pcs";
1528 interconnect-names = "dma-mem", "write";
1530 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1535 compatible = "nvidia,tegra234-mgbe";
1539 reg-names = "hypervisor", "mac", "xpcs";
1541 interrupt-names = "common";
1554 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1555 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1556 "rx-pcs", "tx-pcs";
1559 reset-names = "mac", "pcs";
1562 interconnect-names = "dma-mem", "write";
1564 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1569 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1702 stream-match-mask = <0x7f80>;
1703 #global-interrupts = <2>;
1704 #iommu-cells = <1>;
1706 nvidia,memory-controller = <&mc>;
1710 sce-fabric@b600000 {
1711 compatible = "nvidia,tegra234-sce-fabric";
1717 rce-fabric@be00000 {
1718 compatible = "nvidia,tegra234-rce-fabric";
1725 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1735 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1736 #mbox-cells = <2>;
1739 hte_aon: hardware-timestamp@c1e0000 {
1740 compatible = "nvidia,tegra234-gte-aon";
1743 nvidia,int-threshold = <1>;
1744 nvidia,gpio-controller = <&gpio_aon>;
1745 #timestamp-cells = <1>;
1749 compatible = "nvidia,tegra194-i2c";
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1755 clock-frequency = <100000>;
1758 clock-names = "div-clk", "parent";
1759 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1760 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1762 reset-names = "i2c";
1764 dma-names = "rx", "tx";
1768 compatible = "nvidia,tegra194-i2c";
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1774 clock-frequency = <400000>;
1777 clock-names = "div-clk", "parent";
1778 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1779 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1781 reset-names = "i2c";
1783 dma-names = "rx", "tx";
1787 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1793 clock-names = "spi";
1795 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
1796 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1798 reset-names = "spi";
1800 dma-names = "rx", "tx";
1801 dma-coherent;
1806 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
1808 interrupt-parent = <&pmc>;
1811 clock-names = "rtc";
1816 compatible = "nvidia,tegra234-gpio-aon";
1817 reg-names = "security", "gpio";
1824 #interrupt-cells = <2>;
1825 interrupt-controller;
1826 #gpio-cells = <2>;
1827 gpio-controller;
1828 gpio-ranges = <&pinmux_aon 0 0 32>;
1832 compatible = "nvidia,tegra234-pinmux-aon";
1837 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
1841 reset-names = "pwm";
1843 #pwm-cells = <2>;
1847 compatible = "nvidia,tegra234-pmc";
1853 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1855 #interrupt-cells = <2>;
1856 interrupt-controller;
1858 sdmmc1_1v8: sdmmc1-1v8 {
1859 pins = "sdmmc1-hv";
1860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1863 sdmmc1_3v3: sdmmc1-3v3 {
1864 pins = "sdmmc1-hv";
1865 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1868 sdmmc3_1v8: sdmmc3-1v8 {
1869 pins = "sdmmc3-hv";
1870 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1873 sdmmc3_3v3: sdmmc3-3v3 {
1874 pins = "sdmmc3-hv";
1875 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1879 aon-fabric@c600000 {
1880 compatible = "nvidia,tegra234-aon-fabric";
1886 bpmp-fabric@d600000 {
1887 compatible = "nvidia,tegra234-bpmp-fabric";
1893 dce-fabric@de00000 {
1894 compatible = "nvidia,tegra234-sce-fabric";
1901 compatible = "nvidia,tegra234-ccplex-cluster";
1907 gic: interrupt-controller@f400000 {
1908 compatible = "arm,gic-v3";
1911 interrupt-parent = <&gic>;
1914 #redistributor-regions = <1>;
1915 #interrupt-cells = <3>;
1916 interrupt-controller;
1920 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2051 stream-match-mask = <0x7f80>;
2052 #global-interrupts = <1>;
2053 #iommu-cells = <1>;
2055 nvidia,memory-controller = <&mc>;
2060 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2193 stream-match-mask = <0x7f80>;
2194 #global-interrupts = <2>;
2195 #iommu-cells = <1>;
2197 nvidia,memory-controller = <&mc>;
2201 cbb-fabric@13a00000 {
2202 compatible = "nvidia,tegra234-cbb-fabric";
2209 compatible = "nvidia,tegra234-host1x";
2213 reg-names = "common", "hypervisor", "vm";
2223 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
2226 clock-names = "host1x";
2228 #address-cells = <2>;
2229 #size-cells = <2>;
2233 interconnect-names = "dma-mem";
2235 dma-coherent;
2238 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2256 compatible = "nvidia,tegra234-vic";
2260 clock-names = "vic";
2262 reset-names = "vic";
2264 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2267 interconnect-names = "dma-mem", "write";
2269 dma-coherent;
2273 compatible = "nvidia,tegra234-nvdec";
2278 clock-names = "nvdec", "fuse", "tsec_pka";
2280 reset-names = "nvdec";
2281 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2284 interconnect-names = "dma-mem", "write";
2286 dma-coherent;
2288 nvidia,memory-controller = <&mc>;
2294 nvidia,bl-manifest-offset = <0>;
2295 nvidia,bl-data-offset = <0>;
2296 nvidia,bl-code-offset = <0>;
2297 nvidia,os-manifest-offset = <0>;
2298 nvidia,os-data-offset = <0>;
2299 nvidia,os-code-offset = <0>;
2310 compatible = "nvidia,tegra234-pcie";
2311 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2317 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2319 #address-cells = <3>;
2320 #size-cells = <2>;
2322 num-lanes = <4>;
2323 num-viewport = <8>;
2324 linux,pci-domain = <8>;
2327 clock-names = "core";
2331 reset-names = "apb", "core";
2335 interrupt-names = "intr", "msi";
2337 #interrupt-cells = <1>;
2338 interrupt-map-mask = <0 0 0 0>;
2339 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2343 nvidia,aspm-cmrt-us = <60>;
2344 nvidia,aspm-pwr-on-t-us = <20>;
2345 nvidia,aspm-l0s-entrance-latency-us = <3>;
2347 bus-range = <0x0 0xff>;
2350 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2355 interconnect-names = "dma-mem", "write";
2356 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2357 iommu-map-mask = <0x0>;
2358 dma-coherent;
2364 compatible = "nvidia,tegra234-pcie";
2365 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2371 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2373 #address-cells = <3>;
2374 #size-cells = <2>;
2376 num-lanes = <4>;
2377 num-viewport = <8>;
2378 linux,pci-domain = <9>;
2381 clock-names = "core";
2385 reset-names = "apb", "core";
2389 interrupt-names = "intr", "msi";
2391 #interrupt-cells = <1>;
2392 interrupt-map-mask = <0 0 0 0>;
2393 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2397 nvidia,aspm-cmrt-us = <60>;
2398 nvidia,aspm-pwr-on-t-us = <20>;
2399 nvidia,aspm-l0s-entrance-latency-us = <3>;
2401 bus-range = <0x0 0xff>;
2404 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2409 interconnect-names = "dma-mem", "write";
2410 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2411 iommu-map-mask = <0x0>;
2412 dma-coherent;
2418 compatible = "nvidia,tegra234-pcie";
2419 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2425 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2427 #address-cells = <3>;
2428 #size-cells = <2>;
2430 num-lanes = <4>;
2431 num-viewport = <8>;
2432 linux,pci-domain = <10>;
2435 clock-names = "core";
2439 reset-names = "apb", "core";
2443 interrupt-names = "intr", "msi";
2445 #interrupt-cells = <1>;
2446 interrupt-map-mask = <0 0 0 0>;
2447 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2451 nvidia,aspm-cmrt-us = <60>;
2452 nvidia,aspm-pwr-on-t-us = <20>;
2453 nvidia,aspm-l0s-entrance-latency-us = <3>;
2455 bus-range = <0x0 0xff>;
2458 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2463 interconnect-names = "dma-mem", "write";
2464 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2465 iommu-map-mask = <0x0>;
2466 dma-coherent;
2471 pcie-ep@140e0000 {
2472 compatible = "nvidia,tegra234-pcie-ep";
2473 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2478 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2480 num-lanes = <4>;
2483 clock-names = "core";
2487 reset-names = "apb", "core";
2490 interrupt-names = "intr";
2494 nvidia,enable-ext-refclk;
2495 nvidia,aspm-cmrt-us = <60>;
2496 nvidia,aspm-pwr-on-t-us = <20>;
2497 nvidia,aspm-l0s-entrance-latency-us = <3>;
2501 interconnect-names = "dma-mem", "write";
2502 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2503 iommu-map-mask = <0x0>;
2504 dma-coherent;
2510 compatible = "nvidia,tegra234-pcie";
2511 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2517 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2519 #address-cells = <3>;
2520 #size-cells = <2>;
2522 num-lanes = <1>;
2523 num-viewport = <8>;
2524 linux,pci-domain = <1>;
2527 clock-names = "core";
2531 reset-names = "apb", "core";
2535 interrupt-names = "intr", "msi";
2537 #interrupt-cells = <1>;
2538 interrupt-map-mask = <0 0 0 0>;
2539 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2543 nvidia,aspm-cmrt-us = <60>;
2544 nvidia,aspm-pwr-on-t-us = <20>;
2545 nvidia,aspm-l0s-entrance-latency-us = <3>;
2547 bus-range = <0x0 0xff>;
2550 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2555 interconnect-names = "dma-mem", "write";
2556 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2557 iommu-map-mask = <0x0>;
2558 dma-coherent;
2564 compatible = "nvidia,tegra234-pcie";
2565 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2571 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2573 #address-cells = <3>;
2574 #size-cells = <2>;
2576 num-lanes = <1>;
2577 num-viewport = <8>;
2578 linux,pci-domain = <2>;
2581 clock-names = "core";
2585 reset-names = "apb", "core";
2589 interrupt-names = "intr", "msi";
2591 #interrupt-cells = <1>;
2592 interrupt-map-mask = <0 0 0 0>;
2593 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2597 nvidia,aspm-cmrt-us = <60>;
2598 nvidia,aspm-pwr-on-t-us = <20>;
2599 nvidia,aspm-l0s-entrance-latency-us = <3>;
2601 bus-range = <0x0 0xff>;
2604 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2609 interconnect-names = "dma-mem", "write";
2610 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2611 iommu-map-mask = <0x0>;
2612 dma-coherent;
2618 compatible = "nvidia,tegra234-pcie";
2619 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2625 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2627 #address-cells = <3>;
2628 #size-cells = <2>;
2630 num-lanes = <1>;
2631 num-viewport = <8>;
2632 linux,pci-domain = <3>;
2635 clock-names = "core";
2639 reset-names = "apb", "core";
2643 interrupt-names = "intr", "msi";
2645 #interrupt-cells = <1>;
2646 interrupt-map-mask = <0 0 0 0>;
2647 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2651 nvidia,aspm-cmrt-us = <60>;
2652 nvidia,aspm-pwr-on-t-us = <20>;
2653 nvidia,aspm-l0s-entrance-latency-us = <3>;
2655 bus-range = <0x0 0xff>;
2658 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2663 interconnect-names = "dma-mem", "write";
2664 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2665 iommu-map-mask = <0x0>;
2666 dma-coherent;
2672 compatible = "nvidia,tegra234-pcie";
2673 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2679 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2681 #address-cells = <3>;
2682 #size-cells = <2>;
2684 num-lanes = <4>;
2685 num-viewport = <8>;
2686 linux,pci-domain = <4>;
2689 clock-names = "core";
2693 reset-names = "apb", "core";
2697 interrupt-names = "intr", "msi";
2699 #interrupt-cells = <1>;
2700 interrupt-map-mask = <0 0 0 0>;
2701 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2705 nvidia,aspm-cmrt-us = <60>;
2706 nvidia,aspm-pwr-on-t-us = <20>;
2707 nvidia,aspm-l0s-entrance-latency-us = <3>;
2709 bus-range = <0x0 0xff>;
2712 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2717 interconnect-names = "dma-mem", "write";
2718 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2719 iommu-map-mask = <0x0>;
2720 dma-coherent;
2726 compatible = "nvidia,tegra234-pcie";
2727 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2733 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2735 #address-cells = <3>;
2736 #size-cells = <2>;
2738 num-lanes = <4>;
2739 num-viewport = <8>;
2740 linux,pci-domain = <0>;
2743 clock-names = "core";
2747 reset-names = "apb", "core";
2751 interrupt-names = "intr", "msi";
2753 #interrupt-cells = <1>;
2754 interrupt-map-mask = <0 0 0 0>;
2755 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2759 nvidia,aspm-cmrt-us = <60>;
2760 nvidia,aspm-pwr-on-t-us = <20>;
2761 nvidia,aspm-l0s-entrance-latency-us = <3>;
2763 bus-range = <0x0 0xff>;
2766 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2771 interconnect-names = "dma-mem", "write";
2772 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2773 iommu-map-mask = <0x0>;
2774 dma-coherent;
2780 compatible = "nvidia,tegra234-pcie";
2781 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2787 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2789 #address-cells = <3>;
2790 #size-cells = <2>;
2792 num-lanes = <8>;
2793 num-viewport = <8>;
2794 linux,pci-domain = <5>;
2797 clock-names = "core";
2801 reset-names = "apb", "core";
2805 interrupt-names = "intr", "msi";
2807 #interrupt-cells = <1>;
2808 interrupt-map-mask = <0 0 0 0>;
2809 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2813 nvidia,aspm-cmrt-us = <60>;
2814 nvidia,aspm-pwr-on-t-us = <20>;
2815 nvidia,aspm-l0s-entrance-latency-us = <3>;
2817 bus-range = <0x0 0xff>;
2820 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2825 interconnect-names = "dma-mem", "write";
2826 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2827 iommu-map-mask = <0x0>;
2828 dma-coherent;
2833 pcie-ep@141a0000 {
2834 compatible = "nvidia,tegra234-pcie-ep";
2835 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2840 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2842 num-lanes = <8>;
2845 clock-names = "core";
2849 reset-names = "apb", "core";
2852 interrupt-names = "intr";
2856 nvidia,enable-ext-refclk;
2857 nvidia,aspm-cmrt-us = <60>;
2858 nvidia,aspm-pwr-on-t-us = <20>;
2859 nvidia,aspm-l0s-entrance-latency-us = <3>;
2863 interconnect-names = "dma-mem", "write";
2864 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2865 iommu-map-mask = <0x0>;
2866 dma-coherent;
2872 compatible = "nvidia,tegra234-pcie";
2873 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2879 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2881 #address-cells = <3>;
2882 #size-cells = <2>;
2884 num-lanes = <4>;
2885 num-viewport = <8>;
2886 linux,pci-domain = <6>;
2889 clock-names = "core";
2893 reset-names = "apb", "core";
2897 interrupt-names = "intr", "msi";
2899 #interrupt-cells = <1>;
2900 interrupt-map-mask = <0 0 0 0>;
2901 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2905 nvidia,aspm-cmrt-us = <60>;
2906 nvidia,aspm-pwr-on-t-us = <20>;
2907 nvidia,aspm-l0s-entrance-latency-us = <3>;
2909 bus-range = <0x0 0xff>;
2912 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2917 interconnect-names = "dma-mem", "write";
2918 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2919 iommu-map-mask = <0x0>;
2920 dma-coherent;
2925 pcie-ep@141c0000 {
2926 compatible = "nvidia,tegra234-pcie-ep";
2927 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2932 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2934 num-lanes = <4>;
2937 clock-names = "core";
2941 reset-names = "apb", "core";
2944 interrupt-names = "intr";
2948 nvidia,enable-ext-refclk;
2949 nvidia,aspm-cmrt-us = <60>;
2950 nvidia,aspm-pwr-on-t-us = <20>;
2951 nvidia,aspm-l0s-entrance-latency-us = <3>;
2955 interconnect-names = "dma-mem", "write";
2956 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2957 iommu-map-mask = <0x0>;
2958 dma-coherent;
2964 compatible = "nvidia,tegra234-pcie";
2965 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2971 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2973 #address-cells = <3>;
2974 #size-cells = <2>;
2976 num-lanes = <8>;
2977 num-viewport = <8>;
2978 linux,pci-domain = <7>;
2981 clock-names = "core";
2985 reset-names = "apb", "core";
2989 interrupt-names = "intr", "msi";
2991 #interrupt-cells = <1>;
2992 interrupt-map-mask = <0 0 0 0>;
2993 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2997 nvidia,aspm-cmrt-us = <60>;
2998 nvidia,aspm-pwr-on-t-us = <20>;
2999 nvidia,aspm-l0s-entrance-latency-us = <3>;
3001 bus-range = <0x0 0xff>;
3004 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
3009 interconnect-names = "dma-mem", "write";
3010 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3011 iommu-map-mask = <0x0>;
3012 dma-coherent;
3017 pcie-ep@141e0000 {
3018 compatible = "nvidia,tegra234-pcie-ep";
3019 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
3024 reg-names = "appl", "atu_dma", "dbi", "addr_space";
3026 num-lanes = <8>;
3029 clock-names = "core";
3033 reset-names = "apb", "core";
3036 interrupt-names = "intr";
3040 nvidia,enable-ext-refclk;
3041 nvidia,aspm-cmrt-us = <60>;
3042 nvidia,aspm-pwr-on-t-us = <20>;
3043 nvidia,aspm-l0s-entrance-latency-us = <3>;
3047 interconnect-names = "dma-mem", "write";
3048 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3049 iommu-map-mask = <0x0>;
3050 dma-coherent;
3057 compatible = "nvidia,tegra234-sysram", "mmio-sram";
3060 #address-cells = <1>;
3061 #size-cells = <1>;
3064 no-memory-wc;
3068 label = "cpu-bpmp-tx";
3074 label = "cpu-bpmp-rx";
3080 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
3084 #clock-cells = <1>;
3085 #reset-cells = <1>;
3086 #power-domain-cells = <1>;
3091 interconnect-names = "read", "write", "dma-mem", "dma-write";
3095 compatible = "nvidia,tegra186-bpmp-i2c";
3096 nvidia,bpmp-bus-id = <5>;
3097 #address-cells = <1>;
3098 #size-cells = <0>;
3102 compatible = "nvidia,tegra186-bpmp-thermal";
3103 #thermal-sensor-cells = <1>;
3108 #address-cells = <1>;
3109 #size-cells = <0>;
3112 compatible = "arm,cortex-a78";
3116 enable-method = "psci";
3118 operating-points-v2 = <&cl0_opp_tbl>;
3121 i-cache-size = <65536>;
3122 i-cache-line-size = <64>;
3123 i-cache-sets = <256>;
3124 d-cache-size = <65536>;
3125 d-cache-line-size = <64>;
3126 d-cache-sets = <256>;
3127 next-level-cache = <&l2c0_0>;
3131 compatible = "arm,cortex-a78";
3135 enable-method = "psci";
3137 operating-points-v2 = <&cl0_opp_tbl>;
3140 i-cache-size = <65536>;
3141 i-cache-line-size = <64>;
3142 i-cache-sets = <256>;
3143 d-cache-size = <65536>;
3144 d-cache-line-size = <64>;
3145 d-cache-sets = <256>;
3146 next-level-cache = <&l2c0_1>;
3150 compatible = "arm,cortex-a78";
3154 enable-method = "psci";
3156 operating-points-v2 = <&cl0_opp_tbl>;
3159 i-cache-size = <65536>;
3160 i-cache-line-size = <64>;
3161 i-cache-sets = <256>;
3162 d-cache-size = <65536>;
3163 d-cache-line-size = <64>;
3164 d-cache-sets = <256>;
3165 next-level-cache = <&l2c0_2>;
3169 compatible = "arm,cortex-a78";
3173 enable-method = "psci";
3175 operating-points-v2 = <&cl0_opp_tbl>;
3178 i-cache-size = <65536>;
3179 i-cache-line-size = <64>;
3180 i-cache-sets = <256>;
3181 d-cache-size = <65536>;
3182 d-cache-line-size = <64>;
3183 d-cache-sets = <256>;
3184 next-level-cache = <&l2c0_3>;
3188 compatible = "arm,cortex-a78";
3192 enable-method = "psci";
3194 operating-points-v2 = <&cl1_opp_tbl>;
3197 i-cache-size = <65536>;
3198 i-cache-line-size = <64>;
3199 i-cache-sets = <256>;
3200 d-cache-size = <65536>;
3201 d-cache-line-size = <64>;
3202 d-cache-sets = <256>;
3203 next-level-cache = <&l2c1_0>;
3207 compatible = "arm,cortex-a78";
3211 enable-method = "psci";
3213 operating-points-v2 = <&cl1_opp_tbl>;
3216 i-cache-size = <65536>;
3217 i-cache-line-size = <64>;
3218 i-cache-sets = <256>;
3219 d-cache-size = <65536>;
3220 d-cache-line-size = <64>;
3221 d-cache-sets = <256>;
3222 next-level-cache = <&l2c1_1>;
3226 compatible = "arm,cortex-a78";
3230 enable-method = "psci";
3232 operating-points-v2 = <&cl1_opp_tbl>;
3235 i-cache-size = <65536>;
3236 i-cache-line-size = <64>;
3237 i-cache-sets = <256>;
3238 d-cache-size = <65536>;
3239 d-cache-line-size = <64>;
3240 d-cache-sets = <256>;
3241 next-level-cache = <&l2c1_2>;
3245 compatible = "arm,cortex-a78";
3249 enable-method = "psci";
3251 operating-points-v2 = <&cl1_opp_tbl>;
3254 i-cache-size = <65536>;
3255 i-cache-line-size = <64>;
3256 i-cache-sets = <256>;
3257 d-cache-size = <65536>;
3258 d-cache-line-size = <64>;
3259 d-cache-sets = <256>;
3260 next-level-cache = <&l2c1_3>;
3264 compatible = "arm,cortex-a78";
3268 enable-method = "psci";
3270 operating-points-v2 = <&cl2_opp_tbl>;
3273 i-cache-size = <65536>;
3274 i-cache-line-size = <64>;
3275 i-cache-sets = <256>;
3276 d-cache-size = <65536>;
3277 d-cache-line-size = <64>;
3278 d-cache-sets = <256>;
3279 next-level-cache = <&l2c2_0>;
3283 compatible = "arm,cortex-a78";
3287 enable-method = "psci";
3289 operating-points-v2 = <&cl2_opp_tbl>;
3292 i-cache-size = <65536>;
3293 i-cache-line-size = <64>;
3294 i-cache-sets = <256>;
3295 d-cache-size = <65536>;
3296 d-cache-line-size = <64>;
3297 d-cache-sets = <256>;
3298 next-level-cache = <&l2c2_1>;
3302 compatible = "arm,cortex-a78";
3306 enable-method = "psci";
3308 operating-points-v2 = <&cl2_opp_tbl>;
3311 i-cache-size = <65536>;
3312 i-cache-line-size = <64>;
3313 i-cache-sets = <256>;
3314 d-cache-size = <65536>;
3315 d-cache-line-size = <64>;
3316 d-cache-sets = <256>;
3317 next-level-cache = <&l2c2_2>;
3321 compatible = "arm,cortex-a78";
3325 enable-method = "psci";
3327 operating-points-v2 = <&cl2_opp_tbl>;
3330 i-cache-size = <65536>;
3331 i-cache-line-size = <64>;
3332 i-cache-sets = <256>;
3333 d-cache-size = <65536>;
3334 d-cache-line-size = <64>;
3335 d-cache-sets = <256>;
3336 next-level-cache = <&l2c2_3>;
3339 cpu-map {
3395 l2c0_0: l2-cache00 {
3397 cache-size = <262144>;
3398 cache-line-size = <64>;
3399 cache-sets = <512>;
3400 cache-unified;
3401 cache-level = <2>;
3402 next-level-cache = <&l3c0>;
3405 l2c0_1: l2-cache01 {
3407 cache-size = <262144>;
3408 cache-line-size = <64>;
3409 cache-sets = <512>;
3410 cache-unified;
3411 cache-level = <2>;
3412 next-level-cache = <&l3c0>;
3415 l2c0_2: l2-cache02 {
3417 cache-size = <262144>;
3418 cache-line-size = <64>;
3419 cache-sets = <512>;
3420 cache-unified;
3421 cache-level = <2>;
3422 next-level-cache = <&l3c0>;
3425 l2c0_3: l2-cache03 {
3427 cache-size = <262144>;
3428 cache-line-size = <64>;
3429 cache-sets = <512>;
3430 cache-unified;
3431 cache-level = <2>;
3432 next-level-cache = <&l3c0>;
3435 l2c1_0: l2-cache10 {
3437 cache-size = <262144>;
3438 cache-line-size = <64>;
3439 cache-sets = <512>;
3440 cache-unified;
3441 cache-level = <2>;
3442 next-level-cache = <&l3c1>;
3445 l2c1_1: l2-cache11 {
3447 cache-size = <262144>;
3448 cache-line-size = <64>;
3449 cache-sets = <512>;
3450 cache-unified;
3451 cache-level = <2>;
3452 next-level-cache = <&l3c1>;
3455 l2c1_2: l2-cache12 {
3457 cache-size = <262144>;
3458 cache-line-size = <64>;
3459 cache-sets = <512>;
3460 cache-unified;
3461 cache-level = <2>;
3462 next-level-cache = <&l3c1>;
3465 l2c1_3: l2-cache13 {
3467 cache-size = <262144>;
3468 cache-line-size = <64>;
3469 cache-sets = <512>;
3470 cache-unified;
3471 cache-level = <2>;
3472 next-level-cache = <&l3c1>;
3475 l2c2_0: l2-cache20 {
3477 cache-size = <262144>;
3478 cache-line-size = <64>;
3479 cache-sets = <512>;
3480 cache-unified;
3481 cache-level = <2>;
3482 next-level-cache = <&l3c2>;
3485 l2c2_1: l2-cache21 {
3487 cache-size = <262144>;
3488 cache-line-size = <64>;
3489 cache-sets = <512>;
3490 cache-unified;
3491 cache-level = <2>;
3492 next-level-cache = <&l3c2>;
3495 l2c2_2: l2-cache22 {
3497 cache-size = <262144>;
3498 cache-line-size = <64>;
3499 cache-sets = <512>;
3500 cache-unified;
3501 cache-level = <2>;
3502 next-level-cache = <&l3c2>;
3505 l2c2_3: l2-cache23 {
3507 cache-size = <262144>;
3508 cache-line-size = <64>;
3509 cache-sets = <512>;
3510 cache-unified;
3511 cache-level = <2>;
3512 next-level-cache = <&l3c2>;
3515 l3c0: l3-cache0 {
3517 cache-unified;
3518 cache-size = <2097152>;
3519 cache-line-size = <64>;
3520 cache-sets = <2048>;
3521 cache-level = <3>;
3524 l3c1: l3-cache1 {
3526 cache-unified;
3527 cache-size = <2097152>;
3528 cache-line-size = <64>;
3529 cache-sets = <2048>;
3530 cache-level = <3>;
3533 l3c2: l3-cache2 {
3535 cache-unified;
3536 cache-size = <2097152>;
3537 cache-line-size = <64>;
3538 cache-sets = <2048>;
3539 cache-level = <3>;
3543 dsu-pmu0 {
3544 compatible = "arm,dsu-pmu";
3549 dsu-pmu1 {
3550 compatible = "arm,dsu-pmu";
3555 dsu-pmu2 {
3556 compatible = "arm,dsu-pmu";
3562 compatible = "arm,cortex-a78-pmu";
3568 compatible = "arm,psci-1.0";
3574 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3577 mbox-names = "rx", "tx";
3586 clock-names = "pll_a", "plla_out0";
3587 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3590 assigned-clock-parents = <0>,
3595 thermal-zones {
3596 cpu-thermal {
3597 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
3601 gpu-thermal {
3602 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
3606 cv0-thermal {
3607 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
3611 cv1-thermal {
3612 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
3616 cv2-thermal {
3617 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
3621 soc0-thermal {
3622 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
3626 soc1-thermal {
3627 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
3631 soc2-thermal {
3632 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
3636 tj-thermal {
3637 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
3643 compatible = "arm,armv8-timer";
3648 interrupt-parent = <&gic>;
3649 always-on;
3652 cl0_opp_tbl: opp-table-cluster0 {
3653 compatible = "operating-points-v2";
3654 opp-shared;
3656 cl0_ch1_opp1: opp-115200000 {
3657 opp-hz = /bits/ 64 <115200000>;
3658 opp-peak-kBps = <816000>;
3661 cl0_ch1_opp2: opp-192000000 {
3662 opp-hz = /bits/ 64 <192000000>;
3663 opp-peak-kBps = <816000>;
3666 cl0_ch1_opp3: opp-268800000 {
3667 opp-hz = /bits/ 64 <268800000>;
3668 opp-peak-kBps = <816000>;
3671 cl0_ch1_opp4: opp-345600000 {
3672 opp-hz = /bits/ 64 <345600000>;
3673 opp-peak-kBps = <816000>;
3676 cl0_ch1_opp5: opp-422400000 {
3677 opp-hz = /bits/ 64 <422400000>;
3678 opp-peak-kBps = <816000>;
3681 cl0_ch1_opp6: opp-499200000 {
3682 opp-hz = /bits/ 64 <499200000>;
3683 opp-peak-kBps = <816000>;
3686 cl0_ch1_opp7: opp-576000000 {
3687 opp-hz = /bits/ 64 <576000000>;
3688 opp-peak-kBps = <816000>;
3691 cl0_ch1_opp8: opp-652800000 {
3692 opp-hz = /bits/ 64 <652800000>;
3693 opp-peak-kBps = <816000>;
3696 cl0_ch1_opp9: opp-729600000 {
3697 opp-hz = /bits/ 64 <729600000>;
3698 opp-peak-kBps = <816000>;
3701 cl0_ch1_opp10: opp-806400000 {
3702 opp-hz = /bits/ 64 <806400000>;
3703 opp-peak-kBps = <816000>;
3706 cl0_ch1_opp11: opp-883200000 {
3707 opp-hz = /bits/ 64 <883200000>;
3708 opp-peak-kBps = <816000>;
3711 cl0_ch1_opp12: opp-960000000 {
3712 opp-hz = /bits/ 64 <960000000>;
3713 opp-peak-kBps = <816000>;
3716 cl0_ch1_opp13: opp-1036800000 {
3717 opp-hz = /bits/ 64 <1036800000>;
3718 opp-peak-kBps = <816000>;
3721 cl0_ch1_opp14: opp-1113600000 {
3722 opp-hz = /bits/ 64 <1113600000>;
3723 opp-peak-kBps = <1632000>;
3726 cl0_ch1_opp15: opp-1190400000 {
3727 opp-hz = /bits/ 64 <1190400000>;
3728 opp-peak-kBps = <1632000>;
3731 cl0_ch1_opp16: opp-1267200000 {
3732 opp-hz = /bits/ 64 <1267200000>;
3733 opp-peak-kBps = <1632000>;
3736 cl0_ch1_opp17: opp-1344000000 {
3737 opp-hz = /bits/ 64 <1344000000>;
3738 opp-peak-kBps = <1632000>;
3741 cl0_ch1_opp18: opp-1420800000 {
3742 opp-hz = /bits/ 64 <1420800000>;
3743 opp-peak-kBps = <1632000>;
3746 cl0_ch1_opp19: opp-1497600000 {
3747 opp-hz = /bits/ 64 <1497600000>;
3748 opp-peak-kBps = <3200000>;
3751 cl0_ch1_opp20: opp-1574400000 {
3752 opp-hz = /bits/ 64 <1574400000>;
3753 opp-peak-kBps = <3200000>;
3756 cl0_ch1_opp21: opp-1651200000 {
3757 opp-hz = /bits/ 64 <1651200000>;
3758 opp-peak-kBps = <3200000>;
3761 cl0_ch1_opp22: opp-1728000000 {
3762 opp-hz = /bits/ 64 <1728000000>;
3763 opp-peak-kBps = <3200000>;
3766 cl0_ch1_opp23: opp-1804800000 {
3767 opp-hz = /bits/ 64 <1804800000>;
3768 opp-peak-kBps = <3200000>;
3771 cl0_ch1_opp24: opp-1881600000 {
3772 opp-hz = /bits/ 64 <1881600000>;
3773 opp-peak-kBps = <3200000>;
3776 cl0_ch1_opp25: opp-1958400000 {
3777 opp-hz = /bits/ 64 <1958400000>;
3778 opp-peak-kBps = <3200000>;
3781 cl0_ch1_opp26: opp-2035200000 {
3782 opp-hz = /bits/ 64 <2035200000>;
3783 opp-peak-kBps = <3200000>;
3786 cl0_ch1_opp27: opp-2112000000 {
3787 opp-hz = /bits/ 64 <2112000000>;
3788 opp-peak-kBps = <6400000>;
3791 cl0_ch1_opp28: opp-2188800000 {
3792 opp-hz = /bits/ 64 <2188800000>;
3793 opp-peak-kBps = <6400000>;
3796 cl0_ch1_opp29: opp-2201600000 {
3797 opp-hz = /bits/ 64 <2201600000>;
3798 opp-peak-kBps = <6400000>;
3802 cl1_opp_tbl: opp-table-cluster1 {
3803 compatible = "operating-points-v2";
3804 opp-shared;
3806 cl1_ch1_opp1: opp-115200000 {
3807 opp-hz = /bits/ 64 <115200000>;
3808 opp-peak-kBps = <816000>;
3811 cl1_ch1_opp2: opp-192000000 {
3812 opp-hz = /bits/ 64 <192000000>;
3813 opp-peak-kBps = <816000>;
3816 cl1_ch1_opp3: opp-268800000 {
3817 opp-hz = /bits/ 64 <268800000>;
3818 opp-peak-kBps = <816000>;
3821 cl1_ch1_opp4: opp-345600000 {
3822 opp-hz = /bits/ 64 <345600000>;
3823 opp-peak-kBps = <816000>;
3826 cl1_ch1_opp5: opp-422400000 {
3827 opp-hz = /bits/ 64 <422400000>;
3828 opp-peak-kBps = <816000>;
3831 cl1_ch1_opp6: opp-499200000 {
3832 opp-hz = /bits/ 64 <499200000>;
3833 opp-peak-kBps = <816000>;
3836 cl1_ch1_opp7: opp-576000000 {
3837 opp-hz = /bits/ 64 <576000000>;
3838 opp-peak-kBps = <816000>;
3841 cl1_ch1_opp8: opp-652800000 {
3842 opp-hz = /bits/ 64 <652800000>;
3843 opp-peak-kBps = <816000>;
3846 cl1_ch1_opp9: opp-729600000 {
3847 opp-hz = /bits/ 64 <729600000>;
3848 opp-peak-kBps = <816000>;
3851 cl1_ch1_opp10: opp-806400000 {
3852 opp-hz = /bits/ 64 <806400000>;
3853 opp-peak-kBps = <816000>;
3856 cl1_ch1_opp11: opp-883200000 {
3857 opp-hz = /bits/ 64 <883200000>;
3858 opp-peak-kBps = <816000>;
3861 cl1_ch1_opp12: opp-960000000 {
3862 opp-hz = /bits/ 64 <960000000>;
3863 opp-peak-kBps = <816000>;
3866 cl1_ch1_opp13: opp-1036800000 {
3867 opp-hz = /bits/ 64 <1036800000>;
3868 opp-peak-kBps = <816000>;
3871 cl1_ch1_opp14: opp-1113600000 {
3872 opp-hz = /bits/ 64 <1113600000>;
3873 opp-peak-kBps = <1632000>;
3876 cl1_ch1_opp15: opp-1190400000 {
3877 opp-hz = /bits/ 64 <1190400000>;
3878 opp-peak-kBps = <1632000>;
3881 cl1_ch1_opp16: opp-1267200000 {
3882 opp-hz = /bits/ 64 <1267200000>;
3883 opp-peak-kBps = <1632000>;
3886 cl1_ch1_opp17: opp-1344000000 {
3887 opp-hz = /bits/ 64 <1344000000>;
3888 opp-peak-kBps = <1632000>;
3891 cl1_ch1_opp18: opp-1420800000 {
3892 opp-hz = /bits/ 64 <1420800000>;
3893 opp-peak-kBps = <1632000>;
3896 cl1_ch1_opp19: opp-1497600000 {
3897 opp-hz = /bits/ 64 <1497600000>;
3898 opp-peak-kBps = <3200000>;
3901 cl1_ch1_opp20: opp-1574400000 {
3902 opp-hz = /bits/ 64 <1574400000>;
3903 opp-peak-kBps = <3200000>;
3906 cl1_ch1_opp21: opp-1651200000 {
3907 opp-hz = /bits/ 64 <1651200000>;
3908 opp-peak-kBps = <3200000>;
3911 cl1_ch1_opp22: opp-1728000000 {
3912 opp-hz = /bits/ 64 <1728000000>;
3913 opp-peak-kBps = <3200000>;
3916 cl1_ch1_opp23: opp-1804800000 {
3917 opp-hz = /bits/ 64 <1804800000>;
3918 opp-peak-kBps = <3200000>;
3921 cl1_ch1_opp24: opp-1881600000 {
3922 opp-hz = /bits/ 64 <1881600000>;
3923 opp-peak-kBps = <3200000>;
3926 cl1_ch1_opp25: opp-1958400000 {
3927 opp-hz = /bits/ 64 <1958400000>;
3928 opp-peak-kBps = <3200000>;
3931 cl1_ch1_opp26: opp-2035200000 {
3932 opp-hz = /bits/ 64 <2035200000>;
3933 opp-peak-kBps = <3200000>;
3936 cl1_ch1_opp27: opp-2112000000 {
3937 opp-hz = /bits/ 64 <2112000000>;
3938 opp-peak-kBps = <6400000>;
3941 cl1_ch1_opp28: opp-2188800000 {
3942 opp-hz = /bits/ 64 <2188800000>;
3943 opp-peak-kBps = <6400000>;
3946 cl1_ch1_opp29: opp-2201600000 {
3947 opp-hz = /bits/ 64 <2201600000>;
3948 opp-peak-kBps = <6400000>;
3952 cl2_opp_tbl: opp-table-cluster2 {
3953 compatible = "operating-points-v2";
3954 opp-shared;
3956 cl2_ch1_opp1: opp-115200000 {
3957 opp-hz = /bits/ 64 <115200000>;
3958 opp-peak-kBps = <816000>;
3961 cl2_ch1_opp2: opp-192000000 {
3962 opp-hz = /bits/ 64 <192000000>;
3963 opp-peak-kBps = <816000>;
3966 cl2_ch1_opp3: opp-268800000 {
3967 opp-hz = /bits/ 64 <268800000>;
3968 opp-peak-kBps = <816000>;
3971 cl2_ch1_opp4: opp-345600000 {
3972 opp-hz = /bits/ 64 <345600000>;
3973 opp-peak-kBps = <816000>;
3976 cl2_ch1_opp5: opp-422400000 {
3977 opp-hz = /bits/ 64 <422400000>;
3978 opp-peak-kBps = <816000>;
3981 cl2_ch1_opp6: opp-499200000 {
3982 opp-hz = /bits/ 64 <499200000>;
3983 opp-peak-kBps = <816000>;
3986 cl2_ch1_opp7: opp-576000000 {
3987 opp-hz = /bits/ 64 <576000000>;
3988 opp-peak-kBps = <816000>;
3991 cl2_ch1_opp8: opp-652800000 {
3992 opp-hz = /bits/ 64 <652800000>;
3993 opp-peak-kBps = <816000>;
3996 cl2_ch1_opp9: opp-729600000 {
3997 opp-hz = /bits/ 64 <729600000>;
3998 opp-peak-kBps = <816000>;
4001 cl2_ch1_opp10: opp-806400000 {
4002 opp-hz = /bits/ 64 <806400000>;
4003 opp-peak-kBps = <816000>;
4006 cl2_ch1_opp11: opp-883200000 {
4007 opp-hz = /bits/ 64 <883200000>;
4008 opp-peak-kBps = <816000>;
4011 cl2_ch1_opp12: opp-960000000 {
4012 opp-hz = /bits/ 64 <960000000>;
4013 opp-peak-kBps = <816000>;
4016 cl2_ch1_opp13: opp-1036800000 {
4017 opp-hz = /bits/ 64 <1036800000>;
4018 opp-peak-kBps = <816000>;
4021 cl2_ch1_opp14: opp-1113600000 {
4022 opp-hz = /bits/ 64 <1113600000>;
4023 opp-peak-kBps = <1632000>;
4026 cl2_ch1_opp15: opp-1190400000 {
4027 opp-hz = /bits/ 64 <1190400000>;
4028 opp-peak-kBps = <1632000>;
4031 cl2_ch1_opp16: opp-1267200000 {
4032 opp-hz = /bits/ 64 <1267200000>;
4033 opp-peak-kBps = <1632000>;
4036 cl2_ch1_opp17: opp-1344000000 {
4037 opp-hz = /bits/ 64 <1344000000>;
4038 opp-peak-kBps = <1632000>;
4041 cl2_ch1_opp18: opp-1420800000 {
4042 opp-hz = /bits/ 64 <1420800000>;
4043 opp-peak-kBps = <1632000>;
4046 cl2_ch1_opp19: opp-1497600000 {
4047 opp-hz = /bits/ 64 <1497600000>;
4048 opp-peak-kBps = <3200000>;
4051 cl2_ch1_opp20: opp-1574400000 {
4052 opp-hz = /bits/ 64 <1574400000>;
4053 opp-peak-kBps = <3200000>;
4056 cl2_ch1_opp21: opp-1651200000 {
4057 opp-hz = /bits/ 64 <1651200000>;
4058 opp-peak-kBps = <3200000>;
4061 cl2_ch1_opp22: opp-1728000000 {
4062 opp-hz = /bits/ 64 <1728000000>;
4063 opp-peak-kBps = <3200000>;
4066 cl2_ch1_opp23: opp-1804800000 {
4067 opp-hz = /bits/ 64 <1804800000>;
4068 opp-peak-kBps = <3200000>;
4071 cl2_ch1_opp24: opp-1881600000 {
4072 opp-hz = /bits/ 64 <1881600000>;
4073 opp-peak-kBps = <3200000>;
4076 cl2_ch1_opp25: opp-1958400000 {
4077 opp-hz = /bits/ 64 <1958400000>;
4078 opp-peak-kBps = <3200000>;
4081 cl2_ch1_opp26: opp-2035200000 {
4082 opp-hz = /bits/ 64 <2035200000>;
4083 opp-peak-kBps = <3200000>;
4086 cl2_ch1_opp27: opp-2112000000 {
4087 opp-hz = /bits/ 64 <2112000000>;
4088 opp-peak-kBps = <6400000>;
4091 cl2_ch1_opp28: opp-2188800000 {
4092 opp-hz = /bits/ 64 <2188800000>;
4093 opp-peak-kBps = <6400000>;
4096 cl2_ch1_opp29: opp-2201600000 {
4097 opp-hz = /bits/ 64 <2201600000>;
4098 opp-peak-kBps = <6400000>;