Lines Matching +full:0 +full:x15480000
19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
123 reg = <0x0 0x2600000 0x0 0x210000>;
160 dma-channel-mask = <0xfffffffe>;
175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
179 reg = <0x0 0x02900800 0x0 0x800>;
189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
194 reg = <0x0 0x2901000 0x0 0x100>;
208 reg = <0x0 0x2901100 0x0 0x100>;
222 reg = <0x0 0x2901200 0x0 0x100>;
236 reg = <0x0 0x2901300 0x0 0x100>;
250 reg = <0x0 0x2901400 0x0 0x100>;
264 reg = <0x0 0x2901500 0x0 0x100>;
278 reg = <0x0 0x2902000 0x0 0x200>;
286 reg = <0x0 0x2902200 0x0 0x200>;
294 reg = <0x0 0x2902400 0x0 0x200>;
302 reg = <0x0 0x2902600 0x0 0x200>;
310 reg = <0x0 0x2903000 0x0 0x100>;
318 reg = <0x0 0x2903100 0x0 0x100>;
326 reg = <0x0 0x2903200 0x0 0x100>;
334 reg = <0x0 0x2903300 0x0 0x100>;
342 reg = <0x0 0x2903800 0x0 0x100>;
350 reg = <0x0 0x2903900 0x0 0x100>;
358 reg = <0x0 0x2903a00 0x0 0x100>;
366 reg = <0x0 0x2903b00 0x0 0x100>;
375 reg = <0x0 0x2904000 0x0 0x100>;
388 reg = <0x0 0x2904100 0x0 0x100>;
401 reg = <0x0 0x2904200 0x0 0x100>;
414 reg = <0x0 0x2904300 0x0 0x100>;
427 reg = <0x0 0x2905000 0x0 0x100>;
440 reg = <0x0 0x2905100 0x0 0x100>;
453 reg = <0x0 0x2908000 0x0 0x100>;
464 reg = <0x0 0x2908100 0x0 0x100>;
470 reg = <0x0 0x2908200 0x0 0x200>;
477 reg = <0x0 0x290a000 0x0 0x200>;
485 reg = <0x0 0x290a200 0x0 0x200>;
493 reg = <0x0 0x290bb00 0x0 0x800>;
501 reg = <0x0 0x0290f000 0x0 0x1000>;
552 reg = <0x0 0x2910000 0x0 0x2000>;
561 reg = <0x0 0x02930000 0x0 0x20000>;
563 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
606 reg = <0x0 0x02a41000 0x0 0x1000>,
607 <0x0 0x02a42000 0x0 0x2000>;
619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
620 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
621 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
622 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
623 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
624 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
625 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
626 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
627 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
628 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
629 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
630 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
631 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
632 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
633 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
634 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
635 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
636 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
646 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
647 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
648 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
663 * Limit the DMA range for memory clients to [38:0].
665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
669 reg = <0x0 0x02c60000 0x0 0x90000>,
670 <0x0 0x01780000 0x0 0x80000>;
676 #interconnect-cells = <0>;
684 reg = <0x0 0x03100000 0x0 0x10000>;
693 reg = <0x0 0x03140000 0x0 0x10000>;
704 reg = <0x0 0x3160000 0x0 0x100>;
708 #size-cells = <0>;
723 reg = <0x0 0x3180000 0x0 0x100>;
726 #size-cells = <0>;
742 reg = <0x0 0x3190000 0x0 0x100>;
745 #size-cells = <0>;
761 reg = <0x0 0x31b0000 0x0 0x100>;
764 #size-cells = <0>;
780 reg = <0x0 0x31c0000 0x0 0x100>;
783 #size-cells = <0>;
799 reg = <0x0 0x31d0000 0x0 0x10000>;
806 reg = <0x0 0x31e0000 0x0 0x100>;
809 #size-cells = <0>;
825 reg = <0x0 0x03210000 0x0 0x1000>;
828 #size-cells = <0>;
844 reg = <0x0 0x03230000 0x0 0x1000>;
847 #size-cells = <0>;
863 reg = <0x0 0x3270000 0x0 0x1000>;
866 #size-cells = <0>;
876 reg = <0x0 0x3280000 0x0 0x10000>;
886 reg = <0x0 0x3290000 0x0 0x10000>;
896 reg = <0x0 0x32a0000 0x0 0x10000>;
906 reg = <0x0 0x32c0000 0x0 0x10000>;
916 reg = <0x0 0x32d0000 0x0 0x10000>;
926 reg = <0x0 0x32e0000 0x0 0x10000>;
936 reg = <0x0 0x32f0000 0x0 0x10000>;
946 reg = <0x0 0x3300000 0x0 0x1000>;
949 #size-cells = <0>;
959 reg = <0x0 0x03400000 0x0 0x20000>;
975 pinctrl-0 = <&sdmmc1_3v3>;
977 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
978 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
979 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
980 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
981 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
982 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
984 nvidia,default-trim = <0x8>;
994 reg = <0x0 0x03460000 0x0 0x20000>;
1008 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1009 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1010 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1011 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1012 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1013 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1014 nvidia,default-tap = <0x8>;
1015 nvidia,default-trim = <0x14>;
1023 reg = <0x0 0x3510000 0x0 0x10000>;
1041 reg = <0x0 0x03520000 0x0 0x20000>,
1042 <0x0 0x03540000 0x0 0x10000>;
1057 usb2-0 {
1060 #phy-cells = <0>;
1066 #phy-cells = <0>;
1072 #phy-cells = <0>;
1078 #phy-cells = <0>;
1085 usb3-0 {
1088 #phy-cells = <0>;
1094 #phy-cells = <0>;
1100 #phy-cells = <0>;
1106 #phy-cells = <0>;
1113 usb2-0 {
1129 usb3-0 {
1149 reg = <0x0 0x03550000 0x0 0x8000>,
1150 <0x0 0x03558000 0x0 0x8000>;
1172 reg = <0x0 0x03610000 0x0 0x40000>,
1173 <0x0 0x03600000 0x0 0x10000>,
1174 <0x0 0x03650000 0x0 0x10000>;
1209 reg = <0x0 0x03810000 0x0 0x10000>;
1216 reg = <0x0 0x3aa0000 0x0 0x10000>;
1224 reg = <0x0 0x03c00000 0x0 0xa0000>;
1242 reg = <0x0 0x03e00000 0x0 0x10000>;
1245 #phy-cells = <0>;
1250 reg = <0x0 0x03e10000 0x0 0x10000>;
1253 #phy-cells = <0>;
1258 reg = <0x0 0x03e20000 0x0 0x10000>;
1261 #phy-cells = <0>;
1266 reg = <0x0 0x03e30000 0x0 0x10000>;
1269 #phy-cells = <0>;
1274 reg = <0x0 0x03e40000 0x0 0x10000>;
1277 #phy-cells = <0>;
1282 reg = <0x0 0x03e50000 0x0 0x10000>;
1285 #phy-cells = <0>;
1290 reg = <0x0 0x03e60000 0x0 0x10000>;
1293 #phy-cells = <0>;
1298 reg = <0x0 0x03e70000 0x0 0x10000>;
1301 #phy-cells = <0>;
1306 reg = <0x0 0x03e90000 0x0 0x10000>;
1309 #phy-cells = <0>;
1314 reg = <0x0 0x03ea0000 0x0 0x10000>;
1317 #phy-cells = <0>;
1322 reg = <0x0 0x03eb0000 0x0 0x10000>;
1325 #phy-cells = <0>;
1330 reg = <0x0 0x03ec0000 0x0 0x10000>;
1333 #phy-cells = <0>;
1338 reg = <0x0 0x03ed0000 0x0 0x10000>;
1341 #phy-cells = <0>;
1346 reg = <0x0 0x03ee0000 0x0 0x10000>;
1349 #phy-cells = <0>;
1354 reg = <0x0 0x03ef0000 0x0 0x10000>;
1357 #phy-cells = <0>;
1362 reg = <0x0 0x03f00000 0x0 0x10000>;
1365 #phy-cells = <0>;
1370 reg = <0x0 0x03f20000 0x0 0x10000>;
1373 #phy-cells = <0>;
1378 reg = <0x0 0x03f30000 0x0 0x10000>;
1381 #phy-cells = <0>;
1386 reg = <0x0 0x03f40000 0x0 0x10000>;
1389 #phy-cells = <0>;
1394 reg = <0x0 0x03f50000 0x0 0x10000>;
1397 #phy-cells = <0>;
1402 reg = <0x0 0x03f60000 0x0 0x10000>;
1405 #phy-cells = <0>;
1410 reg = <0x0 0x03f70000 0x0 0x10000>;
1413 #phy-cells = <0>;
1418 reg = <0x0 0x03f80000 0x0 0x10000>;
1421 #phy-cells = <0>;
1426 reg = <0x0 0x03f90000 0x0 0x10000>;
1429 #phy-cells = <0>;
1434 reg = <0x0 0x06800000 0x0 0x10000>,
1435 <0x0 0x06810000 0x0 0x10000>,
1436 <0x0 0x068a0000 0x0 0x10000>;
1468 reg = <0x0 0x06900000 0x0 0x10000>,
1469 <0x0 0x06910000 0x0 0x10000>,
1470 <0x0 0x069a0000 0x0 0x10000>;
1502 reg = <0x0 0x06a00000 0x0 0x10000>,
1503 <0x0 0x06a10000 0x0 0x10000>,
1504 <0x0 0x06aa0000 0x0 0x10000>;
1536 reg = <0x0 0x06b00000 0x0 0x10000>,
1537 <0x0 0x06b10000 0x0 0x10000>,
1538 <0x0 0x06ba0000 0x0 0x10000>;
1570 reg = <0x0 0x8000000 0x0 0x1000000>,
1571 <0x0 0x7000000 0x0 0x1000000>;
1702 stream-match-mask = <0x7f80>;
1712 reg = <0x0 0xb600000 0x0 0x40000>;
1719 reg = <0x0 0xbe00000 0x0 0x40000>;
1726 reg = <0x0 0x0c150000 0x0 0x90000>;
1732 * Shared interrupt 0 is routed only to AON/SPE, so
1741 reg = <0x0 0xc1e0000 0x0 0x10000>;
1750 reg = <0x0 0xc240000 0x0 0x100>;
1753 #size-cells = <0>;
1769 reg = <0x0 0xc250000 0x0 0x100>;
1772 #size-cells = <0>;
1782 dmas = <&gpcdma 0>, <&gpcdma 0>;
1788 reg = <0x0 0x0c260000 0x0 0x1000>;
1791 #size-cells = <0>;
1807 reg = <0x0 0x0c2a0000 0x0 0x10000>;
1818 reg = <0x0 0x0c2f0000 0x0 0x1000>,
1819 <0x0 0x0c2f1000 0x0 0x1000>;
1828 gpio-ranges = <&pinmux_aon 0 0 32>;
1833 reg = <0x0 0xc300000 0x0 0x4000>;
1838 reg = <0x0 0xc340000 0x0 0x10000>;
1848 reg = <0x0 0x0c360000 0x0 0x10000>,
1849 <0x0 0x0c370000 0x0 0x10000>,
1850 <0x0 0x0c380000 0x0 0x10000>,
1851 <0x0 0x0c390000 0x0 0x10000>,
1852 <0x0 0x0c3a0000 0x0 0x10000>;
1881 reg = <0x0 0xc600000 0x0 0x40000>;
1888 reg = <0x0 0xd600000 0x0 0x40000>;
1895 reg = <0x0 0xde00000 0x0 0x40000>;
1902 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1909 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
1910 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
1921 reg = <0x0 0x10000000 0x0 0x1000000>;
2051 stream-match-mask = <0x7f80>;
2061 reg = <0x0 0x12000000 0x0 0x1000000>,
2062 <0x0 0x11000000 0x0 0x1000000>;
2193 stream-match-mask = <0x7f80>;
2203 reg = <0x0 0x13a00000 0x0 0x400000>;
2210 reg = <0x0 0x13e00000 0x0 0x10000>,
2211 <0x0 0x13e10000 0x0 0x10000>,
2212 <0x0 0x13e40000 0x0 0x10000>;
2230 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
2238 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2257 reg = <0x0 0x15340000 0x0 0x00040000>;
2274 reg = <0x0 0x15480000 0x0 0x00040000>;
2294 nvidia,bl-manifest-offset = <0>;
2295 nvidia,bl-data-offset = <0>;
2296 nvidia,bl-code-offset = <0>;
2297 nvidia,os-manifest-offset = <0>;
2298 nvidia,os-data-offset = <0>;
2299 nvidia,os-code-offset = <0>;
2312 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
2313 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2314 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2315 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2316 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2338 interrupt-map-mask = <0 0 0 0>;
2339 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2347 bus-range = <0x0 0xff>;
2349 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2350 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2351 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2356 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2357 iommu-map-mask = <0x0>;
2366 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
2367 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2368 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2369 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2370 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2392 interrupt-map-mask = <0 0 0 0>;
2393 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2401 bus-range = <0x0 0xff>;
2403 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
2404 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2405 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2410 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2411 iommu-map-mask = <0x0>;
2420 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2421 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2422 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2423 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2424 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2446 interrupt-map-mask = <0 0 0 0>;
2447 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2455 bus-range = <0x0 0xff>;
2457 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2458 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2459 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2464 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2465 iommu-map-mask = <0x0>;
2474 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2475 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2476 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2477 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2502 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2503 iommu-map-mask = <0x0>;
2512 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2513 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2514 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2515 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
2516 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
2538 interrupt-map-mask = <0 0 0 0>;
2539 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2547 bus-range = <0x0 0xff>;
2549 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2550 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2551 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2556 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2557 iommu-map-mask = <0x0>;
2566 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2567 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2568 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2569 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
2570 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
2592 interrupt-map-mask = <0 0 0 0>;
2593 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2601 bus-range = <0x0 0xff>;
2603 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2604 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2605 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2610 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2611 iommu-map-mask = <0x0>;
2620 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2621 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2622 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2623 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
2624 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2646 interrupt-map-mask = <0 0 0 0>;
2647 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2655 bus-range = <0x0 0xff>;
2657 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2658 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2659 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2664 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2665 iommu-map-mask = <0x0>;
2674 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2675 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2676 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2677 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2678 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2700 interrupt-map-mask = <0 0 0 0>;
2701 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2709 bus-range = <0x0 0xff>;
2711 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2712 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2713 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2718 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2719 iommu-map-mask = <0x0>;
2728 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2729 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2730 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2731 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2732 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2740 linux,pci-domain = <0>;
2754 interrupt-map-mask = <0 0 0 0>;
2755 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2757 nvidia,bpmp = <&bpmp 0>;
2763 bus-range = <0x0 0xff>;
2765 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2766 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2767 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2772 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2773 iommu-map-mask = <0x0>;
2782 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2783 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2784 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2785 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2786 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2808 interrupt-map-mask = <0 0 0 0>;
2809 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2817 bus-range = <0x0 0xff>;
2819 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
2820 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2821 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2826 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2827 iommu-map-mask = <0x0>;
2836 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2837 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2838 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2839 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2864 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2865 iommu-map-mask = <0x0>;
2874 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2875 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2876 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2877 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2878 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2900 interrupt-map-mask = <0 0 0 0>;
2901 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2909 bus-range = <0x0 0xff>;
2911 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2912 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2913 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2918 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2919 iommu-map-mask = <0x0>;
2928 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2929 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2930 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2931 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2956 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2957 iommu-map-mask = <0x0>;
2966 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2967 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2968 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2969 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2970 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2992 interrupt-map-mask = <0 0 0 0>;
2993 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
3001 bus-range = <0x0 0xff>;
3003 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
3004 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
3005 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
3010 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3011 iommu-map-mask = <0x0>;
3020 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
3021 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
3022 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
3023 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
3048 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3049 iommu-map-mask = <0x0>;
3058 reg = <0x0 0x40000000 0x0 0x80000>;
3062 ranges = <0x0 0x0 0x40000000 0x80000>;
3067 reg = <0x70000 0x1000>;
3073 reg = <0x71000 0x1000>;
3098 #size-cells = <0>;
3109 #size-cells = <0>;
3111 cpu0_0: cpu@0 {
3114 reg = <0x00000>;
3133 reg = <0x00100>;
3152 reg = <0x00200>;
3171 reg = <0x00300>;
3190 reg = <0x10000>;
3209 reg = <0x10100>;
3228 reg = <0x10200>;
3247 reg = <0x10300>;
3266 reg = <0x20000>;
3285 reg = <0x20100>;
3304 reg = <0x20200>;
3323 reg = <0x20300>;
3575 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3590 assigned-clock-parents = <0>,