Lines Matching +full:0 +full:x54040000
21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
54 pinctrl-0 = <&pex_dpd_disable>;
59 pci@1,0 {
61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
73 pci@2,0 {
75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
90 reg = <0x0 0x50000000 0x0 0x00034000>;
102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
108 reg = <0x0 0x54040000 0x0 0x00040000>;
135 #size-cells = <0>;
141 reg = <0x0 0x54080000 0x0 0x700>;
153 ranges = <0x0 0x0 0x54080000 0x2000>;
157 reg = <0x838 0x1300>;
183 reg = <0x0 0x54100000 0x0 0x00040000>;
194 reg = <0x0 0x54200000 0x0 0x00040000>;
204 nvidia,head = <0>;
209 reg = <0x0 0x54240000 0x0 0x00040000>;
224 reg = <0x0 0x54300000 0x0 0x00040000>;
232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
237 #size-cells = <0>;
242 reg = <0x0 0x54340000 0x0 0x00040000>;
255 reg = <0x0 0x54380000 0x0 0x00040000>;
261 reg = <0x0 0x54400000 0x0 0x00040000>;
269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
274 #size-cells = <0>;
279 reg = <0x0 0x54480000 0x0 0x00040000>;
285 reg = <0x0 0x544c0000 0x0 0x00040000>;
291 reg = <0x0 0x54500000 0x0 0x00040000>;
302 reg = <0x0 0x54540000 0x0 0x00040000>;
312 pinctrl-0 = <&state_dpaux_aux>;
322 reg = <0x0 0x54580000 0x0 0x00040000>;
332 pinctrl-0 = <&state_dpaux1_aux>;
342 reg = <0x0 0x545c0000 0x0 0x00040000>;
369 #size-cells = <0>;
375 reg = <0x0 0x54600000 0x0 0x00040000>;
385 reg = <0x0 0x54680000 0x0 0x00040000>;
395 reg = <0x0 0x546c0000 0x0 0x00040000>;
406 #size-cells = <0>;
414 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x2000>;
425 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01000000>;
444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40>; /* senary controller */
457 reg = <0x0 0x60005000 0x0 0x400>;
459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
478 reg = <0x0 0x60006000 0x0 0x1000>;
485 reg = <0x0 0x60007000 0x0 0x1000>;
490 reg = <0x0 0x6000d000 0x0 0x1000>;
507 reg = <0x0 0x60020000 0x0 0x1400>;
549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
561 nvidia,pull-down-strength = <0x4>;
562 nvidia,pull-up-strength = <0x3>;
569 nvidia,pull-down-strength = <0x8>;
570 nvidia,pull-up-strength = <0x8>;
577 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up-strength = <0x10>;
585 nvidia,pull-down-strength = <0x4>;
586 nvidia,pull-up-strength = <0x3>;
593 nvidia,pull-down-strength = <0x8>;
594 nvidia,pull-up-strength = <0x8>;
601 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up-strength = <0x10>;
617 reg = <0x0 0x70006000 0x0 0x40>;
629 reg = <0x0 0x70006040 0x0 0x40>;
641 reg = <0x0 0x70006200 0x0 0x40>;
653 reg = <0x0 0x70006300 0x0 0x40>;
665 reg = <0x0 0x7000a000 0x0 0x100>;
675 reg = <0x0 0x7000c000 0x0 0x100>;
678 #size-cells = <0>;
690 reg = <0x0 0x7000c400 0x0 0x100>;
693 #size-cells = <0>;
705 reg = <0x0 0x7000c500 0x0 0x100>;
708 #size-cells = <0>;
720 reg = <0x0 0x7000c700 0x0 0x100>;
723 #size-cells = <0>;
730 pinctrl-0 = <&state_dpaux1_i2c>;
738 reg = <0x0 0x7000d000 0x0 0x100>;
741 #size-cells = <0>;
753 reg = <0x0 0x7000d100 0x0 0x100>;
756 #size-cells = <0>;
763 pinctrl-0 = <&state_dpaux_i2c>;
771 reg = <0x0 0x7000d400 0x0 0x200>;
774 #size-cells = <0>;
786 reg = <0x0 0x7000d600 0x0 0x200>;
789 #size-cells = <0>;
801 reg = <0x0 0x7000d800 0x0 0x200>;
804 #size-cells = <0>;
816 reg = <0x0 0x7000da00 0x0 0x200>;
819 #size-cells = <0>;
831 reg = <0x0 0x7000e000 0x0 0x100>;
840 reg = <0x0 0x7000e400 0x0 0x400>;
884 #power-domain-cells = <0>;
905 #power-domain-cells = <0>;
914 #power-domain-cells = <0>;
920 #power-domain-cells = <0>;
926 #power-domain-cells = <0>;
932 #power-domain-cells = <0>;
938 #power-domain-cells = <0>;
945 reg = <0x0 0x7000f800 0x0 0x400>;
954 reg = <0x0 0x70019000 0x0 0x1000>;
966 reg = <0x0 0x7001b000 0x0 0x1000>,
967 <0x0 0x7001e000 0x0 0x1000>,
968 <0x0 0x7001f000 0x0 0x1000>;
978 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
994 reg = <0x0 0x70030000 0x0 0x10000>;
1010 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1000>;
1047 reg = <0x0 0x7009f000 0x0 0x1000>;
1062 usb2-0 {
1064 #phy-cells = <0>;
1069 #phy-cells = <0>;
1074 #phy-cells = <0>;
1079 #phy-cells = <0>;
1090 hsic-0 {
1092 #phy-cells = <0>;
1097 #phy-cells = <0>;
1110 pcie-0 {
1112 #phy-cells = <0>;
1117 #phy-cells = <0>;
1122 #phy-cells = <0>;
1127 #phy-cells = <0>;
1132 #phy-cells = <0>;
1137 #phy-cells = <0>;
1142 #phy-cells = <0>;
1155 sata-0 {
1157 #phy-cells = <0>;
1164 usb2-0 {
1180 hsic-0 {
1184 usb3-0 {
1204 reg = <0x0 0x700b0000 0x0 0x200>;
1213 pinctrl-0 = <&sdmmc1_3v3>;
1217 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>;
1233 reg = <0x0 0x700b0200 0x0 0x200>;
1241 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>;
1251 reg = <0x0 0x700b0400 0x0 0x200>;
1260 pinctrl-0 = <&sdmmc3_3v3>;
1264 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>;
1275 reg = <0x0 0x700b0600 0x0 0x200>;
1283 pinctrl-0 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>;
1299 reg = <0x0 0x700d0000 0x0 0x8000>,
1300 <0x0 0x700d8000 0x0 0x1000>,
1301 <0x0 0x700d9000 0x0 0x1000>;
1318 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1319 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1344 reg = <0x0 0x700e3000 0x0 0x100>;
1353 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1365 #clock-cells = <0>;
1378 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1383 reg = <0x702d0800 0x800>;
1391 ranges = <0x702d0000 0x702d0000 0x0000e400>;
1396 reg = <0x702d0000 0x800>;
1421 #size-cells = <0>;
1423 admaif1_port: port@0 {
1424 reg = <0>;
1507 reg = <0x702d1000 0x100>;
1520 reg = <0x702d1100 0x100>;
1533 reg = <0x702d1200 0x100>;
1546 reg = <0x702d1300 0x100>;
1559 reg = <0x702d1400 0x100>;
1572 reg = <0x702d2000 0x200>;
1579 reg = <0x702d2200 0x200>;
1586 reg = <0x702d2400 0x200>;
1593 reg = <0x702d2600 0x200>;
1600 reg = <0x702d3000 0x100>;
1607 reg = <0x702d3100 0x100>;
1614 reg = <0x702d3800 0x100>;
1621 reg = <0x702d3900 0x100>;
1628 reg = <0x702d4000 0x100>;
1640 reg = <0x702d4100 0x100>;
1652 reg = <0x702d4200 0x100>;
1664 reg = <0x702d8000 0x100>;
1673 reg = <0x702d8100 0x100>;
1678 reg = <0x702d8200 0x200>;
1684 reg = <0x702d8400 0x100>;
1693 reg = <0x702d8500 0x100>;
1698 reg = <0x702d8600 0x200>;
1704 reg = <0x702da000 0x200>;
1711 reg = <0x702da200 0x200>;
1718 reg = <0x702dbb00 0x800>;
1725 #size-cells = <0>;
1727 port@0 {
1728 reg = <0x0>;
1736 reg = <0x1>;
1744 reg = <0x2>;
1752 reg = <0x3>;
1760 reg = <0x4>;
1766 reg = <0x5>;
1774 reg = <0x6>;
1782 reg = <0x7>;
1790 reg = <0x8>;
1798 reg = <0x9>;
1809 reg = <0x702e2000 0x2000>;
1843 reg = <0x702f9000 0x1000>,
1844 <0x702fa000 0x2000>;
1854 reg = <0x0 0x70410000 0x0 0x1000>;
1857 #size-cells = <0>;
1869 reg = <0x0 0x7d000000 0x0 0x4000>;
1882 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4000>;
1891 nvidia,hssync-start-delay = <0>;
1896 nvidia,xcvr-lsfslew = <0>;
1907 reg = <0x0 0x7d004000 0x0 0x4000>;
1920 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4000>;
1929 nvidia,hssync-start-delay = <0>;
1934 nvidia,xcvr-lsfslew = <0>;
1944 #size-cells = <0>;
1946 cpu@0 {
1949 reg = <0>;
1989 arm,psci-suspend-param = <0x40000007>;
2012 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2026 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2033 polling-delay = <0>;
2041 hysteresis = <0>;
2061 polling-delay-passive = <0>;
2062 polling-delay = <0>;
2088 hysteresis = <0>;
2095 cooling-device = <&emc 0 0>;
2108 polling-delay = <0>;
2116 hysteresis = <0>;
2136 polling-delay-passive = <0>;
2137 polling-delay = <0>;
2145 hysteresis = <0>;