Lines Matching +full:0 +full:x3aa0000
20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
107 <0x0 0x23b0000 0x0 0x1000>,
108 <0x0 0x23c0000 0x0 0x1000>,
109 <0x0 0x23d0000 0x0 0x1000>,
110 <0x0 0x23e0000 0x0 0x1000>;
116 reg = <0x0 0x2430000 0x0 0x17000>;
146 reg = <0x0 0x02490000 0x0 0x10000>;
164 snps,burst-map = <0x7>;
172 reg = <0x0 0x2600000 0x0 0x210000>;
210 dma-channel-mask = <0xfffffffe>;
225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
230 reg = <0x0 0x02900800 0x0 0x800>;
240 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
245 reg = <0x0 0x2901000 0x0 0x100>;
259 reg = <0x0 0x2901100 0x0 0x100>;
273 reg = <0x0 0x2901200 0x0 0x100>;
287 reg = <0x0 0x2901300 0x0 0x100>;
301 reg = <0x0 0x2901400 0x0 0x100>;
315 reg = <0x0 0x2901500 0x0 0x100>;
329 reg = <0x0 0x2902000 0x0 0x200>;
337 reg = <0x0 0x2902200 0x0 0x200>;
345 reg = <0x0 0x2902400 0x0 0x200>;
353 reg = <0x0 0x2902600 0x0 0x200>;
360 reg = <0x0 0x2903000 0x0 0x100>;
367 reg = <0x0 0x2903100 0x0 0x100>;
374 reg = <0x0 0x2903200 0x0 0x100>;
381 reg = <0x0 0x2903300 0x0 0x100>;
389 reg = <0x0 0x2903800 0x0 0x100>;
397 reg = <0x0 0x2903900 0x0 0x100>;
405 reg = <0x0 0x2903a00 0x0 0x100>;
413 reg = <0x0 0x2903b00 0x0 0x100>;
421 reg = <0x0 0x2904000 0x0 0x100>;
434 reg = <0x0 0x2904100 0x0 0x100>;
447 reg = <0x0 0x2904200 0x0 0x100>;
460 reg = <0x0 0x2904300 0x0 0x100>;
473 reg = <0x0 0x2905000 0x0 0x100>;
486 reg = <0x0 0x2905100 0x0 0x100>;
499 reg = <0x0 0x2908000 0x0 0x100>;
510 reg = <0x0 0x2908100 0x0 0x100>;
516 reg = <0x0 0x2908200 0x0 0x200>;
523 reg = <0x0 0x290a000 0x0 0x200>;
531 reg = <0x0 0x290a200 0x0 0x200>;
539 reg = <0x0 0x290bb00 0x0 0x800>;
547 reg = <0x0 0x0290f000 0x0 0x1000>;
598 reg = <0x0 0x2910000 0x0 0x2000>;
607 reg = <0x0 0x02930000 0x0 0x20000>;
609 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
652 reg = <0x0 0x02a41000 0x0 0x1000>,
653 <0x0 0x02a42000 0x0 0x2000>;
665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
666 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
667 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
668 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
669 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
670 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
671 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
672 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
673 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
674 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
675 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
676 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
677 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
678 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
679 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
680 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
681 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
682 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
692 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
693 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
694 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
709 * Limit the DMA range for memory clients to [38:0].
711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
715 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x01780000 0x0 0x80000>;
721 #interconnect-cells = <0>;
729 reg = <0x0 0x03010000 0x0 0x000e0000>;
730 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
745 reg = <0x0 0x03100000 0x0 0x40>;
755 reg = <0x0 0x03110000 0x0 0x40>;
765 reg = <0x0 0x03130000 0x0 0x40>;
777 reg = <0x0 0x03140000 0x0 0x40>;
789 reg = <0x0 0x03150000 0x0 0x40>;
801 reg = <0x0 0x03160000 0x0 0x10000>;
804 #size-cells = <0>;
816 reg = <0x0 0x03170000 0x0 0x40>;
828 reg = <0x0 0x03180000 0x0 0x10000>;
831 #size-cells = <0>;
844 reg = <0x0 0x03190000 0x0 0x10000>;
847 #size-cells = <0>;
852 pinctrl-0 = <&state_dpaux1_i2c>;
863 reg = <0x0 0x031b0000 0x0 0x10000>;
866 #size-cells = <0>;
871 pinctrl-0 = <&state_dpaux0_i2c>;
882 reg = <0x0 0x031c0000 0x0 0x10000>;
885 #size-cells = <0>;
890 pinctrl-0 = <&state_dpaux2_i2c>;
901 reg = <0x0 0x031e0000 0x0 0x10000>;
904 #size-cells = <0>;
909 pinctrl-0 = <&state_dpaux3_i2c>;
919 reg = <0x0 0x3270000 0x0 0x1000>;
922 #size-cells = <0>;
933 reg = <0x0 0x3280000 0x0 0x10000>;
944 reg = <0x0 0x3290000 0x0 0x10000>;
955 reg = <0x0 0x32a0000 0x0 0x10000>;
966 reg = <0x0 0x32c0000 0x0 0x10000>;
977 reg = <0x0 0x32d0000 0x0 0x10000>;
988 reg = <0x0 0x32e0000 0x0 0x10000>;
999 reg = <0x0 0x32f0000 0x0 0x10000>;
1009 reg = <0x0 0x3300000 0x0 0x1000>;
1012 #size-cells = <0>;
1022 reg = <0x0 0x03400000 0x0 0x10000>;
1039 pinctrl-0 = <&sdmmc1_3v3>;
1042 <0x07>;
1044 <0x07>;
1045 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1047 <0x07>;
1048 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = <0x5>;
1061 reg = <0x0 0x03440000 0x0 0x10000>;
1078 pinctrl-0 = <&sdmmc3_3v3>;
1080 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1084 <0x07>;
1085 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1087 <0x07>;
1088 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = <0x5>;
1101 reg = <0x0 0x03460000 0x0 0x10000>;
1116 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1120 <0x0a>;
1121 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1123 <0x0a>;
1124 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = <0x14>;
1138 reg = <0x0 0x3510000 0x0 0x10000>;
1157 reg = <0x0 0x03520000 0x0 0x1000>,
1158 <0x0 0x03540000 0x0 0x1000>;
1173 usb2-0 {
1176 #phy-cells = <0>;
1182 #phy-cells = <0>;
1188 #phy-cells = <0>;
1194 #phy-cells = <0>;
1201 usb3-0 {
1204 #phy-cells = <0>;
1210 #phy-cells = <0>;
1216 #phy-cells = <0>;
1222 #phy-cells = <0>;
1229 usb2-0 {
1245 usb3-0 {
1265 reg = <0x0 0x03550000 0x0 0x8000>,
1266 <0x0 0x03558000 0x0 0x1000>;
1288 reg = <0x0 0x03610000 0x0 0x40000>,
1289 <0x0 0x03600000 0x0 0x10000>;
1323 reg = <0x0 0x03820000 0x0 0x10000>;
1332 reg = <0x0 0x03881000 0x0 0x1000>,
1333 <0x0 0x03882000 0x0 0x2000>,
1334 <0x0 0x03884000 0x0 0x2000>,
1335 <0x0 0x03886000 0x0 0x2000>;
1343 reg = <0x0 0x03960000 0x0 0x10000>;
1352 reg = <0x0 0x3aa0000 0x0 0x10000>;
1362 reg = <0x0 0x03c00000 0x0 0xa0000>;
1380 reg = <0x0 0x03e10000 0x0 0x10000>;
1383 #phy-cells = <0>;
1388 reg = <0x0 0x03e20000 0x0 0x10000>;
1391 #phy-cells = <0>;
1396 reg = <0x0 0x03e30000 0x0 0x10000>;
1399 #phy-cells = <0>;
1404 reg = <0x0 0x03e40000 0x0 0x10000>;
1407 #phy-cells = <0>;
1412 reg = <0x0 0x03e50000 0x0 0x10000>;
1415 #phy-cells = <0>;
1420 reg = <0x0 0x03e60000 0x0 0x10000>;
1423 #phy-cells = <0>;
1428 reg = <0x0 0x03e70000 0x0 0x10000>;
1431 #phy-cells = <0>;
1436 reg = <0x0 0x03e80000 0x0 0x10000>;
1439 #phy-cells = <0>;
1444 reg = <0x0 0x03e90000 0x0 0x10000>;
1447 #phy-cells = <0>;
1452 reg = <0x0 0x03ea0000 0x0 0x10000>;
1455 #phy-cells = <0>;
1460 reg = <0x0 0x03eb0000 0x0 0x10000>;
1463 #phy-cells = <0>;
1468 reg = <0x0 0x03ec0000 0x0 0x10000>;
1471 #phy-cells = <0>;
1476 reg = <0x0 0x03ed0000 0x0 0x10000>;
1479 #phy-cells = <0>;
1484 reg = <0x0 0x03ee0000 0x0 0x10000>;
1487 #phy-cells = <0>;
1492 reg = <0x0 0x03ef0000 0x0 0x10000>;
1495 #phy-cells = <0>;
1500 reg = <0x0 0x03f00000 0x0 0x10000>;
1503 #phy-cells = <0>;
1508 reg = <0x0 0x03f10000 0x0 0x10000>;
1511 #phy-cells = <0>;
1516 reg = <0x0 0x03f20000 0x0 0x10000>;
1519 #phy-cells = <0>;
1524 reg = <0x0 0x03f30000 0x0 0x10000>;
1527 #phy-cells = <0>;
1532 reg = <0x0 0x03f40000 0x0 0x10000>;
1535 #phy-cells = <0>;
1540 reg = <0x0 0xb600000 0x0 0x1000>;
1550 reg = <0x0 0xbe00000 0x0 0x1000>;
1560 reg = <0x0 0x0c150000 0x0 0x90000>;
1566 * Shared interrupt 0 is routed only to AON/SPE, so
1575 reg = <0x0 0xc1e0000 0x0 0x10000>;
1585 reg = <0x0 0x0c240000 0x0 0x10000>;
1588 #size-cells = <0>;
1600 reg = <0x0 0x0c250000 0x0 0x10000>;
1603 #size-cells = <0>;
1608 dmas = <&gpcdma 0>, <&gpcdma 0>;
1615 reg = <0x0 0x0c280000 0x0 0x40>;
1627 reg = <0x0 0x0c290000 0x0 0x40>;
1639 reg = <0x0 0x0c2a0000 0x0 0x10000>;
1650 reg = <0x0 0xc2f0000 0x0 0x1000>,
1651 <0x0 0xc2f1000 0x0 0x1000>;
1660 gpio-ranges = <&pinmux_aon 0 0 30>;
1665 reg = <0x0 0xc300000 0x0 0x4000>;
1673 reg = <0x0 0xc340000 0x0 0x10000>;
1683 reg = <0x0 0x0c360000 0x0 0x10000>,
1684 <0x0 0x0c370000 0x0 0x10000>,
1685 <0x0 0x0c380000 0x0 0x10000>,
1686 <0x0 0x0c390000 0x0 0x10000>,
1687 <0x0 0x0c3a0000 0x0 0x10000>;
1716 reg = <0x0 0xc600000 0x0 0x1000>;
1725 reg = <0x0 0xd600000 0x0 0x1000>;
1735 reg = <0x0 0x10000000 0x0 0x800000>;
1801 stream-match-mask = <0x7f80>;
1811 reg = <0x0 0x12000000 0x0 0x800000>,
1812 <0x0 0x11000000 0x0 0x800000>;
1879 stream-match-mask = <0x7f80>;
1889 reg = <0x0 0x13e00000 0x0 0x10000>,
1890 <0x0 0x13e10000 0x0 0x10000>;
1902 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>;
1910 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1921 reg = <0x0 0x15140000 0x0 0x00040000>;
1935 nvidia,host1x-class = <0xf5>;
1940 reg = <0x0 0x15200000 0x0 0x00040000>;
1959 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>;
1963 reg = <0x0 0x15200000 0x0 0x10000>;
1976 nvidia,head = <0>;
1981 reg = <0x0 0x15210000 0x0 0x10000>;
1999 reg = <0x0 0x15220000 0x0 0x10000>;
2017 reg = <0x0 0x15230000 0x0 0x10000>;
2036 reg = <0x0 0x15340000 0x0 0x00040000>;
2053 reg = <0x0 0x15380000 0x0 0x40000>;
2069 reg = <0x0 0x15480000 0x0 0x00040000>;
2083 nvidia,host1x-class = <0xf0>;
2088 reg = <0x0 0x154c0000 0x0 0x40000>;
2102 nvidia,host1x-class = <0x21>;
2107 reg = <0x0 0x155c0000 0x0 0x10000>;
2135 #size-cells = <0>;
2141 reg = <0x0 0x155d0000 0x0 0x10000>;
2169 #size-cells = <0>;
2175 reg = <0x0 0x155e0000 0x0 0x10000>;
2203 #size-cells = <0>;
2209 reg = <0x0 0x155f0000 0x0 0x10000>;
2237 #size-cells = <0>;
2243 reg = <0x0 0x15a80000 0x0 0x00040000>;
2257 nvidia,host1x-class = <0x22>;
2262 reg = <0x0 0x15b00000 0x0 0x40000>;
2274 pinctrl-0 = <&state_dpaux0_aux>;
2281 nvidia,interface = <0>;
2286 reg = <0x0 0x15b40000 0x0 0x40000>;
2298 pinctrl-0 = <&state_dpaux1_aux>;
2310 reg = <0x0 0x15b80000 0x0 0x40000>;
2322 pinctrl-0 = <&state_dpaux2_aux>;
2334 reg = <0x0 0x15bc0000 0x0 0x40000>;
2346 pinctrl-0 = <&state_dpaux3_aux>;
2360 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2361 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2362 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2363 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2386 interrupt-map-mask = <0 0 0 0>;
2387 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2395 bus-range = <0x0 0xff>;
2397 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2398 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2399 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2404 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2405 iommu-map-mask = <0x0>;
2412 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2413 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2414 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2415 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
2438 interrupt-map-mask = <0 0 0 0>;
2439 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2447 bus-range = <0x0 0xff>;
2449 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2450 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2451 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2456 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2457 iommu-map-mask = <0x0>;
2464 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2465 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2466 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2467 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
2490 interrupt-map-mask = <0 0 0 0>;
2491 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2499 bus-range = <0x0 0xff>;
2501 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2502 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
2503 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2508 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2509 iommu-map-mask = <0x0>;
2516 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2517 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2518 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2519 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
2542 interrupt-map-mask = <0 0 0 0>;
2543 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2551 bus-range = <0x0 0xff>;
2553 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2554 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2555 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2560 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2561 iommu-map-mask = <0x0>;
2568 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2569 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2570 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2571 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2599 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2600 iommu-map-mask = <0x0>;
2607 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2608 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2609 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2610 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2619 linux,pci-domain = <0>;
2633 interrupt-map-mask = <0 0 0 0>;
2634 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2636 nvidia,bpmp = <&bpmp 0>;
2642 bus-range = <0x0 0xff>;
2644 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2645 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2646 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2651 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2652 iommu-map-mask = <0x0>;
2659 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2660 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2661 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2662 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2681 nvidia,bpmp = <&bpmp 0>;
2690 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2691 iommu-map-mask = <0x0>;
2698 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2699 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2700 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2701 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2713 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>;
2729 interrupt-map-mask = <0 0 0 0>;
2730 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2736 bus-range = <0x0 0xff>;
2738 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2739 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2740 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2745 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2746 iommu-map-mask = <0x0>;
2753 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2754 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2755 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2756 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2766 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>;
2787 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2788 iommu-map-mask = <0x0>;
2794 reg = <0x0 0x17000000 0x0 0x1000000>,
2795 <0x0 0x18000000 0x0 0x1000000>;
2820 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2829 reg = <0x0 0x40000000 0x0 0x50000>;
2833 ranges = <0x0 0x0 0x40000000 0x50000>;
2838 reg = <0x4e000 0x1000>;
2844 reg = <0x4f000 0x1000>;
2869 #size-cells = <0>;
2882 #size-cells = <0>;
2884 cpu0_0: cpu@0 {
2887 reg = <0x000>;
2901 reg = <0x001>;
2915 reg = <0x100>;
2929 reg = <0x101>;
2943 reg = <0x200>;
2957 reg = <0x201>;
2971 reg = <0x300>;
2985 reg = <0x301>;
3110 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3124 assigned-clock-parents = <0>,