Lines Matching +full:0 +full:x40700000
22 #size-cells = <0>;
24 cpu0: cpu@0 {
27 reg = <0x0 0x0>;
35 reg = <0x0 0x1>;
44 cache-size = <0x80000>;
55 reg = <0x0 0x50801000 0 0x1000>, /* GICD */
56 <0x0 0x50802000 0 0x2000>, /* GICC */
57 <0x0 0x50804000 0 0x2000>, /* GICH */
58 <0x0 0x50806000 0 0x2000>; /* GICV */
62 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
87 reg = <0x0 0x40460000 0x0 0x200>;
93 reg = <0x00000000 0x40460200 0x0 0x100>;
100 reg = <0x0 0x40700000 0x0 0x100>;
108 reg = <0x0 0x40710000 0x0 0x100>;
116 reg = <0x0 0x40720000 0x0 0x100>;
124 reg = <0x0 0x40730000 0x0 0x100>;
132 reg = <0x0 0x40740000 0x0 0x100>;
140 reg = <0x0 0x40750000 0x0 0x100>;
148 reg = <0x0 0x40760000 0x0 0x100>;
156 reg = <0x0 0x40770000 0x0 0x100>;
164 reg = <0x0 0x40780000 0x0 0x100>;
172 reg = <0x0 0x40790000 0x0 0x100>;
180 reg = <0x0 0x407a0000 0x0 0x100>;
188 reg = <0x0 0x407b0000 0x0 0x100>;
196 reg = <0x0 0x407c0000 0x0 0x100>;
204 reg = <0x0 0x407d0000 0x0 0x100>;
212 reg = <0x0 0x407e0000 0x0 0x100>;
220 reg = <0x0 0x407f0000 0x0 0x100>;
228 reg = <0x0 0x40880000 0x0 0x100>;