Lines Matching +full:0 +full:x5d0000
28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
118 <0x6 0x00200000 0x2000>, /* GICC */
119 <0x6 0x00210000 0x2000>, /* GICV */
120 <0x6 0x00220000 0x2000>; /* GICH */
127 reg = <0x6 0x00000000 0xd0>;
130 #mux-control-cells = <0>;
133 * SPI: value 9 - (SIMC,SIBM) = 0b1001
134 * SPI2: value 6 - (SIBM,SIMC) = 0b0110
136 mux-reg-masks = <0x88 0xf0>;
142 reg = <0x6 0x11010008 0x4>;
149 pinctrl-0 = <&uart_pins>;
152 reg = <0x6 0x00100000 0x20>;
162 pinctrl-0 = <&uart2_pins>;
165 reg = <0x6 0x00102000 0x20>;
176 #size-cells = <0>;
178 reg = <0x6 0x00104000 0x40>;
189 reg = <0x6 0x00105000 0x1000>;
198 reg = <0x6 0x00800000 0x1000>;
199 pinctrl-0 = <&emmc_pins>;
211 reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
214 gpio-ranges = <&gpio 0 0 64>;
302 #size-cells = <0>;
306 pinctrl-0 = <&sgpio0_pins>;
308 resets = <&reset 0>;
310 reg = <0x6 0x1101036c 0x100>;
311 sgpio_in0: gpio@0 {
313 reg = <0>;
332 #size-cells = <0>;
336 pinctrl-0 = <&sgpio1_pins>;
338 resets = <&reset 0>;
340 reg = <0x6 0x11010484 0x100>;
341 sgpio_in1: gpio@0 {
343 reg = <0>;
362 #size-cells = <0>;
366 pinctrl-0 = <&sgpio2_pins>;
368 resets = <&reset 0>;
370 reg = <0x6 0x1101059c 0x100>;
371 sgpio_in2: gpio@0 {
372 reg = <0>;
393 pinctrl-0 = <&i2c_pins>;
395 reg = <0x6 0x00101000 0x100>;
397 #size-cells = <0>;
407 pinctrl-0 = <&i2c2_pins>;
409 reg = <0x6 0x00103000 0x100>;
411 #size-cells = <0>;
420 reg = <0x6 0x10508110 0xc>;
421 #thermal-sensor-cells = <0>;
429 #size-cells = <0>;
430 reg = <0x6 0x110102b0 0x24>;
436 pinctrl-0 = <&miim1_pins>;
439 #size-cells = <0>;
440 reg = <0x6 0x110102d4 0x24>;
446 pinctrl-0 = <&miim2_pins>;
449 #size-cells = <0>;
450 reg = <0x6 0x110102d4 0x24>;
456 pinctrl-0 = <&miim3_pins>;
459 #size-cells = <0>;
460 reg = <0x6 0x1101031c 0x24>;
467 reg = <0x6 0x10808000 0x5d0000>;
472 reg = <0x6 0 0x401000>,
473 <0x6 0x10004000 0x7fc000>,
474 <0x6 0x11010000 0xaf0000>;
480 resets = <&reset 0>;