Lines Matching +full:0 +full:x1100000
42 reg = <0 0x40000000 0x2 0x00000000>;
52 * +-----------------------+ 0x43e0_0000
54 * +-----------------------+ 0x43c0_0000
56 * + TZDRAM +--------------+ 0x4340_0000
58 * +-----------------------+ 0x4320_0000
62 reg = <0 0x43200000 0 0x00c00000>;
67 reg = <0 0x50000000 0 0x2900000>;
73 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
79 reg = <0 0x54600000 0x0 0x200000>;
84 reg = <0 0x60000000 0 0x1100000>;
90 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
96 pwms = <&disp_pwm0 0 500000>;
98 brightness-levels = <0 1023>;
105 pwms = <&disp_pwm1 0 500000>;
107 brightness-levels = <0 1023>;
114 #clock-cells = <0>;
119 edp_panel_fixed_3v3: regulator-0 {
127 pinctrl-0 = <&edp_panel_3v3_en_pins>;
138 pinctrl-0 = <&edp_panel_12v_en_pins>;
166 pinctrl-0 = <&pwm0_default_pins>;
178 snps,reset-delays-us = <0 10000 10000>;
182 pinctrl-0 = <ð_default_pins>;
189 #size-cells = <0>;
192 reg = <0x1>;
199 pinctrl-0 = <&i2c0_pins>;
206 pinctrl-0 = <&i2c1_pins>;
212 reg = <0x5d>;
218 pinctrl-0 = <&touch_pins>;
224 pinctrl-0 = <&i2c2_pins>;
231 pinctrl-0 = <&i2c6_pins>;
234 #size-cells = <0>;
239 reg = <0x34>;
245 pinctrl-0 = <&mt6360_pins>;
343 pinctrl-0 = <&mmc0_default_pins>;
353 hs400-ds-delay = <0x14c11>;
361 pinctrl-0 = <&mmc1_default_pins>;
411 mediatek,mic-type-0 = <1>; /* ACC */
418 pinctrl-0 = <&pcie0_default_pins>;
425 pinctrl-0 = <&pcie1_default_pins>;
785 pinctrl-0 = <&spi1_pins>;
787 mediatek,pad-select = <0>;
789 #size-cells = <0>;
793 can0: can@0 {
795 reg = <0>;
805 pinctrl-0 = <&spi2_pins>;
807 mediatek,pad-select = <0>;
809 #size-cells = <0>;
815 #size-cells = <0>;
819 reg = <0x6 SPMI_USID>;
828 regulator-allowed-modes = <0 1 2>;
836 reg = <0x7 SPMI_USID>;
845 regulator-allowed-modes = <0 1 2>;
872 pinctrl-0 = <&uart0_pins>;
878 pinctrl-0 = <&uart1_pins>;