Lines Matching +full:0 +full:x11007000
22 #size-cells = <0>;
24 cluster0_opp: opp-table-0 {
126 cpu0: cpu@0 {
129 reg = <0x0>;
133 i-cache-size = <0x8000>;
136 d-cache-size = <0x8000>;
149 reg = <0x1>;
153 i-cache-size = <0x8000>;
156 d-cache-size = <0x8000>;
169 reg = <0x2>;
173 i-cache-size = <0x8000>;
176 d-cache-size = <0x8000>;
189 reg = <0x3>;
193 i-cache-size = <0x8000>;
196 d-cache-size = <0x8000>;
212 arm,psci-suspend-param = <0x00010001>;
221 arm,psci-suspend-param = <0x01010001>;
230 arm,psci-suspend-param = <0x01010004>;
240 cache-size = <0x80000>;
249 #clock-cells = <0>;
270 reg = <0 0x0c000000 0 0x10000>, /* GICD */
271 <0 0x0c080000 0 0x80000>, /* GICR */
272 <0 0x0c400000 0 0x2000>, /* GICC */
273 <0 0x0c410000 0 0x1000>, /* GICH */
274 <0 0x0c420000 0 0x2000>; /* GICV */
281 reg = <0 0x10000000 0 0x1000>;
287 reg = <0 0x10001000 0 0x1000>;
293 reg = <0 0x10003000 0 0x1000>;
299 reg = <0 0x10005000 0 0x1000>;
304 reg = <0 0x10006000 0 0x1000>;
311 #size-cells = <0>;
322 clock-names = "mm", "mm-0", "mm-1",
324 #power-domain-cells = <0>;
328 #size-cells = <0>;
338 clock-names = "cam-0", "cam-1",
341 #power-domain-cells = <0>;
348 #power-domain-cells = <0>;
354 #power-domain-cells = <0>;
367 clock-names = "apu", "apu-0",
371 #power-domain-cells = <0>;
382 #power-domain-cells = <0>;
390 #power-domain-cells = <0>;
400 #power-domain-cells = <0>;
409 #power-domain-cells = <0>;
417 reg = <0 0x10007000 0 0x100>;
423 reg = <0 0x1000b000 0 0x1000>;
434 reg = <0 0x1000c000 0 0x1000>;
440 reg = <0 0x1000d000 0 0x1000>;
452 reg = <0 0x10010000 0 0x1000>;
462 reg = <0 0x10200000 0 0x2000>;
471 reg = <0 0x10200a80 0 0x20>;
476 reg = <0 0x10205000 0 0x1000>;
484 reg = <0 0x1020e000 0 0x1000>;
490 reg = <0 0x1020f000 0 0x100>;
497 reg = <0 0x11000280 0 0x80>,
498 <0 0x11000300 0 0x80>,
499 <0 0x11000380 0 0x80>,
500 <0 0x11000400 0 0x80>,
501 <0 0x11000580 0 0x80>,
502 <0 0x11000600 0 0x80>;
517 reg = <0 0x11002000 0 0x1000>;
521 dmas = <&apdma 0>, <&apdma 1>;
528 reg = <0 0x11003000 0 0x1000>;
539 reg = <0 0x11004000 0 0x1000>;
550 reg = <0 0x11006000 0 0x1000>;
563 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
569 #size-cells = <0>;
575 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
581 #size-cells = <0>;
587 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
593 #size-cells = <0>;
599 reg = <0 0x1100a000 0 0x100>;
601 #size-cells = <0>;
612 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
618 #size-cells = <0>;
624 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
641 reg = <0 0x11200000 0 0x1000>;
657 reg = <0 0x11230000 0 0x1000>,
658 <0 0x11cd0000 0 0x1000>;
669 reg = <0 0x11240000 0 0x1000>,
670 <0 0x11c90000 0 0x1000>;
681 reg = <0 0x11250000 0 0x1000>,
682 <0 0x11c60000 0 0x1000>;
696 reg = <0 0x112a0000 0 0x1000>;
710 ranges = <0 0 0x11cc0000 0x9000>;
712 u2port0: usb-phy@0 {
713 reg = <0x0 0x400>;
721 reg = <0x1000 0x400>;
731 reg = <0 0x14000000 0 0x1000>;
737 reg = <0 0x14002000 0 0x1000>;
749 reg = <0 0x14003000 0 0x1000>;
755 mediatek,larb-id = <0>;
760 reg = <0 0x15000000 0 0x1000>;
767 reg = <0 0x15001000 0 0x1000>;
778 reg = <0 0x16000000 0 0x1000>;
785 reg = <0 0x16010000 0 0x1000>;
796 reg = <0 0x17000000 0 0x1000>;
803 reg = <0 0x17010000 0 0x1000>;
813 reg = <0 0x19020000 0 0x1000>;
830 #clock-cells = <0>;
835 reg = <0 0x10017000 0 0x100>;